JPS63138727A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS63138727A JPS63138727A JP28615286A JP28615286A JPS63138727A JP S63138727 A JPS63138727 A JP S63138727A JP 28615286 A JP28615286 A JP 28615286A JP 28615286 A JP28615286 A JP 28615286A JP S63138727 A JPS63138727 A JP S63138727A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- resist film
- compound semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 150000001875 compounds Chemical class 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000007772 electrode material Substances 0.000 claims abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 15
- 230000001681 protective effect Effects 0.000 description 6
- 229910005091 Si3N Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関する。より詳細に
は、本発明は、化合物半導体装置の製造方法であって、
容易なアニール処理と容易な素子表面の平坦化を実現し
得る新規な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention is a method for manufacturing a compound semiconductor device, comprising:
The present invention relates to a novel method for manufacturing a semiconductor device that allows easy annealing and easy flattening of the device surface.
従来の技術
ＧａＡｓ等に代表される化合物半導体は、Ｓｌと比較し
て電子移動度が大きく、放射線に対する耐性が高いとい
う特性を有し、動作速度の高い素子を実現することがで
きると言われている。しかしながら、例えばＧａＡｓは
安定な自然酸化膜が存在しないために、動作層上に直接
ショットキゲート電極を形成したＭＥＳＦＥＴを能動素
子として用いている。Conventional technologyCompound semiconductors such as GaAs have characteristics such as higher electron mobility and higher resistance to radiation than Sl, and are said to be able to realize devices with high operating speeds. There is. However, since GaAs, for example, does not have a stable natural oxide film, a MESFET in which a Schottky gate electrode is directly formed on the active layer is used as an active element.
第２図（ａ）乃至（ｆ）は、従来の一般的な化合物半導
体装置の製造方法として、ＭＥＳＦＥＴのゲート電極の
製造方法を、工程を追って描いた図である。FIGS. 2(a) to 2(f) are diagrams depicting a method for manufacturing a gate electrode of a MESFET, step by step, as a conventional general method for manufacturing a compound semiconductor device.
第２図（ａ）は、表面近傍に動作層を形成されたＧａＡ
ｓ基板１の全面に、スパッタ法、蒸着法等によってＷＳ
ｉ等の高融点電極材料を１０００〜２０００人程度の厚
さに堆積して金属層２を形成した様子を示している。Figure 2(a) shows GaA with an active layer formed near the surface.
WS is applied to the entire surface of the s-substrate 1 by sputtering, vapor deposition, etc.
This figure shows how a metal layer 2 is formed by depositing a high melting point electrode material such as I to a thickness of about 1000 to 2000 layers.
この金属層２上で、第２図ら）に示すように、ゲート電
極を形成すべき領域にレジスト膜３を形成した後、第２
図（Ｃ）に示すように、ドライエツチング法、イオンミ
リング法等により、レジスト膜３に覆われていない領域
の不要な金属を除去してゲート電極２ａを形成する。On this metal layer 2, as shown in FIG.
As shown in Figure (C), unnecessary metal in the region not covered by the resist film 3 is removed by dry etching, ion milling, or the like to form the gate electrode 2a.
こうしてゲート電極２ａを形成された基板１に対して、
１５０〜２００ｋＶ程度の電圧で加速されたｎ“不純物
の注入を行い、ソース領域４並びにドレイン領域５を形
成する。With respect to the substrate 1 on which the gate electrode 2a is formed in this way,
A source region 4 and a drain region 5 are formed by implanting n'' impurities accelerated at a voltage of about 150 to 200 kV.
続いて、第２図（ｄ）に示すように、アニールによって
動作層、ソース領域４並びにドレイン領域５の不純物の
活性化を行う。Subsequently, as shown in FIG. 2(d), impurities in the active layer, source region 4, and drain region 5 are activated by annealing.
このように、ソース領域４並びにドレイン領域５が完成
したものにソース電極４ａ並びにドレイン電極５ａを装
着し、ＭＥＳＦＥＴが完成する。A source electrode 4a and a drain electrode 5a are attached to the structure in which the source region 4 and the drain region 5 have been completed in this way, thereby completing the MESFET.
発明の解決しようとする問題点
ところで、ＧａＡｓに代表される■−Ｖ族あるいはＩＩ
−ＶＩ族の化合物半導体は、熱的には必ずしも安定な物
質ではなく、高温下では■族あるいは■族元素の飛散が
生じる。従って、前述のような半導体装置の製造工程に
おいても、アニール工程で高温に曝された場合に、例え
ばＧａＡｓにおける所謂“Ａｓ抜け”を生じる。Problems to be solved by the invention By the way, the ■-V group or II group represented by GaAs
-VI group compound semiconductors are not necessarily thermally stable substances, and group (1) or (2) group elements scatter at high temperatures. Therefore, even in the manufacturing process of the semiconductor device as described above, when exposed to high temperatures in the annealing process, for example, so-called "As omission" occurs in GaAs.
従来の製造工程では、これを防止するために、例えばＧ
ａＡｓの場合は、アニール工程をＡＳＨ３雰囲気中で行
いＡｓの飛散を防止あるいは補充したり、あるいは第２
図（ｆ）に示すようにゲート電極２ａを形成した後に、
プラズマＣＶＤ法等によって窒化保護膜６を基板の全面
に形成し、Ａｓの飛散を防止していた。In conventional manufacturing processes, for example, G
In the case of aAs, the annealing process is performed in an ASH3 atmosphere to prevent or replenish As scattering, or to
After forming the gate electrode 2a as shown in Figure (f),
A nitride protective film 6 was formed on the entire surface of the substrate by plasma CVD or the like to prevent As from scattering.
しかしながら、ＡｓＨｓ雲囲気中でアニール処理を行う
場合、Ａｓ温度あるいは流量等を精密に制御しない限り
、ＧａＡｓ基板の品質を安定に保ことか困難であった。However, when performing annealing treatment in an AsHs cloud environment, it is difficult to maintain stable quality of the GaAs substrate unless the As temperature, flow rate, etc. are precisely controlled.
また、基板上をＳｉ３Ｎ、膜で保護する方法は、半導体
素子の製造プロセスに本来は必要のない保護膜の形成工
程と更にその除去工程とが加わることになり、生産性を
著しく低下する。Furthermore, the method of protecting the substrate with a Si3N film adds an originally unnecessary step of forming a protective film and a step of removing the protective film to the manufacturing process of the semiconductor element, resulting in a significant decrease in productivity.
また、この問題点とは別に、化合物半導体の分野におけ
る一般的な課題として、半導体装置表面の平坦化の問題
がある。In addition to this problem, another common problem in the field of compound semiconductors is the problem of flattening the surface of semiconductor devices.
即ち、高集積度あるいは高速動作の実現のために開発さ
れた多層配線技術を実施するためには、半導体装置表面
が平坦であることが望ましい。何故ならば半導体装置の
表面形状に起伏が激しいと、良好な上層配線の形成が困
難となったり、あるいは層間絶縁膜が容易に裂断するこ
とが多くなるからである。この点、第２図（ｆ）に示す
ようにアニール保護膜を形成してそれを層間絶縁膜に利
用する場合、良好な平坦性が得られない。That is, in order to implement multilayer wiring technology developed to achieve high integration or high-speed operation, it is desirable that the surface of the semiconductor device be flat. This is because if the surface shape of a semiconductor device has severe undulations, it becomes difficult to form a good upper layer wiring, or the interlayer insulating film is often easily torn. In this respect, when an annealing protective film is formed and used as an interlayer insulating film as shown in FIG. 2(f), good flatness cannot be obtained.
そこで、本発明の目的は、上記従来技術の問題点を解消
し、生産性を低下することなく品質の高い化合物半導体
装置を形成すると同時に、素子表面の平坦化を行うこと
のできる新規な化合物半導体の製造方法を提供すること
にある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a novel compound semiconductor that can form high-quality compound semiconductor devices without reducing productivity and at the same time flatten the device surface. The purpose of this invention is to provide a method for manufacturing the same.
問題点を解決するための手段
即ち、本発明に従い、化合物半導体基板上の全面に電極
材料金属膜を形成する工程と、該金属膜上の電極を形成
すべき領域にレジスト膜を形成する工程と、該レジスト
膜に覆われていない領域の金属膜を除去する工程と、金
属を除去された領域に対して不純物を注入する工程と、
該基板をアニールする工程とを少なくとも含む半導体装
置の製造方法であって、前記不純物注入工程後の基板に
対して、前記レジスト膜を残したままＥＣＲプラズマＣ
ＶＤ法によって、基板全体に前記金属膜の厚さまで絶縁
膜を堆積する工程と、該レジスト膜と共に該レジスト膜
上の前記絶縁膜を除去する工程とを前記アニール工程よ
りも前の工程に含むことを特徴とする化合物半導体装置
の製造方法が提供される。Means for solving the problem, that is, according to the present invention, a step of forming an electrode material metal film on the entire surface of a compound semiconductor substrate, and a step of forming a resist film on the region where an electrode is to be formed on the metal film. , a step of removing a metal film in a region not covered with the resist film, and a step of implanting an impurity into the region from which the metal has been removed;
A method of manufacturing a semiconductor device including at least a step of annealing the substrate, wherein the substrate after the impurity implantation step is subjected to ECR plasma C while leaving the resist film.
The step before the annealing step includes a step of depositing an insulating film to the thickness of the metal film over the entire substrate by a VD method, and a step of removing the insulating film on the resist film together with the resist film. A method for manufacturing a compound semiconductor device is provided.
作用
本発明に従う化合物半導体装置の製造方法は、ゲート電
極形成工程後の基板上全面にＥＣＲプラズマＣＶＤ法に
よって絶縁膜を保護膜として形成し、この絶縁膜のゲー
ト電極上の領域をリフトオフ法によって除去することを
その主要な特徴としている。Operation The method for manufacturing a compound semiconductor device according to the present invention includes forming an insulating film as a protective film on the entire surface of the substrate by ECR plasma CVD method after the gate electrode forming step, and removing the region of the insulating film above the gate electrode by lift-off method. Its main feature is to
即ち、ＥＣＲプラズマＣＶＤ法によれば、絶縁膜の形成
は常温あるいはそれに近い低温で行うことができるので
、ゲート電極上のレジストが硬化することがなく、絶縁
膜をリフトオフ法によって除去することが可能となる。That is, according to the ECR plasma CVD method, the insulating film can be formed at room temperature or a low temperature close to it, so the resist on the gate electrode does not harden, and the insulating film can be removed by the lift-off method. becomes.
尚、このゲート電極上の絶縁膜をリフトオフする際に、
ゲート電極上の絶縁膜とゲート電極との間に介在すべき
レジスト膜に、ゲート電極形成の際に用いたレジスト膜
をそのまま利用することによって、工数を大きく増加す
ることなく本発明の方法を実施できる。In addition, when lifting off the insulating film on this gate electrode,
By using the resist film used when forming the gate electrode as it is as the resist film that should be interposed between the insulating film on the gate electrode and the gate electrode, the method of the present invention can be carried out without significantly increasing the number of steps. can.
また、絶縁膜をゲート電極と同じ厚さまで堆積しておく
ことによって、ゲート電極上の絶縁膜を除去した後は、
絶縁膜の表面とゲート電極の表面とが平坦になるので、
特別な工程なしに素子表面の平坦化を実現することがで
きる。In addition, by depositing the insulating film to the same thickness as the gate electrode, after removing the insulating film on the gate electrode,
Since the surface of the insulating film and the surface of the gate electrode are flat,
Planarization of the device surface can be achieved without any special process.
更に、基板の表面は、この絶縁膜とゲート電極とによっ
て完全に覆われており、アニール処理の際に格別の対策
を講じなくてもＡｓの飛散は防止される。また、ＥＣＲ
プラズマＣＶＤ法によって形成される絶縁膜は、基板に
対する応力が少なく、基板の曲げや剥離が生じない。Furthermore, the surface of the substrate is completely covered by the insulating film and the gate electrode, and scattering of As can be prevented without taking any special measures during annealing. Also, ECR
An insulating film formed by the plasma CVD method has little stress on the substrate, and does not cause bending or peeling of the substrate.
実施例
以下に図面を参照して本発明をより具体的に詳述するが
、以下に示すものは本発明の一実施例に過ぎず、本発明
の技術的範囲を何等限定するものではない。EXAMPLES The present invention will be described in more detail below with reference to the drawings, but what is shown below is only one example of the present invention and does not limit the technical scope of the present invention in any way.
第１図（ａ）乃至（ｆ）は、本発明に従う化合物半導体
装置の製造方法によるＭＥＳＦＥＴのゲート電極の形成
工程を順次水したものである。FIGS. 1(a) to 1(f) sequentially illustrate the steps of forming a gate electrode of a MESFET according to the method for manufacturing a compound semiconductor device according to the present invention.
第１図（ａ）は、表面近傍に動作層を形成されたＧａＡ
ｓ基板１の全面に、スパッタ法、蒸着法等によってＷＳ
ｉ等の高融点電極材料金属を１０００〜２００ＯＡ程度
の厚さに堆積して金属層２を形成した様子を示している
。Figure 1(a) shows GaA with an active layer formed near the surface.
WS is applied to the entire surface of the s-substrate 1 by sputtering, vapor deposition, etc.
This figure shows a state in which a metal layer 2 is formed by depositing a high melting point electrode material metal such as i to a thickness of about 1000 to 200 OA.
この金属層２上で、第２図（ｂ）に示すように、ゲート
電極を形成すべき領域にレジスト膜３を形成した後、第
２図（Ｃ）に示すように、ドライエツチング法、イオン
ミリング法等により、レジスト膜３に覆われていない領
域の不要な金属を除去してゲート電極２ａを形成する。On this metal layer 2, as shown in FIG. 2(b), a resist film 3 is formed in a region where a gate electrode is to be formed, and then, as shown in FIG. 2(c), dry etching and ion etching are performed. The gate electrode 2a is formed by removing unnecessary metal in the area not covered by the resist film 3 by a milling method or the like.
こうしてゲート電極２ａを形成された基板１に対して、
１５０〜２００ｋＶ程度の電圧で加速されたＳ１゛の注
入を行い、低抵抗のソース領域４並びにドレイン領域５
を形成する。With respect to the substrate 1 on which the gate electrode 2a is formed in this way,
S1'' implantation accelerated at a voltage of about 150 to 200 kV is performed to form a low resistance source region 4 and drain region 5.
form.
続いて、ゲート電極２ａ上にレジスト膜３を残したまま
、ＥＣＲプラズマＣＶＤ法によってＳｉ３Ｎ。Next, with the resist film 3 remaining on the gate electrode 2a, Si3N is deposited by ECR plasma CVD.
膜７を１０００乃至２０００への厚さに堆積した。Film 7 was deposited to a thickness of 1000 to 2000 nm.
更に、このＳｉ３Ｎ、膜７のうち、ゲート電極２ａ上に
形成されたものは、第１図（ｄ）に示すように、リフト
オフ法によってレジスト膜３と共に除去した。この状態
の基板をアニールし１、動作層、ソース領域４並びにド
レイン領域５の活性化を行った。Furthermore, the Si3N film 7 formed on the gate electrode 2a was removed together with the resist film 3 by a lift-off method, as shown in FIG. 1(d). The substrate in this state was annealed 1, and the active layer, source region 4, and drain region 5 were activated.
こうして完成したゲート電極２ａは、Ｓｉ３Ｎ４膜７と
厚さが同じであり、基板の表面ば略完全に平坦となって
いる。The gate electrode 2a thus completed has the same thickness as the Si3N4 film 7, and the surface of the substrate is substantially completely flat.
また、このゲート電極２ａ並びにＳｉ３Ｎ４膜７上に、
第１図（ｅ）に点線で示すように、レジスト膜８を再び
形成し、このレジスト膜８に覆われていない領域のＳｉ
３Ｎ４膜７を除去した後に、第１図（ｆ）に示すように
、全体に電極材料金属９をスパッタ法、蒸着法等によっ
て堆積し、更にリフトオフ法によってレジスト膜８上の
金属層９を除去すると、第１図（ｆ）に実線で描かれて
いるように、ソース電極９ａ並びにドレイン電極９ｂも
含めて、表面が平坦なＭＥＳＦＥＴが完成する。Moreover, on this gate electrode 2a and Si3N4 film 7,
As shown by the dotted line in FIG.
After removing the 3N4 film 7, as shown in FIG. 1(f), an electrode material metal 9 is deposited over the entire surface by sputtering, vapor deposition, etc., and the metal layer 9 on the resist film 8 is further removed by a lift-off method. Then, as shown by the solid line in FIG. 1(f), a MESFET with a flat surface including the source electrode 9a and drain electrode 9b is completed.
発明の効果
以上詳述の如く、本発明の化合物半導体装置の製造方法
に従えば、アニール処理における化合物半導体基板の保
護と完成した半導体装置表面の平坦化とを同時に実現す
ることができる。Effects of the Invention As detailed above, according to the method for manufacturing a compound semiconductor device of the present invention, protection of the compound semiconductor substrate during annealing treatment and planarization of the surface of the completed semiconductor device can be achieved simultaneously.
即ち、本発明に従う方法では、アニール時の基板表面は
絶縁膜とゲート電極とによって覆われているので、Ａｓ
等のＶ族あるいは■族元素が熱によって飛散することは
ない。That is, in the method according to the present invention, since the substrate surface during annealing is covered with an insulating film and a gate electrode, As
Group V or group II elements such as these do not scatter due to heat.
また、絶縁膜の形成は常温で実施できるＥＣＲプラズマ
ＣＶＤ法によって行うので、ゲート電極形成時にゲート
電極上に形成されたレジスト膜を利用してゲート電極上
の絶縁膜を容易にリフトオフすることができる。従って
、ゲート電極と同じ厚さで堆積した絶縁膜の表面とゲー
ト電極の表面とは共に同じ高さにあり、素子表面の平坦
化も自ずと実現される。In addition, since the insulating film is formed by the ECR plasma CVD method that can be performed at room temperature, the insulating film on the gate electrode can be easily lifted off using the resist film formed on the gate electrode when forming the gate electrode. . Therefore, the surface of the insulating film deposited to the same thickness as the gate electrode and the surface of the gate electrode are both at the same height, and the device surface is naturally flattened.
このように、本発明の方法によれば、従来の化半導体形
成工程に比して大きな工数の増加を招くことなく、品質
の高い化半導体装置を形成することができる。また素子
の平坦化は、この上層に上層配線あるいは層間絶縁層を
形成した場合に、その品質あるいは歩留りの向上を実現
する。As described above, according to the method of the present invention, a high quality semiconductor device can be formed without causing a large increase in the number of steps compared to the conventional semiconductor formation process. Furthermore, planarization of the device improves the quality or yield when an upper wiring layer or an interlayer insulating layer is formed on this upper layer.
第１図（ａ）乃至（ｆ）は、本発明に従う化半導体装置
の製造方法を工程を追って示す図であり、第２図（ａ）
乃至（ｆ）は、従来の化半導体装置の製造方法を工程を
追って示す図である。
〔主な参照番号〕
１・・・・化合物半導体基板、
２．９・・金属膜、
２ａ・・・ゲート電極、
３．８・・レジスト膜、
４・・・・ソース領域、
４ａ・・・ソース電極、
５・・・ ・ドレイン領域、
５ａ・・・ドレイン電極、
６・・・・保護３ｉ３Ｎ４膜、1(a) to 1(f) are diagrams showing step by step a method for manufacturing a semiconductor device according to the present invention, and FIG. 2(a)
1 to 3(f) are diagrams illustrating a conventional semiconductor device manufacturing method step by step. [Main reference numbers] 1... compound semiconductor substrate, 2.9... metal film, 2a... gate electrode, 3.8... resist film, 4... source region, 4a... Source electrode, 5... Drain region, 5a... Drain electrode, 6... Protective 3i3N4 film,
Claims (3)
成する工程と、 該金属膜上の電極を形成すべき領域にレジスト膜を形成
する工程と、 該レジスト膜に覆われていない領域の金属膜を除去する
工程と、 金属を除去された領域に対して不純物を注入する工程と
、 該基板をアニールする工程とを少なくとも含む半導体装
置の製造方法であって、 前記不純物注入工程後の基板に対して、前記レジスト膜
を残したままＥＣＲプラズマＣＶＤ法によって、基板全
体に前記金属膜の厚さまで絶縁膜を堆積する工程と、 該レジスト膜と共に該レジスト膜上の前記絶縁膜を除去
する工程と を前記アニール工程よりも前の工程に含むことを特徴と
する化合物半導体装置の製造方法。(1) A step of forming an electrode material metal film on the entire surface of the compound semiconductor substrate, a step of forming a resist film on the region where the electrode is to be formed on the metal film, and a step of forming the resist film on the region not covered with the resist film. A method for manufacturing a semiconductor device including at least the steps of removing a metal film, implanting an impurity into the region from which the metal has been removed, and annealing the substrate, the substrate after the impurity implantation step. In contrast, a step of depositing an insulating film to the thickness of the metal film over the entire substrate by ECR plasma CVD while leaving the resist film, and a step of removing the insulating film on the resist film together with the resist film. A method for manufacturing a compound semiconductor device, characterized in that a step before the annealing step includes:
とする特許請求の範囲第１項に記載の化合物半導体装置
の製造方法。(2) The method for manufacturing a compound semiconductor device according to claim 1, wherein the insulating film is a Si_3N_4 film.
ることを特徴とする特許請求の範囲第１項または第２項
に記載の化合物半導体装置の製造方法。(3) The method for manufacturing a compound semiconductor device according to claim 1 or 2, wherein the compound semiconductor substrate is a GaAs single crystal substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28615286A JPS63138727A (en) | 1986-12-01 | 1986-12-01 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28615286A JPS63138727A (en) | 1986-12-01 | 1986-12-01 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63138727A true JPS63138727A (en) | 1988-06-10 |
Family
ID=17700608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28615286A Pending JPS63138727A (en) | 1986-12-01 | 1986-12-01 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63138727A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202286A (en) * | 1989-02-27 | 1993-04-13 | Mitsubishi Denki Kabushiki Kaisha | Method of forming three-dimensional features on substrates with adjacent insulating films |
-
1986
- 1986-12-01 JP JP28615286A patent/JPS63138727A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202286A (en) * | 1989-02-27 | 1993-04-13 | Mitsubishi Denki Kabushiki Kaisha | Method of forming three-dimensional features on substrates with adjacent insulating films |
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