JPS63136637A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63136637A
JPS63136637A JP61281749A JP28174986A JPS63136637A JP S63136637 A JPS63136637 A JP S63136637A JP 61281749 A JP61281749 A JP 61281749A JP 28174986 A JP28174986 A JP 28174986A JP S63136637 A JPS63136637 A JP S63136637A
Authority
JP
Japan
Prior art keywords
pad
bonding
ball
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61281749A
Other languages
Japanese (ja)
Inventor
Fujihiko Inomata
猪又　藤彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61281749A priority Critical patent/JPS63136637A/en
Publication of JPS63136637A publication Critical patent/JPS63136637A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a bonding pad structure substantially reduced in its capacity without decreasing a bonding strength by the displacement of a press-bonding ball by surrounding electrode pads made of a metal film connected to an element through an insulating film around its periphery, and disposing a plurality of individually separated small pads. CONSTITUTION:A pad 1 made of an aluminum film is connected through aluminum wirings 6 to a semiconductor element. If the displacement of a press- bonding ball occurs at the time of wire bonding, part of the pad 7 of the periphery is contacted with the ball, but the small pad not contacted with the ball is electrically separated from the pad 1 at the center so as not to operate as a pad capacity. A floating part which does not contribute to the connection to a package is not formed, the pad area S decreases, thereby reducing a CMOS. This decreases Cob, Coc of a transistor element, thereby improving its high-frequency characteristics.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置における端子電極部（ボンディング
パッド）構造に関するもので、主とじて高周波用トラン
ジスタの電極パッドパターン形状を対象とする。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a terminal electrode portion (bonding pad) structure in a semiconductor device, and is mainly directed to the electrode pad pattern shape of a high frequency transistor.

〔従来技術〕[Prior art]

トランジスタの電極に関してはたとえば特開昭５３−１
２９９６５公報に記載され℃いる。その概要は半導体ペ
レットの各電極表面をワイヤボンディングに必要な部分
のみをバンドとして露出させ、それ以外の各電極表面を
絶縁膜で被覆し、露出電極面の相互の位置を充分に離丁
ことでワイヤボンディングの際にボンディング位置ずれ
による短絡事故等を防止するものである。Regarding the electrodes of transistors, for example, JP-A-53-1
It is described in Publication No. 29965. The outline of this method is to expose only the part of each electrode surface of the semiconductor pellet necessary for wire bonding as a band, cover the other electrode surfaces with an insulating film, and keep the exposed electrode surfaces sufficiently apart from each other. This prevents accidents such as short circuits due to bonding misalignment during wire bonding.

ところで高周波トランジスタの場合はボンディングのた
めの電極パッドは円形に形成してパッド面積を小さくし
、あるいはパッド直下の酸化膜を厚くして低容量化する
ことで特性向上を図りている。In the case of high-frequency transistors, characteristics are improved by forming electrode pads for bonding in a circular shape to reduce the pad area, or by thickening the oxide film directly under the pads to reduce capacitance.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

トランジスタの微細化が丁丁むにしたがい、電極パッド
部におけるワイヤボンドの際の圧着ポールの位置ずれが
問題となりてくる。As transistors become smaller and smaller, misalignment of the crimp pole during wire bonding at the electrode pad becomes a problem.

第５図はワイヤボンディングの位置ずれの状態を示す平
面図、第６図は同断面図である。１はＡ！等の金属膜よ
りなる電極パッド部、２は圧着ボール、３は金線（ワイ
ヤ）である。４はパッド部の下地酸化膜（ＳｉＯ１膜）
である。５はＳｔ半導体基板である。６は素子に接続さ
れるＡ！配線である。FIG. 5 is a plan view showing the state of wire bonding misalignment, and FIG. 6 is a sectional view thereof. 1 is A! 2 is a press-bonded ball, and 3 is a gold wire. 4 is the base oxide film (SiO1 film) of the pad part
It is. 5 is an St semiconductor substrate. 6 is A! connected to the element. It's the wiring.

このような圧着ボール２のパッド部１への位置ずれを考
慮し、パッド部１は大きめにしである。In consideration of such misalignment of the press-bonded ball 2 to the pad portion 1, the pad portion 1 is made larger.

したがつ℃圧着に寄与しない部分囚のパッド又はパッド
からずれた圧着ボール部分冊は丁べて本来のパッケージ
との接続という目的に効果のない浮遊の容量となる。Therefore, the partial pads that do not contribute to the crimping or the crimp ball portions that are deviated from the pads together become floating capacitances that are ineffective for the purpose of connecting to the original package.

パッド面積を小さくずれは圧着ボールのずれ部が大きく
なることにより、ボンティング強度が小さくなる。If the pad area is made smaller and the pad area deviates, the deviated portion of the crimped ball becomes larger, resulting in a decrease in bonding strength.

容量を小さくする他の手段として下地酸化膜を厚くする
ことは工程が余分に附加されるとともに、酸化膜自体の
ストレスが加わりクラック等を生じるおそれがあって好
ましくない。Increasing the thickness of the base oxide film as another means of reducing the capacitance is not preferable because it adds an extra step and may add stress to the oxide film itself, causing cracks or the like.

本発明は上記した問題を克服するためになされたもので
あり、その目的とするところは、圧着ボールのずれによ
ってボンティング強度を小さくすることなく実質的に低
容量化できるポンディングパッド構造を提供することに
ある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to provide a bonding pad structure that can substantially reduce the capacitance without reducing the bonding strength due to displacement of the crimped balls. It's about doing.

本発明の前記ならびにそのほかの目的と新規な特徴は本
明細書の記述及び添付図面からあきらかになろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明子れば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

丁なわち、半導体基板の一主表面に半導体素子が形成さ
れ、上記基板上で上記素子に接続する金属膜からなる電
極パッド部が絶縁膜を介し配設された半導体装置であっ
て、上記電極パッド部はその周辺を取り囲み、個々に分
離された複数の小パッドが配設されたものである。That is, a semiconductor device in which a semiconductor element is formed on one main surface of a semiconductor substrate, and an electrode pad portion made of a metal film connected to the element on the substrate is disposed via an insulating film, The pad section is surrounded by a plurality of individually separated small pads.

〔作用〕[Effect]

上記した手段により、パッド部面積中の容量成分として
の面積は小さくなり、ボンディング強度を低下させるこ
となく低容量化が実現できる。By the means described above, the area as a capacitance component in the area of the pad portion is reduced, and a reduction in capacitance can be realized without reducing bonding strength.

〔実施例〕〔Example〕

第１図及び第２図は本発明の一実施例を示すものであっ
て、このうち、第１図はポンディングパッドの平面図、
第２図は第１図におけるイーイ断面図である。１はＡ！
膜からなるパッド部でＡ−ｅ配線６を介して半導体素子
に接続される。４は下地酸化膜、５はＳｉ基板である。1 and 2 show one embodiment of the present invention, in which FIG. 1 is a plan view of a bonding pad;
FIG. 2 is a cross-sectional view of FIG. 1. 1 is A!
A pad portion made of a film is connected to a semiconductor element via an A-e wiring 6. 4 is a base oxide film, and 5 is a Si substrate.

７はパッドを取り囲み、個々に分離されたＡ！膜からな
る小パッド部である。同図ではワイヤボンディング時に
圧着ボール２がパッドの中心から斜め横にずれた場合の
状態を示す。7 surrounds the pad and the individually separated A! This is a small pad part made of a membrane. This figure shows a situation where the crimp ball 2 is shifted diagonally from the center of the pad during wire bonding.

この実施例で述べた構造によれば、下記のように効果が
得られる。According to the structure described in this embodiment, the following effects can be obtained.

（１）　　ワイヤボンティング時に圧着ボールのずれが
発生した場合に、周囲の小パッドの一部は圧着ボールと
接触するが、圧着ボールに接触しない小パッドは中心の
電極パッド１から電気的に分離していることによりパッ
ド容量として働かない。(1) If the crimp ball shifts during wire bonding, some of the surrounding small pads will come into contact with the crimp ball, but the small pads that do not contact the crimp ball will be electrically isolated from the center electrode pad 1. Because of this, it does not work as a pad capacitor.

丁なわち、パッド容量（ＭＯ８容量）はＣＭＯ８−＃　
Ｓ／Ｔｏｘ（ただし、Ｓはパッド面積、ＴＯＸは酸化膜
厚、１は誘電率）− であられされる。圧着ボールがずれることで従来生じた
パッケージとの接続に寄与しない浮遊部分が形成されず
Ｓが小さくなり、ＣＭＯ８が低減され、これがトランジ
スタ素子のＣｏｂ　、　Ｃｏｅ等の減少となり、高周波
特性を向上する。In other words, the pad capacity (MO8 capacity) is CMO8-#
S/Tox (where S is the pad area, TOX is the oxide film thickness, and 1 is the dielectric constant). Due to the displacement of the crimp ball, floating parts that do not contribute to the connection with the package, which occur conventionally, are not formed, S is reduced, CMO8 is reduced, and this reduces Cob, Coe, etc. of the transistor element, improving high frequency characteristics.

（２）ずれた圧着ボールは小パッドに接着することで圧
着（ボンディング）強度を充分に確保できる。(2) By adhering the misaligned crimped ball to a small pad, sufficient crimping (bonding) strength can be ensured.

以上本発明者により℃なされた発明を実施例（もとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範囲で稽々変更可
能である。The invention made by the present inventors has been described in detail based on the embodiments described above, but the present invention is not limited to the above embodiments (and can be modified without departing from the gist thereof).

たとえば、第３図又は第４図に示すように複数の小パッ
ド部を回路素子側（ＡＡ配線６のある側）へ偏るように
パッド部に接して配設することにより通常のずれの範囲
を考慮し、信号出し入れとし℃の持続面積をＡ！配線の
一部を利用して確保てる。For example, as shown in FIG. 3 or 4, by arranging a plurality of small pads in contact with the pads so as to be biased toward the circuit element side (the side where the AA wiring 6 is located), the range of normal deviation can be reduced. Considering the signal input and output, the continuous area of °C is A! It is secured using part of the wiring.

又、パッド直下の酸化膜厚を厚くする構造と併用するこ
とにより低容量化が期待できる。In addition, lower capacitance can be expected by combining this with a structure in which the oxide film directly under the pad is thicker.

本発明は高周波デバイス、丁なわち、パッドと下地絶縁
膜を介してＳｉ基板との間に容量が生成され、それがデ
バイス容量として表われるデバイスに適用して有効であ
り、たとえばＳｔ−バイポーラトランジスタ、Ｊ−ＦＥ
Ｔ、ＭＯＳＦＥＴに応用して効果がある。The present invention is effective when applied to high-frequency devices, that is, devices in which capacitance is generated between a pad and an Si substrate via an underlying insulating film, and this appears as device capacitance, such as a St-bipolar transistor. , J-FE
It is effective when applied to T, MOSFET.

〔発明の効果〕〔Effect of the invention〕

本願におい℃開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

ｊｔｔわち、ポンディングパッド部の低容量化ができ、
しかもボンディング強度を確保し、高性能のデバイスが
実現できる。jttIn other words, the capacitance of the bonding pad part can be reduced,
Furthermore, bonding strength can be ensured and high-performance devices can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すポンディングパッドの
平面図である。 第２図は第１図におけるイーイ視断面図である。 第３図及び第４図は本発明の応用例を示すパッドの平面
図である。 第５図はポンディングパッドの従来例の平面図である。 第６図は第５図におけるイーイ視断面図である。 １・・・Ａ！パッド、２・・・圧着ボール、３・・・金
ワイヤ、４・・・酸化膜、５・・・Ｓｉ基板、６・・・
Ａノ配線、７・・・小パッド。 代理人　弁理士　小　川　勝　男 第　　１　　図 第　　２　　図 第　　３　　図 第　　４　　図FIG. 1 is a plan view of a bonding pad showing an embodiment of the present invention. FIG. 2 is a cross-sectional view of FIG. 1 as viewed from E. 3 and 4 are plan views of a pad showing an example of application of the present invention. FIG. 5 is a plan view of a conventional example of a bonding pad. FIG. 6 is a cross-sectional view of FIG. 5 as viewed from E. 1...A! Pad, 2... Crimp ball, 3... Gold wire, 4... Oxide film, 5... Si substrate, 6...
A wiring, 7... small pad. Agent Patent Attorney Katsoo Ogawa Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 １、半導体基板の一主表面に半導体素子が形成され、上
記基板上で上記半導体素子に接続する金属膜からなる電
極パッド部が絶縁膜を介して配設された半導体装置であ
って、上記電極パッド部はその周辺を取り囲み個々に分
離された複数の小パッド部が配設されていることを特徴
とする半導体装置。 ２、上記複数の小パッド部は回路素子側へ偏るようにパ
ッド部に接して形成される特許請求の範囲第１項に記載
の半導体装置。 ３、上記半導体素子は高周波用素子である特許請求の範
囲第１項又は第２項に記載の半導体装置。[Claims] 1. A semiconductor device in which a semiconductor element is formed on one main surface of a semiconductor substrate, and an electrode pad portion made of a metal film connected to the semiconductor element is disposed on the substrate via an insulating film. A semiconductor device characterized in that the electrode pad section has a plurality of individually separated small pad sections surrounding the electrode pad section. 2. The semiconductor device according to claim 1, wherein the plurality of small pad portions are formed in contact with the pad portion so as to be biased toward the circuit element side. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor element is a high frequency element.
JP61281749A 1986-11-28 1986-11-28 Semiconductor device Pending JPS63136637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61281749A JPS63136637A (en) 1986-11-28 1986-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61281749A JPS63136637A (en) 1986-11-28 1986-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63136637A true JPS63136637A (en) 1988-06-08

Family

ID=17643441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61281749A Pending JPS63136637A (en) 1986-11-28 1986-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63136637A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334935A (en) * 2001-05-08 2002-11-22 Mitsubishi Electric Corp High-frequency circuit chip, high-frequency circuit device having the chip, and method of manufacturing the same
CN104347562A (en) * 2013-08-02 2015-02-11 英飞凌科技股份有限公司 Segmented Bond Pads and Methods of Fabrication Thereof
JP2021193745A (en) * 2015-12-18 2021-12-23 ローム株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334935A (en) * 2001-05-08 2002-11-22 Mitsubishi Electric Corp High-frequency circuit chip, high-frequency circuit device having the chip, and method of manufacturing the same
CN104347562A (en) * 2013-08-02 2015-02-11 英飞凌科技股份有限公司 Segmented Bond Pads and Methods of Fabrication Thereof
US9543260B2 (en) 2013-08-02 2017-01-10 Infineon Technologies Ag Segmented bond pads and methods of fabrication thereof
JP2021193745A (en) * 2015-12-18 2021-12-23 ローム株式会社 Semiconductor device
US11674983B2 (en) 2015-12-18 2023-06-13 Rohm Co., Ltd. SiC semiconductor device with current sensing capability

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