JPS6313619B2 - - Google Patents
Info
- Publication number
- JPS6313619B2 JPS6313619B2 JP56194086A JP19408681A JPS6313619B2 JP S6313619 B2 JPS6313619 B2 JP S6313619B2 JP 56194086 A JP56194086 A JP 56194086A JP 19408681 A JP19408681 A JP 19408681A JP S6313619 B2 JPS6313619 B2 JP S6313619B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- frequency
- stereo
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000926 separation method Methods 0.000 claims description 8
- 230000006872 improvement Effects 0.000 claims description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000003321 amplification Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
- H04H40/72—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/1646—Circuits adapted for the reception of stereophonic signals
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stereo-Broadcasting Methods (AREA)
Description
【発明の詳細な説明】
本発明は、種々の妨害雑音、特に変調の浅い妨
害信号による同一チヤンネル妨害に対して、効果
的に聴感上のSN比を改善し得るSN比改善回路を
提供せんとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention aims to provide an SN ratio improvement circuit that can effectively improve the auditory SN ratio against various types of interference noise, particularly against same-channel interference caused by shallowly modulated interference signals. It is something to do.
従来、受信信号の電界強度を検出し、該電界強
度に応じて、ステレオMPX（マルチプレツクス）
回路の分離度を調整したり、前記ステレオMPX
回路の入力側もしくは出力側に得られる高域成分
を減衰させたりして、SN比を改善する方法が公
知である。この方法は、電界強度が低下した状態
においては効果があるが、電界強度に対応せず受
信条件に応じて発生するマルチパス妨害、隣接チ
ヤンネル妨害、同一チヤンネ妨害等には全く効果
のないものであつた。 Conventionally, the electric field strength of the received signal is detected, and depending on the electric field strength, stereo MPX (multiplex)
Adjust the degree of separation of the circuit or the stereo MPX
There is a known method of improving the SN ratio by attenuating high-frequency components obtained at the input or output side of a circuit. This method is effective when the electric field strength is reduced, but it is completely ineffective against multipath interference, adjacent channel interference, same channel interference, etc. that do not correspond to the electric field strength and occur depending on the reception conditions. It was hot.
また、従来、FM復調回路の出力信号中の高域
（例えば75KHz以上）雑音成分を検出し、それに
応じてステレオ分離度を調整したり、高域成分を
減衰させたりする方法も公知である。この方法
は、マルチパス妨害や、隣接チヤンネル妨害に対
しても有効であるが、変調が浅く周波数変移の少
い妨害信号に起因する同一チヤンネル妨害に対し
ては、効力が無かつた。 Furthermore, there is also a conventionally known method of detecting high-frequency (for example, 75 KHz or higher) noise components in the output signal of an FM demodulation circuit, and adjusting the degree of stereo separation or attenuating the high-frequency components accordingly. Although this method is effective against multipath interference and adjacent channel interference, it is ineffective against same-channel interference caused by interference signals with shallow modulation and little frequency shift.
本発明は、上述の点に鑑み成されたもので、以
下実施例に基づき図面を参照しながら説明する。
第１図は、FM復調回路の出力信号中に含まれる
同一チヤンネル妨害に起因して発生する雑音のス
ペクトルを示すものである。第１図の場合は、無
変調の希望信号に対して、40KHz程度の周波数変
移を有する妨害信号が混入したときの同一チヤン
ネル妨害により生じる雑音を示すものである。第
２図は、本発明の一実施例を示すもので、１はア
ンテナ、２はFMフロントエンド、３はIF（中間
周波）増幅回路、４はFM復調回路、５はステレ
オMPX回路、６は左信号増幅回路、７は右信号
増幅回路、８は左スピーカ、及び９は右スピーカ
である。また、１０は、位相比較器１１、低域通
過フイルタ兼直流増幅器１２、電圧制御発振器１
３、第１分周器１４及び第２分周器１５から成る
ステレオMPX回路５の為のサブキヤリア信号を
発生するPLL回路、１６は前記FM復調回路４と
前記PLL回路１０の位相比較器１１との間に挿
入された19KHzを中心周波数とする帯域通過フイ
ルタ、３１はパルスカウント検出器で、第２分周
器１５の出力信号が加えられる単安定マルチバイ
ブレータ２９と積分回路３０とからなる。１７は
前記積分回路３０の出力信号を増幅する帯域増幅
器、１８は該帯域増幅器１７の出力信号を整流す
る整流回路及び１９は該整流回路１８の出力信号
に応じた直流制御信号を発生する制御信号発生回
路である。 The present invention has been made in view of the above points, and will be described below based on embodiments with reference to the drawings.
FIG. 1 shows the spectrum of noise generated due to co-channel interference contained in the output signal of the FM demodulation circuit. The case in FIG. 1 shows the noise caused by same-channel interference when an interference signal having a frequency shift of about 40 KHz is mixed into an unmodulated desired signal. FIG. 2 shows an embodiment of the present invention, where 1 is an antenna, 2 is an FM front end, 3 is an IF (intermediate frequency) amplification circuit, 4 is an FM demodulation circuit, 5 is a stereo MPX circuit, and 6 is a stereo MPX circuit. A left signal amplification circuit, 7 a right signal amplification circuit, 8 a left speaker, and 9 a right speaker. Further, 10 is a phase comparator 11, a low-pass filter/DC amplifier 12, and a voltage controlled oscillator 1.
3. A PLL circuit that generates a subcarrier signal for the stereo MPX circuit 5, which is composed of a first frequency divider 14 and a second frequency divider 15; 16 is a phase comparator 11 of the FM demodulation circuit 4 and the PLL circuit 10 ; A bandpass filter 31 having a center frequency of 19 KHz is inserted between the two, and 31 is a pulse count detector, which is composed of a monostable multivibrator 29 to which the output signal of the second frequency divider 15 is applied, and an integrating circuit 30. 17 is a band amplifier that amplifies the output signal of the integrating circuit 30; 18 is a rectifier circuit that rectifies the output signal of the band amplifier 17; and 19 is a control signal that generates a DC control signal according to the output signal of the rectifier circuit 18. This is a generation circuit.
アンテナ１に受信された信号は、フロントエン
ド２でIF信号に変換され、IF増幅回路３で増幅
された後、FM復調回路４で復調される。そし
て、FM復調出力は、ステレオMPX回路５で
PLL回路１０の第１分周器１４から得られる38K
Hzサブキヤリア信号の作用により左右のステレオ
信号に分離され、左ステレオ信号は、左信号増幅
回路６で増幅され、右ステレオ信号は右信号増幅
回路７で増幅された後、それぞれ左右スピーカ８
及び９に印加される
PLL回路１０の位相比較器１１の第１入力端
子には、FM復調回路４の出力信号が帯域通過フ
イルタ１６を介して印加される。また前記位相比
較器１１の第２入力端子には、電圧制御発振器１
３の発振出力（76KHz）を第１及び第２分周器１
４及び１５で分周して得られる19KHzの分周信号
が印加される。位相比較器１１の第１及び第２入
力端子に前述の如き入力信号が印加されると、そ
の位相差に応じた信号が前記位相比較器１１の出
力に生じる。この位相差に応じた信号は、低域通
過フイルタ兼直流増幅器１２で増幅された後、電
圧制御発振器１３に印加され、該電圧制御発振器
１３の出力信号が正しく76KHzとなり、第１分周
器１４の出力がFM復調回路４の出力信号と正し
く同期する様に作用する。この時、バンドパスフ
イルタ１６の出力に19KHzステレオパイロツト信
号とともに雑音が生じると、第２分周器１５の出
力に得られる19KHz信号は、帯域通過フイルタ１
６を介して位相比較器１１の第１入力端子に印加
される入力信号が雑音により位相変調を受ける為
に、雑音の発生時に厳密には19KHzを中心として
僅かに異なる周波数に交互に変化される。その信
号がパルスカウント検出器３１に加えられると、
単安定マルチバイブレータ２９より第２分周器１
５よりの正規な周波数19KHzとの差に応じて間隔
が変わる方形波信号が発振される（第５図イ）。
前記方形波信号は積分回路３０に加えられ平滑さ
れる（第５図ロ）。方形波信号を平滑して得られ
る直流レベルは19KHzのときの方形波信号を平滑
して得られた直流レベルを中心として上下に変わ
る（第５図ハ）。即ち第２分周器１５の出力より
得られる信号が19KHzより周波数が高なると方形
波信号の間隔が短かくなり、充電時間は同一であ
るが放電時間が短かくなり積分回路３０で平滑し
て得られる直流レベルは高まり、逆に第２分周器
１５の出力より得られる信号が19KHzより周波数
が低くなると方形波信号の間隔が長くなり、前述
と同様充電時間は同一であるが放電時間が長くな
るので直流レベルは低下され、結果として同一チ
ヤンネル妨害または隣接チヤンネル妨害発生時に
はパルスカウント検出器３１の出力に受信信号と
妨害信号によるビートを発生する。そのビート信
号の振幅は受信信号レベルを一定にした場合妨害
信号レベルに比例する。 A signal received by the antenna 1 is converted into an IF signal by the front end 2, amplified by the IF amplifier circuit 3, and then demodulated by the FM demodulation circuit 4. Then, the FM demodulation output is output by the stereo MPX circuit 5.
38K obtained from the first frequency divider 14 of the PLL circuit 10
The left and right stereo signals are separated by the action of the Hz subcarrier signal, and the left stereo signal is amplified by the left signal amplification circuit 6, and the right stereo signal is amplified by the right signal amplification circuit 7, and then sent to the left and right speakers 8, respectively.
The output signal of the FM demodulation circuit 4 is applied to the first input terminal of the phase comparator 11 of the PLL circuit 10 via the bandpass filter 16. Further, a voltage controlled oscillator 1 is connected to the second input terminal of the phase comparator 11.
3 oscillation output (76KHz) to the first and second frequency divider 1
A frequency-divided signal of 19KHz obtained by dividing the frequency by 4 and 15 is applied. When the aforementioned input signals are applied to the first and second input terminals of the phase comparator 11, a signal corresponding to the phase difference is generated at the output of the phase comparator 11. The signal corresponding to this phase difference is amplified by the low-pass filter/DC amplifier 12 and then applied to the voltage controlled oscillator 13, and the output signal of the voltage controlled oscillator 13 becomes correctly 76KHz, and the first frequency divider 14 The output of the FM demodulation circuit 4 functions to be properly synchronized with the output signal of the FM demodulation circuit 4. At this time, if noise occurs in the output of the bandpass filter 16 along with the 19KHz stereo pilot signal, the 19KHz signal obtained at the output of the second frequency divider 15 will be
Since the input signal applied to the first input terminal of the phase comparator 11 via 6 is phase modulated by noise, it is alternately changed to a slightly different frequency centered around 19KHz when noise occurs. . When that signal is applied to the pulse count detector 31,
Second frequency divider 1 from monostable multivibrator 29
A square wave signal whose interval changes according to the difference from the normal frequency of 19KHz from 5 is oscillated (Fig. 5A).
The square wave signal is applied to an integrating circuit 30 and smoothed (FIG. 5b). The DC level obtained by smoothing the square wave signal varies up and down around the DC level obtained by smoothing the square wave signal at 19 KHz (Figure 5 C). That is, when the frequency of the signal obtained from the output of the second frequency divider 15 becomes higher than 19KHz, the interval between the square wave signals becomes shorter, and although the charging time remains the same, the discharging time becomes shorter and is smoothed by the integrating circuit 30. The obtained DC level increases, and conversely, when the frequency of the signal obtained from the output of the second frequency divider 15 becomes lower than 19KHz, the interval between square wave signals becomes longer, and as mentioned above, the charging time is the same, but the discharging time becomes longer. As the length increases, the DC level is lowered, and as a result, when same channel interference or adjacent channel interference occurs, a beat is generated at the output of the pulse count detector 31 due to the received signal and the interference signal. The amplitude of the beat signal is proportional to the interfering signal level when the received signal level is kept constant.
前記ビート信号は帯域増幅器１７で増幅される
が、帯域増幅器１７は数十Hzから１〜2KHzの周
波数帯域の信号のみを通過させるようにしている
ので（第５図ニ）、19KHzのパイロツト信号は十
分に減衰され前記ビート信号のみが増幅して取出
される。増幅されたビート信号を整流回路８で整
流すれば、妨害程度に応じた信号が得られ、これ
を帯域増幅器１７で増幅した後整流回路１８で整
流すれば、雑音に応じた直流出力が発生し（第５
図ホ）、該直流出力を制御信号発生回路１９に印
加することにより、出力端子３２に制御信号が発
生する。この制御信号を、ステレオMPX回路５
に印加すれば、ステレオ分離度の調整及び高域減
衰の調整を行うことが出来、SN比の向上を計る
ことが出来る。尚雑音がない場合の前記各部分の
出力波形図は第６図イ，ロ，ハ，ニ，ホに示す通
りで前記直流出力が発生されることはない。 The beat signal is amplified by the band amplifier 17, but since the band amplifier 17 is designed to only pass signals in the frequency band from several tens of Hz to 1 to 2 KHz (Fig. 5 D), the 19 KHz pilot signal is Only the sufficiently attenuated beat signal is amplified and extracted. If the amplified beat signal is rectified by the rectifier circuit 8, a signal corresponding to the degree of interference will be obtained, and if this is amplified by the band amplifier 17 and then rectified by the rectifier circuit 18, a DC output corresponding to the noise will be generated. (5th
By applying the DC output to the control signal generation circuit 19, a control signal is generated at the output terminal 32 (FIG. E). This control signal is sent to the stereo MPX circuit 5.
By applying it to , it is possible to adjust the degree of stereo separation and the attenuation of high frequencies, and it is possible to improve the signal-to-noise ratio. Note that the output waveform diagrams of the respective parts when there is no noise are as shown in FIG. 6 A, B, C, D, and E, and the DC output is not generated.
前記ステレオ分離調整回路は、例えば第３図に
示す如きものであり、左右ステレオ信号がそれぞ
れ得られる左信号路２０と右信号路２１との間
に、可変抵抗２２を挿入し、該可変抵抗２２の値
を前記制御信号発生回路１９からの制御信号に応
じて動作する駆動回路２３で変化させるものであ
る。このステレオ分離度調整回路を使用すること
により、信号中の雑音が増大し、整流回路１８の
出力が大になつたとき、ステレオ分離度を悪化さ
せ、モノラルに近ずけていきSN比を向上させる
ことが出来る。その時、ステレオ分離度は、整流
回路１８の出力レベルに対応するので、SN比の
改善は、雑音量に対応して行われる。 The stereo separation adjustment circuit is, for example, as shown in FIG. The value of is changed by a drive circuit 23 that operates in response to a control signal from the control signal generation circuit 19. By using this stereo separation degree adjustment circuit, when the noise in the signal increases and the output of the rectifier circuit 18 becomes large, the stereo separation degree becomes worse and the signal becomes closer to monaural, improving the SN ratio. I can do it. At this time, since the degree of stereo separation corresponds to the output level of the rectifier circuit 18, the improvement of the SN ratio is performed in accordance with the amount of noise.
前記高域成分減衰回路は、例えば第４図に示す
如きものであり、左右ステレオ信号がそれぞれ得
られる左右信号路２４及び２５に、第１及び第２
低域通過フイルタ２６及び２７を挿入し、該第１
及び第２低域通過フイルタ２６及び２７の高域信
号の減衰量を制御信号発生回路１９からの制御信
号に応じて動作する駆動回路２８で変化させるも
のである。高域信号の減衰量は、整流回路１８の
出力信号に応じて、すなわち、信号中の雑音量に
応じて変化させることが出来、SN比の改善が雑
音量に応じて連続的に達成出来る。 The high-frequency component attenuation circuit is, for example, as shown in FIG.
Insert low pass filters 26 and 27, and
The amount of attenuation of the high-frequency signals of the second low-pass filters 26 and 27 is changed by a drive circuit 28 that operates in response to a control signal from a control signal generation circuit 19. The amount of attenuation of the high frequency signal can be changed according to the output signal of the rectifier circuit 18, that is, according to the amount of noise in the signal, and the improvement of the SN ratio can be continuously achieved according to the amount of noise.
信号に混入する雑音は、信号の電界強度に対応
する雑音、マルチバスに起因する雑音、隣接チヤ
ンネル妨害に起因する雑音、同一チヤンネル妨害
に起因する雑音等多々あるが、本発明に係る聴感
上のSN比をを改善するSN比改善回路は、これら
すべてに有効である。特に、本発明に係るSN比
改善回路は、同一チヤンネル妨害のうち、従来は
全く対処出来なかつた変調の浅い妨害信号による
同一チヤンネル妨害（第１図の如く雑音が発生す
る）に対しても、大きな効果を発揮することが出
来るという大きな利点を有するので、地理的近接
点に同一チヤンネル放送局が存在する地域向の
FMステレオ受信機に利用して多大な効果があ
る。 There are many types of noise mixed into a signal, such as noise corresponding to the electric field strength of the signal, noise caused by multi-bus, noise caused by adjacent channel interference, and noise caused by same channel interference. An SN ratio improvement circuit that improves the SN ratio is effective for all of these. In particular, the SN ratio improvement circuit according to the present invention can also deal with same-channel interference caused by a shallowly modulated interference signal (which generates noise as shown in Figure 1), which conventionally could not be dealt with at all. Since it has the great advantage of being able to demonstrate a great effect, it is suitable for areas where there are broadcasting stations of the same channel in geographical proximity.
It has great effects when used in FM stereo receivers.
第１図は、同一チヤンネル妨害による雑音を示
す特性図、第２図は本発明の一実施例を示す回路
ブロツク図、第３図及び第４図はその具体例を示
す回路図、第５図イ，ロ，ハ，ニ，ホ及び第６図
イ，ロ，ハ，ニ，ホは各部分の波形特性図であ
る。
主な図番の説明、５…ステレオMPX回路、１
０…PLL回路、１１…位相比較器、１６…帯域
通過フイルタ、１７…帯域増幅器、１８…整流回
路、１９…制御信号発生回路、３１…パルスカウ
ント検出器。
Fig. 1 is a characteristic diagram showing noise due to same channel interference, Fig. 2 is a circuit block diagram showing an embodiment of the present invention, Figs. 3 and 4 are circuit diagrams showing a specific example thereof, and Fig. 5 A, B, C, D, H and FIG. 6 A, B, C, D, and H are waveform characteristic diagrams of each part. Explanation of main drawing numbers, 5...Stereo MPX circuit, 1
0... PLL circuit, 11... Phase comparator, 16... Bandpass filter, 17... Bandpass amplifier, 18... Rectifier circuit, 19... Control signal generation circuit, 31... Pulse count detector.
Claims (1)
調回路よりのFM復調信号から左右のステレオ信
号を分離するステレオマルチプレツクス回路と、
位相比較器、電圧制御発振器及び分周器を有し前
記FM復調回路よりのパイロツト信号と分周器よ
りの分周信号とを位相比較器にて位相比較しその
出力で電圧制御発振器を制御し前記ステレオマル
チプレツクス回路に正確なパイロツト信号を供給
するPLL回路と、該PLL回路の分周信号の周波
数差を検出するパルスカウント検出器と、該パル
スカウント検出器で得られた周波数差信号より制
御信号を発生する制御信号発生回路とよりなり、
前記制御信号にてステレオマルチプレツクス回路
の出力信号のステレオ分離度を徐々に劣化しモノ
ラルに近ずけてSN比を改善することを特徴とす
るSN比改善回路。1. An FM demodulation circuit that demodulates the FM signal, a stereo multiplex circuit that separates left and right stereo signals from the FM demodulated signal from the FM demodulation circuit,
It has a phase comparator, a voltage controlled oscillator, and a frequency divider, and the phase comparator compares the phases of the pilot signal from the FM demodulation circuit and the frequency-divided signal from the frequency divider, and controls the voltage controlled oscillator with its output. A PLL circuit that supplies an accurate pilot signal to the stereo multiplex circuit, a pulse count detector that detects a frequency difference between the frequency-divided signals of the PLL circuit, and control based on the frequency difference signal obtained by the pulse count detector. Consists of a control signal generation circuit that generates signals,
An SN ratio improvement circuit characterized in that the control signal gradually degrades the stereo separation of the output signal of the stereo multiplex circuit to bring it closer to monaural and improve the SN ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19408681A JPS5895444A (en) | 1981-12-01 | 1981-12-01 | Sn ratio improving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19408681A JPS5895444A (en) | 1981-12-01 | 1981-12-01 | Sn ratio improving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5895444A JPS5895444A (en) | 1983-06-07 |
| JPS6313619B2 true JPS6313619B2 (en) | 1988-03-26 |
Family
ID=16318717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19408681A Granted JPS5895444A (en) | 1981-12-01 | 1981-12-01 | Sn ratio improving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895444A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03111167A (en) * | 1989-09-22 | 1991-05-10 | O S G Kk | Manufacture of rolled die |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4901350A (en) * | 1989-04-20 | 1990-02-13 | Delco Electronics Corporation | Closed-loop audio attenuator |
| US5036543A (en) * | 1989-06-30 | 1991-07-30 | Pioneer Electronic Corporation | Noise suppression apparatus for FM receiver |
| US5027402A (en) * | 1989-12-22 | 1991-06-25 | Allegro Microsystems, Inc. | Blend-on-noise stereo decoder |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS452727Y1 (en) * | 1965-09-09 | 1970-02-05 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5859249U (en) * | 1981-10-16 | 1983-04-21 | 富士通テン株式会社 | PLL stereo demodulator |
-
1981
- 1981-12-01 JP JP19408681A patent/JPS5895444A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS452727Y1 (en) * | 1965-09-09 | 1970-02-05 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03111167A (en) * | 1989-09-22 | 1991-05-10 | O S G Kk | Manufacture of rolled die |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5895444A (en) | 1983-06-07 |
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