JPS63129632A - Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation - Google Patents
Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formationInfo
- Publication number
- JPS63129632A JPS63129632A JP27711186A JP27711186A JPS63129632A JP S63129632 A JPS63129632 A JP S63129632A JP 27711186 A JP27711186 A JP 27711186A JP 27711186 A JP27711186 A JP 27711186A JP S63129632 A JPS63129632 A JP S63129632A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- substrate
- gate electrode
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 230000015572 biosynthetic process Effects 0.000 title 2
- 230000007261 regionalization Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 abstract 1
- 229910000070 arsenic hydride Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- -1 GaAs compound Chemical class 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- ZFXYFBGIUFBOJW-UHFFFAOYSA-N theophylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC=N2 ZFXYFBGIUFBOJW-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、開口部を有する絶縁膜のパターンの形成方法
に関し、さらに詳細には電界効果トランジスタの製造等
に好適に用いられる絶縁膜のパターン形成方法とそれを
利用した電界効果トランジスタのゲート電極の形成方法
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming an insulating film pattern having an opening, and more particularly to a method for forming an insulating film pattern suitable for manufacturing field effect transistors. and a method of forming a gate electrode of a field effect transistor using the same.
従来の技術
電界効果トランジスタは半導体基板にオーミック接触さ
れたソースおよびドレインと、ショトキ−接触されたゲ
ートとを有する半導体素子であり、今日広く使用される
ようになっている。BACKGROUND OF THE INVENTION Field effect transistors are semiconductor devices having a source and drain in ohmic contact with a semiconductor substrate and a gate in Schottky contact, and have become widely used today.
このような電界効果型トランジスタにおいて、ゲート電
極と半導体動作層とを分離しかつゲート・ソースまたは
ゲート・ドレイン間の絶縁性を確保するためにＳｉ、Ｎ
、膜あるいはＳｉＯ□膜等の絶縁膜が半導体基板上に設
けられている。このような絶縁膜のパターンを基板上に
形成しその上にゲート電極等の電極を設ける従来の方法
を第２図を参照して説明する。In such field effect transistors, Si, N,
An insulating film such as a film or a SiO□ film is provided on a semiconductor substrate. A conventional method of forming such an insulating film pattern on a substrate and providing an electrode such as a gate electrode thereon will be explained with reference to FIG.
第２図（ａ）に示す如く、まず基板１の全面にＳｉ、Ｎ
。As shown in FIG. 2(a), first, Si, N is applied to the entire surface of the substrate 1.
.
やＳｌＯ□の如き絶縁膜３をＣＶＤ法、スパッタ法等に
より形成する。次いでレジスト膜２を塗布する（第２図
（ｂ）参照）。第２図（Ｃ）に示すように、レジスト膜
２を所定のパターンで露光現像してレジストパターンを
得る。次いで、反応性イオンエツチングを使用して絶縁
膜３の一部を除去した後（第２図（ｄ））、レジスト膜
２を溶剤で流して第２図（ｅ）に示す如き開口部を有す
る絶縁膜のパターンを得る。この絶縁膜を除去した開口
部を含めた領域に第２図（ｆ）に示すようなゲート電極
５を形成していた。An insulating film 3 made of or SlO□ is formed by CVD, sputtering, or the like. Next, a resist film 2 is applied (see FIG. 2(b)). As shown in FIG. 2(C), the resist film 2 is exposed and developed in a predetermined pattern to obtain a resist pattern. Next, after removing a portion of the insulating film 3 using reactive ion etching (FIG. 2(d)), the resist film 2 is flushed with a solvent to form an opening as shown in FIG. 2(e). Obtain an insulating film pattern. A gate electrode 5 as shown in FIG. 2(f) was formed in a region including the opening where the insulating film was removed.
発明の解決しようとする問題点
しかしながら前記従来の方法においては、反応性イオン
エツチング法を用いているので、イオン衝撃のため該イ
オンエツチングされた絶縁膜の真下の基板に損傷を与え
たり、異物を付着させるという問題があった。このため
該イオンエツチングにより開口した部分に電極を設ける
とショットキゲートとしての電気的特性を悪化させてい
た。Problems to be Solved by the Invention However, since the conventional method uses a reactive ion etching method, the ion bombardment may damage the substrate directly below the ion-etched insulating film, or cause foreign matter to be removed. There was a problem with adhesion. For this reason, if an electrode is provided in the portion opened by the ion etching, the electrical characteristics of the Schottky gate will deteriorate.
そこで、本発明の目的は、エツチングされた絶縁膜の下
地である結晶基板に損傷を与えず良好な絶縁特性を有す
る絶縁膜のパターンを形成する方法を提供するものであ
る。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for forming an insulating film pattern having good insulating properties without damaging the crystal substrate underlying the etched insulating film.
問題点を解決するための手段
本発明者等は前記従来の問題点を解決するために鋭意検
討・研究した結果、電子サイクロトロン（ＥＣＲ）共鳴
プラズマＣＶＤ法（以下、ＥＣＲ共鳴プラズマＣＶＤ法
という）を用いることにより、エツチング除去すべく絶
縁膜の下地である基板に損傷を与えることなく良好な絶
縁特性を有する絶縁膜を形成できる方法を見い出した。Means for Solving the Problems As a result of intensive study and research in order to solve the above-mentioned conventional problems, the present inventors have developed the electron cyclotron (ECR) resonance plasma CVD method (hereinafter referred to as the "ECR resonance plasma CVD method"). The inventors have discovered a method by which an insulating film having good insulating properties can be formed without damaging the substrate underlying the insulating film to be removed by etching.
すなわち本発明に従うと、半導体基板上に開口部を有す
る絶縁膜パターンの形成方法であって、上記半導体基板
上にレジスト膜を設け、リソグラフィーによりレジスト
パターンを形成し、該基板上にＥＣＲ共鳴プラズマＣＶ
Ｄ法により絶縁膜を形成し、次にリフトオフにより該レ
ジストパターンおよびその上の絶縁膜を除去する工程を
含むことを特徴とする絶縁膜パターンの形成方法が提供
される。That is, according to the present invention, there is provided a method for forming an insulating film pattern having an opening on a semiconductor substrate, in which a resist film is provided on the semiconductor substrate, a resist pattern is formed by lithography, and ECR resonance plasma CV is applied on the substrate.
A method for forming an insulating film pattern is provided, which includes the steps of forming an insulating film by method D, and then removing the resist pattern and the insulating film thereon by lift-off.
さらに本発明に従い、電界効果トランジスタのゲート電
極の形成方法であって、半導体基板上にレジスト膜を設
け、リソグラフィーによりレジストパターンを形成し、
該基板上にイオン注入して該レジストの側部の該基板内
に自己整合的にイオン注入層を形成し、さらに、該基板
上にＥＣＲ共鳴プラズマＣＶＤ法により絶縁膜を形成し
、次いでリフトオフにより該レジストパターンおよびそ
の上の絶縁膜を除去して開口部を有する絶縁膜パターン
を形成し、該基板をアニールして該イオン注入層を活性
化処理し、リフトオフにより該開口部にゲート電極を形
成する工程を含むことを特徴とする自己整合型ゲート電
極の形成方法が提供される。Further, according to the present invention, there is provided a method for forming a gate electrode of a field effect transistor, comprising: providing a resist film on a semiconductor substrate, forming a resist pattern by lithography;
An ion-implanted layer is formed on the substrate in a self-aligned manner on the side of the resist by ion implantation onto the substrate, an insulating film is formed on the substrate by ECR resonance plasma CVD, and then an insulating film is formed by lift-off. The resist pattern and the insulating film thereon are removed to form an insulating film pattern having an opening, the substrate is annealed to activate the ion implantation layer, and a gate electrode is formed in the opening by lift-off. A method for forming a self-aligned gate electrode is provided, the method comprising the steps of:
本発明の上記のような絶縁膜パターンの形成方法は、５
１３Ｎ４ 、Ｓｔ ０２等の絶縁膜のパターンを採用す
るならば、電界効果トランジスタのゲート電極に限らず
、他の半導体素子の製造工程にも適用可能である。また
、本発明の方法はゲート長がサブミクロンオーダーの場
合においても充分使用可能であり、特に、短ゲート長の
高性能トランジスタの製造に好適である。The method for forming an insulating film pattern as described above according to the present invention includes 5
If an insulating film pattern such as 13N4 or St 02 is employed, it can be applied not only to the gate electrode of a field effect transistor but also to the manufacturing process of other semiconductor devices. Further, the method of the present invention can be satisfactorily used even when the gate length is on the order of submicrons, and is particularly suitable for manufacturing high-performance transistors with short gate lengths.
本発明において上記半導体基板としては、■−Ｖ族の化
合物半導体が好ましく、特にＧａＡｓ化合物半導体が好
ましい。In the present invention, the semiconductor substrate is preferably a ■-V group compound semiconductor, and particularly preferably a GaAs compound semiconductor.
本発明を第１図を参照して説明する。第１図は電界効果
トランジスタの絶縁膜およびゲート電極を形成する工程
の一興体例を示したものであり、本発明は特にこれに限
定されない。The present invention will be explained with reference to FIG. FIG. 1 shows an example of a process for forming an insulating film and a gate electrode of a field effect transistor, and the present invention is not particularly limited thereto.
まず、第１図（ａ）において、ＧａＡｓ等の基板１上に
フォトレジスト等のレジスト膜２を塗布した後、所定の
パターンを露光現像して第１図（ｂ）に示す如きレジス
トパターンを形成する。次いで、基板１上に形成したレ
ジストパターンをマスクとしてＮ＋イオン注入を行ない
、イオン注入層４を自己整合的に形成する（第１図（Ｃ
））。First, in FIG. 1(a), a resist film 2 such as a photoresist is coated on a substrate 1 such as GaAs, and then a prescribed pattern is exposed and developed to form a resist pattern as shown in FIG. 1(b). do. Next, N+ ions are implanted using the resist pattern formed on the substrate 1 as a mask to form an ion implantation layer 4 in a self-aligned manner (see FIG. 1(C)).
)).
次いで、このような基板上に、ＥＣＲプラズマＣＶＤ法
によりＳ １３Ｎ ４等の絶縁膜３を形成する（第１図
（６））。この絶縁膜３は、ＥＣＲプラズマＣＶＤ法の
指向性の特徴によりレジストパターンの側面にはほとん
ど形成されない。Next, an insulating film 3 made of S 13N 4 or the like is formed on such a substrate by ECR plasma CVD (FIG. 1 (6)). This insulating film 3 is hardly formed on the side surfaces of the resist pattern due to the directivity characteristics of the ECR plasma CVD method.
次いで、残っているレジストパターンをウェットエツチ
ングして絶縁膜をリフトオフさせて絶縁膜パターンを形
成すると、第１図（ｅ）に示す如き開口部を有する絶縁
膜パターンが得られる。Next, the remaining resist pattern is wet-etched to lift off the insulating film to form an insulating film pattern, thereby obtaining an insulating film pattern having openings as shown in FIG. 1(e).
このようにして得られた開口部を有する絶縁膜パターン
の基板をＡＳＨｊ中においてアニール処理して、イオン
注入層４を活性化する。次ぎに上記絶縁膜のパターンの
開口部を含む領域にＴｉ／Ｐｔ／Ａｕ等の電極材料を蒸
着し、リフトオフ法により第１図（ｆ）に示すようなゲ
ート電極５を形成することができる。The substrate with the insulating film pattern having the opening thus obtained is annealed in an ASHJ to activate the ion implantation layer 4. Next, an electrode material such as Ti/Pt/Au is deposited in the region including the opening of the insulating film pattern, and a gate electrode 5 as shown in FIG. 1(f) can be formed by a lift-off method.
本発明の方法において用いるＥＣＲプラズマＣＶＤ法と
は、ジャパニーズ・ジャーナル・オブ・アプライド・フ
ィジックス （Ｊａｐａｎｅｓｅ Ｊｏｕｒｎａｌｏｆ
Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ） 、第２２巻、第
２１０頁、１９８３年に開示されているＥＣＲプラズマ
ＣＶＤ装置を利用するものである。The ECR plasma CVD method used in the method of the present invention is described in the Japanese Journal of Applied Physics.
This method uses the ECR plasma CVD apparatus disclosed in Applied Physics, Volume 22, Page 210, 1983.
ＥＣＲプラズマＣＶＤ装置は、プラズマ室と反応室（試
料）とを含み、プラズマ室はマイクロ波導波管と隔壁板
を介して接続され、またその周囲には電磁石が設けられ
ていてプラズマ室内にマイクロ波とともにＥＣＲ条件を
確立し、反応室内でプラズマを引出すための発散磁界を
形成し得るようになっている。このプラズマ室はプラズ
マ引出窓を介して反応室と接続しており、プラズマが試
料台上に載せられた試料に向けて発散磁界により加速さ
れ導かれるようになっている。An ECR plasma CVD apparatus includes a plasma chamber and a reaction chamber (sample), and the plasma chamber is connected to a microwave waveguide via a partition plate, and an electromagnet is installed around the waveguide to transmit microwaves into the plasma chamber. Together with this, it is possible to establish ECR conditions and form a divergent magnetic field for drawing out plasma within the reaction chamber. This plasma chamber is connected to the reaction chamber via a plasma extraction window, and plasma is accelerated and guided by a divergent magnetic field toward a sample placed on a sample stage.
この装置によれば、Ｎ２．０□、ＮＨ３あるいはこれら
の混合ガスなどがマイクロ波と磁界とによりＥＣＲ条件
が設定されたプラズマ室内に送られ、プラズマ化された
ガスが発散磁界により誘導されて反応室に送られる。一
方で、反応室には試料台２に載置された基板があり、ま
たＳｉＨ，，５ｉ３Ｈａ、５ｔ２８ｓなどの絶縁膜形成
用原料ガスが反応室に供給され、これが上記プラズマに
よって励起活性化され、反応を生じて所定の反応生成物
が基板上に堆積する。′
本発明において、ＥＣＲプラズマ法により形成する絶縁
膜としては、Ｓｉ３Ｎ４．５ｉ０２ 、シリコン窒化酸
化膜が好ましい。According to this device, N2.0□, NH3, or a mixture of these gases is sent into a plasma chamber in which ECR conditions are set using microwaves and a magnetic field, and the plasma gas is induced by the divergent magnetic field and reacts. Sent to room. On the other hand, in the reaction chamber, there is a substrate placed on a sample stage 2, and a raw material gas for forming an insulating film such as SiH, 5i3Ha, 5t28s is supplied to the reaction chamber, and this is excited and activated by the plasma. A reaction occurs and a predetermined reaction product is deposited on the substrate. ' In the present invention, the insulating film formed by the ECR plasma method is preferably Si3N4.5i02 or silicon nitride oxide film.
作用
電界効果トランジスタ等を製造する工程において基板上
にゲート電極等を設けるための開口部を有する絶縁膜の
パターンを形成する必要がある。In the process of manufacturing working field effect transistors and the like, it is necessary to form an insulating film pattern having an opening for providing a gate electrode and the like on a substrate.
従来法では基板全面に絶縁膜をプラズマＣＶＤ法、常圧
または減圧ＣＶＤ法、スパッタ法等により成膜しその上
にレジストパターンを形成させた後、反応性イオンエツ
チングを使用して絶縁膜の一部を除去して絶縁膜のパタ
ーンを形成していた。In the conventional method, an insulating film is formed on the entire surface of the substrate by plasma CVD, normal pressure or low pressure CVD, sputtering, etc., a resist pattern is formed thereon, and then reactive ion etching is used to remove part of the insulating film. The pattern of the insulating film was formed by removing the portion.
しかし、反応性イオンエツチングを使用した際、反応性
プラズマによりエツチングされた絶縁膜の下地である結
晶基板が損傷を受けるという欠点があった口
しかしながら、本発明はＥＣＲ７’ラズマ法を用いてい
るのでリフトオフによる絶縁膜のパターン形成が容易に
行なえ、しかも反応性イオンエツチングを用いる必要が
なくなる。ＥＣＲプラズマ法を用いると低温で成膜でき
るという利点とともに、プラズマの基板への指向性が優
れているためプラズマから基板への方向以外の部分すな
わち基板やパターンの側面に膜が形成されない。従って
、リフトオフが他のＣＶＤ等の成膜方法に比べて極めて
容易に行なえるようになる。However, when using reactive ion etching, there was a drawback that the crystal substrate underlying the insulating film etched by the reactive plasma was damaged. However, the present invention uses the ECR7' lasma method. Patterning of the insulating film can be easily performed by lift-off, and there is no need to use reactive ion etching. The ECR plasma method has the advantage of being able to form a film at a low temperature, and also has excellent directivity of the plasma toward the substrate, so that no film is formed in areas other than the direction from the plasma to the substrate, that is, on the sides of the substrate or pattern. Therefore, lift-off can be performed extremely easily compared to other film forming methods such as CVD.
また、生成した膜の膜質が良く、耐エツチング性に富み
、８００℃程度のアニールによっても剥離せず、Ｇａお
よびＡｓの拡散を抑制できる優れた膜を提供する。Further, the produced film has good film quality, is rich in etching resistance, does not peel off even after annealing at about 800° C., and provides an excellent film that can suppress the diffusion of Ga and As.
このような本発明の絶縁膜の形成方法に従えば、ゲート
電極等を設けるための下地である基板に損傷を与えるこ
とがないので電極と基板のコンタクト抵抗が低減される
とともに、エツチング時の異物付着等が生じることがな
いため良好な絶縁機能が達成される。According to the method for forming an insulating film of the present invention, there is no damage to the substrate, which is the base for forming the gate electrode, etc., so the contact resistance between the electrode and the substrate is reduced, and foreign particles are removed during etching. Since no adhesion occurs, a good insulation function is achieved.
実施例
次に本発明を実施例により詳細に説明するが、本発明は
これらに何ら限定されるものではない。EXAMPLES Next, the present invention will be explained in detail by examples, but the present invention is not limited thereto.
実施例１
第１図に示したような本発明の工程に従って、以下のよ
うにして基板上に電界効果トランジスタ用の絶縁膜のパ
ターンおよびゲート電極を形成した。Example 1 According to the process of the present invention as shown in FIG. 1, an insulating film pattern and a gate electrode for a field effect transistor were formed on a substrate in the following manner.
まず、半導体基板としてＧａＡｓ基板を用い、その上に
フォトレジスト膜（ＡＺ−１４００）を全面に塗布し、
所定のパターンを露光した後、現像してレジストパター
ンを形成しに０次に、基板上に形成したレジストをマス
クとして注入イオンを２８３１＊ とじ注入濃度を３Ｘ
１０′３／ｃ＋＋ｆ程度としてイオン注入を行なった。First, a GaAs substrate is used as a semiconductor substrate, and a photoresist film (AZ-1400) is applied over the entire surface.
After exposing a predetermined pattern, it is developed to form a resist pattern.Next, the resist formed on the substrate is used as a mask to implant ions at 2831* and the implantation concentration is 3X.
Ion implantation was performed at a concentration of about 10'3/c++f.
次に、ＥＣＲプラズマＣＶＤ装置により、５ｉＨ１とＮ
Ｈｓ とＮ２の混合ガスを用いて５１３Ｎ４膜を膜厚
が１５００人程度になるように形成した。次いで、ウェ
ットエツチングにより上記レジストパターンのマスクを
除去して、リフトオフを行なうことにより絶縁膜パター
ンを形成させた。次いでこのような基板をＡｓＨａ中に
ふいて温度を約８００℃とし、３０分間アニール処理し
た。そして、この絶縁膜パターンにより基板の表面が露
出している部分を含む全面にＴｉ／Ｐｔ／Ａｕ系の電極
材料を蒸着し、リフトオフ法によりゲート電極を形成し
た。このようにして形成した絶縁膜の機能を調べるため
上記ゲート電極を形成した基板上にソースおよびドレイ
ン電極を設けて相互コンダクタンス（ｇｌ）を測定した
ところ２３０ｍ５ ／ ｍｍであった。Next, 5iH1 and N
A 513N4 film was formed using a mixed gas of Hs and N2 to a thickness of approximately 1500 mm. Next, the mask of the resist pattern was removed by wet etching, and an insulating film pattern was formed by performing lift-off. The substrate was then immersed in AsHa and annealed at a temperature of about 800° C. for 30 minutes. Then, a Ti/Pt/Au based electrode material was deposited on the entire surface of the substrate including the exposed portion of the surface of the substrate due to this insulating film pattern, and a gate electrode was formed by a lift-off method. In order to investigate the function of the insulating film thus formed, source and drain electrodes were provided on the substrate on which the gate electrode was formed, and the mutual conductance (gl) was measured and found to be 230 m5/mm.
比較例
実施例１で作製したＳｉ３Ｎ、絶縁膜およびゲート電極
を備えたＧａＡｓ基板を第２図に示した反応性イオンエ
ツチングを使用した従来の方法により以下のようにして
作製した。Comparative Example The GaAs substrate provided with the Si3N, insulating film, and gate electrode prepared in Example 1 was prepared as follows by a conventional method using reactive ion etching as shown in FIG.
実施例１と同様な方法でイオン注入を行なったＧａＡｓ
基板に、プラズマＣＶＤ法を使用して膜厚１５００人の
３１３ Ｎ ４膜を形成させた。この上にレジスト膜（
ＡＺ−１４００）を塗布し、パターンに従って露光しウ
ェットエツチングによりレジストパターンを作製した後
、反応性イオンエツチング法によりＣＦ、ガスを用いて
５ｉｉＮａ膜をエツチングした。GaAs was ion-implanted using the same method as in Example 1.
A 313 N 4 film having a thickness of 1500 nm was formed on the substrate using a plasma CVD method. On top of this is a resist film (
AZ-1400) was applied, exposed according to the pattern, and wet etched to produce a resist pattern, and then the 5iiNa film was etched using CF and gas by reactive ion etching.
この後パターン化した絶縁膜に実施例１と同様にしてゲ
ート電極を形成し、ソースおよびドレイン電極を設けて
相互コンダクタンス（ｇつ）を測定したところ１７０＋
ｙ＋Ｓ ／ ｍｍであった。After that, a gate electrode was formed on the patterned insulating film in the same manner as in Example 1, a source and a drain electrode were provided, and the mutual conductance (g) was measured to be 170 +
It was y+S/mm.
発明の効果
本発明の方法を用いることにより、電極を形成すべく結
晶基板に損傷を与えないで良好な絶縁特性を有する絶縁
膜のパターンを形成することができる。Effects of the Invention By using the method of the present invention, it is possible to form an insulating film pattern having good insulating properties without damaging a crystal substrate for forming an electrode.
従って、本発明の方法を電界効果トランジスタ等の製造
方法に用いることで良好な電気的特性を有する素子を製
造することができ、その工業的価値は極めて高い。Therefore, by using the method of the present invention in a method for manufacturing field effect transistors and the like, devices having good electrical characteristics can be manufactured, and the industrial value thereof is extremely high.
第１図は本発明の絶縁膜のパターン形成方法の工程を示
す図である。
第２図は従来の絶縁膜のパターン形成方法の工程を示す
図である。
（主な参照番号）
１・・半導体基板、 ２・・レジスト膜、３・・絶縁膜
、 ４・・イオン注入層、５・・ゲート電極FIG. 1 is a diagram showing the steps of the insulating film pattern forming method of the present invention. FIG. 2 is a diagram showing the steps of a conventional insulating film pattern forming method. (Main reference numbers) 1. Semiconductor substrate, 2. Resist film, 3. Insulating film, 4. Ion implantation layer, 5. Gate electrode
Claims (8)
形成方法であって、上記半導体基板上にレジスト膜を設
け、リソグラフィーによりレジストパターンを形成し、
該基板上に電子サイクロトロン共鳴プラズマＣＶＤ法に
より絶縁膜を形成し、次にリフトオフにより該レジスト
パターンおよびその上の絶縁膜を除去する工程を含むこ
とを特徴とする絶縁膜パターンの形成方法。(1) A method for forming an insulating film pattern having an opening on a semiconductor substrate, the method comprising: providing a resist film on the semiconductor substrate, forming a resist pattern by lithography;
A method for forming an insulating film pattern, comprising the steps of forming an insulating film on the substrate by electron cyclotron resonance plasma CVD, and then removing the resist pattern and the insulating film thereon by lift-off.
シリコン窒化酸化膜のいずれかであることを特徴とする
特許請求の範囲第１項記載の絶縁膜パターンの形成方法
。(2) The insulating film is a silicon nitride film, a silicon oxide film,
2. The method of forming an insulating film pattern according to claim 1, wherein the insulating film pattern is a silicon nitride oxide film.
ことを特徴とする特許請求の範囲第１項または第２項記
載の絶縁膜パターンの形成方法。(3) The method for forming an insulating film pattern according to claim 1 or 2, wherein the semiconductor substrate is a III-V group compound semiconductor.
とを特徴とする特許請求の範囲第３項記載の絶縁膜パタ
ーンの形成方法。(4) The method for forming an insulating film pattern according to claim 3, wherein the III-V compound semiconductor is GaAs.
あって、半導体基板上にレジスト膜を設け、リソグラフ
ィーによりレジストパターンを形成し、該基板上にイオ
ン注入して該レジストの側部の該基板内にイオン注入層
を形成し、さらに、該基板上に電子サイクロトロン共鳴
プラズマＣＶＤ法により絶縁膜を形成し、次いでリフト
オフにより該レジストパターンおよびその上の絶縁膜を
除去して開口部を有する絶縁膜パターンを形成し、該基
板をアニールして該イオン注入層を活性化処理し、リフ
トオフにより該開口部にゲート電極を形成する工程を含
むことを特徴とする自己整合型ゲート電極の形成方法。(5) A method for forming a gate electrode of a field effect transistor, which comprises providing a resist film on a semiconductor substrate, forming a resist pattern by lithography, and implanting ions into the substrate on the side of the resist. An ion implantation layer is formed on the substrate, an insulating film is formed on the substrate by electron cyclotron resonance plasma CVD, and then the resist pattern and the insulating film thereon are removed by lift-off to form an insulating film pattern having an opening. 1. A method for forming a self-aligned gate electrode, comprising the steps of: forming a gate electrode, annealing the substrate to activate the ion-implanted layer, and forming a gate electrode in the opening by lift-off.
シリコン窒化酸化膜のいずれかであることを特徴とする
特許請求の範囲第５項記載の自己整合型ゲート電極の形
成方法。(6) The insulating film is a silicon nitride film, a silicon oxide film,
6. The method for forming a self-aligned gate electrode according to claim 5, wherein the gate electrode is formed of a silicon nitride oxide film.
ことを特徴とする特許請求の範囲第５項または第６項記
載の自己整合型ゲート電極の形成方法。(7) The method for forming a self-aligned gate electrode according to claim 5 or 6, wherein the semiconductor substrate is a III-V group compound semiconductor.
とを特徴とする特許請求の範囲第７項記載の自己整合型
ゲート電極の形成方法。(8) The method for forming a self-aligned gate electrode according to claim 7, wherein the III-V group compound semiconductor is GaAs.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27711186A JPS63129632A (en) | 1986-11-20 | 1986-11-20 | Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation |
| DE3751219T DE3751219T2 (en) | 1986-11-20 | 1987-11-19 | Method of manufacturing a Schottky barrier field effect transistor. |
| EP87117099A EP0268298B1 (en) | 1986-11-20 | 1987-11-19 | Method of producing a Schottky-barrier field effect transistor |
| US07/122,438 US4859618A (en) | 1986-11-20 | 1987-11-19 | Method of producing the gate electrode of a field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27711186A JPS63129632A (en) | 1986-11-20 | 1986-11-20 | Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63129632A true JPS63129632A (en) | 1988-06-02 |
Family
ID=17578936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27711186A Pending JPS63129632A (en) | 1986-11-20 | 1986-11-20 | Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63129632A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282577A (en) * | 1988-09-19 | 1990-03-23 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPH0282578A (en) * | 1988-09-19 | 1990-03-23 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPH0574763A (en) * | 1991-07-19 | 1993-03-26 | G T C:Kk | Formation of gate insulating film |
| KR100587036B1 (en) * | 1999-10-25 | 2006-06-07 | 주식회사 하이닉스반도체 | Contact formation method of semiconductor device |
| US7411279B2 (en) | 2004-06-30 | 2008-08-12 | Endwave Corporation | Component interconnect with substrate shielding |
| US7588966B2 (en) | 2004-06-30 | 2009-09-15 | Endwave Corporation | Chip mounting with flowable layer |
| JP2014029983A (en) * | 2012-07-05 | 2014-02-13 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
-
1986
- 1986-11-20 JP JP27711186A patent/JPS63129632A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282577A (en) * | 1988-09-19 | 1990-03-23 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPH0282578A (en) * | 1988-09-19 | 1990-03-23 | Seiko Epson Corp | Manufacture of thin film transistor |
| JPH0574763A (en) * | 1991-07-19 | 1993-03-26 | G T C:Kk | Formation of gate insulating film |
| KR100587036B1 (en) * | 1999-10-25 | 2006-06-07 | 주식회사 하이닉스반도체 | Contact formation method of semiconductor device |
| US7411279B2 (en) | 2004-06-30 | 2008-08-12 | Endwave Corporation | Component interconnect with substrate shielding |
| US7588966B2 (en) | 2004-06-30 | 2009-09-15 | Endwave Corporation | Chip mounting with flowable layer |
| JP2014029983A (en) * | 2012-07-05 | 2014-02-13 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
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