JPS63124742U - - Google Patents

Info

Publication number
JPS63124742U
JPS63124742U JP1987015007U JP1500787U JPS63124742U JP S63124742 U JPS63124742 U JP S63124742U JP 1987015007 U JP1987015007 U JP 1987015007U JP 1500787 U JP1500787 U JP 1500787U JP S63124742 U JPS63124742 U JP S63124742U
Authority
JP
Japan
Prior art keywords
electrodes
insulating plate
package
external electrode
insulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987015007U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987015007U priority Critical patent/JPS63124742U/ja
Publication of JPS63124742U publication Critical patent/JPS63124742U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すパツケージ
の斜視図、第２図は、第１図のパツケージを裏面
より見た斜視図、第３図は従来のパツケージにＧ
ａＡｓＦＥＴのチツプを装着した状態を示す上面
図、第４図は従来のパツケージの斜視図、第５図
はＧａＡｓＦＥＴのチツプの拡大斜視図である。 図において、１はＧａＡｓＦＥＴのチツプ、２
はこの考案のパツケージである絶縁板、３ａ，４
ａ，５ａ，６ａはＧａＡｓＦＥＴのチツプとを接
続する電極、３ｂ，４ｂ，５ｂ，６ｂは外部電極
端子である。なお、各図中の同一符号は同一また
は相当部分を示す。 Fig. 1 is a perspective view of a package showing an embodiment of this invention, Fig. 2 is a perspective view of the package shown in Fig. 1 seen from the back, and Fig. 3 is a perspective view of a conventional package.
FIG. 4 is a perspective view of a conventional package, and FIG. 5 is an enlarged perspective view of the GaAsFET chip. In the figure, 1 is a GaAsFET chip, 2
are insulating plates, 3a and 4, which are the package of this invention.
Reference numerals a, 5a, and 6a are electrodes connected to the GaAsFET chip, and 3b, 4b, 5b, and 6b are external electrode terminals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁板上に互いに絶縁して複数個の電極を形成
し、これら電極と前記絶縁板上に取り付けられた
半導体チツプとを金線により接続し、前記複数個
の電極とそれぞれ導通のある外部電極端子を前記
絶縁板の裏面に設けたことを特徴とする半導体装
置用パツケージ。 A plurality of electrodes are formed on an insulating plate so as to be insulated from each other, and these electrodes are connected to a semiconductor chip mounted on the insulating plate by a gold wire, and an external electrode terminal is electrically connected to each of the plurality of electrodes. A package for a semiconductor device, characterized in that: is provided on the back surface of the insulating plate.
JP1987015007U 1987-02-04 1987-02-04 Pending JPS63124742U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987015007U JPS63124742U (en) 1987-02-04 1987-02-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987015007U JPS63124742U (en) 1987-02-04 1987-02-04

Publications (1)

Publication Number Publication Date
JPS63124742U true JPS63124742U (en) 1988-08-15

Family

ID=30805536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987015007U Pending JPS63124742U (en) 1987-02-04 1987-02-04

Country Status (1)

Country Link
JP (1) JPS63124742U (en)

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