JPS6282736U - - Google Patents
Info
- Publication number
- JPS6282736U JPS6282736U JP1985174362U JP17436285U JPS6282736U JP S6282736 U JPS6282736 U JP S6282736U JP 1985174362 U JP1985174362 U JP 1985174362U JP 17436285 U JP17436285 U JP 17436285U JP S6282736 U JPS6282736 U JP S6282736U
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- insulating base
- conductive path
- base substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す断面図、第２図
は本考案の他の実施例を示す断面図、第３図およ
び第４図は従来例を示す断面図である。
１……金属基板、２……導電路、３……絶縁ベ
ース基板、４……半導体素子、５，７……導体、
６……Ａｌワイヤー線。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIGS. 3 and 4 are sectional views showing a conventional example. 1...Metal substrate, 2...Conducting path, 3...Insulating base substrate, 4...Semiconductor element, 5, 7...Conductor,
6...Al wire line.
Claims (1)
導電路と、前記金属基板上の少なくとも一カ所に
固着された半導体材料からなる絶縁ベース基板と
、該絶縁ベース基板に設けられた導体と、該導電
路上にフエイスダウン接続される半導体素子とを
具備し、前記金属基板上に設けた導電路と前記絶
縁ベース基板上に設けた導体とをボンデイングワ
イヤーで電気的接続することを特徴とした混成集
積回路。 a metal substrate, a conductive path of a desired shape provided on the metal substrate, an insulating base substrate made of a semiconductor material fixed to at least one location on the metal substrate, and a conductor provided on the insulating base substrate; A hybrid device comprising a semiconductor element connected face-down on the conductive path, and electrically connecting the conductive path provided on the metal substrate and the conductor provided on the insulating base substrate with a bonding wire. integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985174362U JPS6282736U (en) | 1985-11-13 | 1985-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985174362U JPS6282736U (en) | 1985-11-13 | 1985-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6282736U true JPS6282736U (en) | 1987-05-27 |
Family
ID=31112672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985174362U Pending JPS6282736U (en) | 1985-11-13 | 1985-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6282736U (en) |
-
1985
- 1985-11-13 JP JP1985174362U patent/JPS6282736U/ja active Pending