JPS63124414A - Ashing apparatus - Google Patents
Ashing apparatusInfo
- Publication number
- JPS63124414A JPS63124414A JP27009886A JP27009886A JPS63124414A JP S63124414 A JPS63124414 A JP S63124414A JP 27009886 A JP27009886 A JP 27009886A JP 27009886 A JP27009886 A JP 27009886A JP S63124414 A JPS63124414 A JP S63124414A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- ozone
- ashing
- wafer
- heating means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004380 ashing Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 31
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
オゾンを利用してレジスト等を焼却除去するアッシング
装置の改良である。[Detailed Description of the Invention] [Summary] This is an improvement of an ashing device that uses ozone to incinerate and remove resist and the like.
面積の大きな半導体ウェーハ面に塗布されているレジス
ト等を均一にアッシングすることを可能にするため、半
導体ウェーハ面に均一にオゾンを分布供給するために多
孔板を設け、この多孔板と半導体ウェーハとの間隔を１
０ｍｍ以下にしたアッシング装置である。In order to make it possible to uniformly ash the resist, etc. applied to the semiconductor wafer surface, which has a large area, a perforated plate is provided to uniformly distribute and supply ozone to the semiconductor wafer surface. the interval of 1
This is an ashing device with a thickness of 0 mm or less.
半導体装置の製造方法において、リソグラフィー法は必
要であり、このリソグラフィー法において使用されるレ
ジスト等を焼却除去するために、従来は、酸素プラズマ
を使用していたが、酸素プラズマは荷電粒子であるため
、半導体ウェーハにダメージを与えやすいという欠点が
ある。そこで、この欠点を解消するため、非荷電性の酸
化剤としてオゾンを使用してアッシングする手法が開発
された。本発明はこのオゾンを使用してなすアッシング
装置の改良である。The lithography method is necessary in the manufacturing method of semiconductor devices, and in order to incinerate and remove the resist used in this lithography method, oxygen plasma has traditionally been used, but since oxygen plasma is charged particles, However, it has the disadvantage of easily damaging semiconductor wafers. Therefore, in order to overcome this drawback, an ashing method using ozone as a non-charged oxidizing agent was developed. The present invention is an improvement of an ashing device using this ozone.
従来技術に係るアッシング装置は、第２図に示すように
、オゾン供給系２と排気系３と半導体ウェーハ支持台４
と加熱手段５とを有する気密容器１よりなるが、オゾン
供給系２の先端はノズル２１とされており、そのため、
このノズル２１の先端とウェーハ面との間隔は５０〜１
００ ｍｍ程度が一般であった。As shown in FIG. 2, the conventional ashing apparatus includes an ozone supply system 2, an exhaust system 3, and a semiconductor wafer support 4.
It consists of an airtight container 1 having a heating means 5 and a nozzle 21 at the tip of the ozone supply system 2.
The distance between the tip of this nozzle 21 and the wafer surface is 50 to 1
Generally, it was about 0.00 mm.
ところが、従来の技術に係るアッシング装置を使用して
アッシングすると、第３図に示すように半導体ウェーハ
の中央部のみはアッシングされるが、周辺部はアッシン
グされず、均一にアッシングできる面積は１ 、０００
ｍｍ２程度が限度であり、工業的に実用に耐えないとい
う欠点があった。However, when ashing is performed using a conventional ashing device, only the central part of the semiconductor wafer is ashed as shown in FIG. 3, but the peripheral part is not ashed, and the area that can be uniformly ashed is 1. 000
The limit is about mm2, which has the disadvantage of not being industrially practical.
本発明の目的は、この欠点を解消することにあり、広い
面積の半導体ウェーハ面に塗布されているレジスト等を
均一に、しかも迅速に、除去しうるアッシング装置を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback, and to provide an ashing device that can uniformly and quickly remove resist and the like coated on a wide area of a semiconductor wafer.
上記の目的を達成するために本発明が採った手段は、オ
ゾン供給系２と排気系３と半導体ウェーハ支持台４と加
熱手段５とを有する気密容器１よりなるアッシング装置
に、半導体ウェーハ支持台４に支持される半導体ウェー
ハ６に向ってオゾンを分布供給する多孔板７を付加し、
この多孔板７と半導体ウェーハ６との間隔を１０ｍｍ以
下としたことにある。The means taken by the present invention to achieve the above object is that an ashing apparatus comprising an airtight container 1 having an ozone supply system 2, an exhaust system 3, a semiconductor wafer support 4, and a heating means 5 is provided with a semiconductor wafer support. A porous plate 7 is added to supply ozone in a distributed manner toward the semiconductor wafer 6 supported by the semiconductor wafer 4.
The reason is that the distance between the porous plate 7 and the semiconductor wafer 6 is 10 mm or less.
上記の欠点は、オゾン供給系としてのノズルから供給さ
れるオゾンが半導体ウェーハの中央部のみに供給される
からであると思われる。The above drawback is thought to be due to the fact that the ozone supplied from the nozzle as the ozone supply system is supplied only to the center of the semiconductor wafer.
そこで、オゾンを半導体ウェーハの全面に均一に供給す
れば、この欠点は解消しうるであろうとの着想を得て、
第４図に示すように、孔が５〜１０ｍｍ程度の間隔をも
って分布形成されている多孔板７１をノズル２１と半導
体ウェーハ６との間に介在させ、多孔板７１と半導体ウ
ェーハ６との間隔は従来の技術の場合と同様に５０〜１
００ ｍｍに保持し、一方、孔の間隔は種々に変化させ
て実験を繰返した。この実験によれば、上記の多孔板７
１の付加は均一にアッシングしうる面積を増大する効果
を有することは認められるが、孔の間隔は、上記の範囲
においては均一にアッシングしうる面積に対して中立で
あることが確認された。たＣ１それと同時に、アッシン
グ速度が極めて遅く側底実用に供しがたいことも判明し
た。Therefore, I got the idea that this drawback could be overcome by uniformly supplying ozone to the entire surface of the semiconductor wafer.
As shown in FIG. 4, a perforated plate 71 having holes distributed at intervals of about 5 to 10 mm is interposed between the nozzle 21 and the semiconductor wafer 6, and the interval between the perforated plate 71 and the semiconductor wafer 6 is 50-1 as in the case of conventional technology
00 mm, while the experiment was repeated with various hole spacings. According to this experiment, the above porous plate 7
Although it is recognized that the addition of 1 has the effect of increasing the area that can be uniformly ashed, it was confirmed that the hole spacing is neutral with respect to the area that can be uniformly ashed within the above range. At the same time, it was also found that the ashing speed of C1 was extremely slow and it was difficult to put it to practical use on the side bottom.
そこで、次に、多孔板７１と半導体ウェーハ６との間隔
を種々に変化させて実験を繰返したところ、第５図に示
すように、顕著な関係のあることが発見された。この実
験の結果によれば、多孔板７１と半導体ウェー八６との
間隔が１０ｍｍ以下であると、その間隔が５０〜１００
ｍｍの場合に比し、２倍以上であり、十分実用に供し
うることが確認された。Then, when the experiment was repeated by variously changing the distance between the porous plate 71 and the semiconductor wafer 6, it was discovered that there was a significant relationship as shown in FIG. According to the results of this experiment, when the distance between the perforated plate 71 and the semiconductor wafer 86 is 10 mm or less, the distance is 50 to 100 mm.
It was confirmed that it is more than twice as large as that in the case of mm, and is sufficiently usable for practical use.
本発明はこの新たに発見された作用（オゾン供給系２と
半導体ウェーハ６との間に多孔板７を付加し、この多孔
板７と半導体ウェーハ６との間隔を１０ｍｍ以下とする
と、高いアッシング速度をもって、しかも、均一にアッ
シングしうる面積を増大する作用）を利用したものであ
る。The present invention utilizes this newly discovered effect (adding a perforated plate 7 between the ozone supply system 2 and the semiconductor wafer 6, and setting the distance between the perforated plate 7 and the semiconductor wafer 6 to 10 mm or less, increasing the ashing rate. This method utilizes the effect of increasing the area that can be uniformly ashed.
以下、図面を参照しつ〜、本発明の一実施例に係るアッ
シング装置についてさらに説明する。Hereinafter, an ashing device according to an embodiment of the present invention will be further described with reference to the drawings.
第１図参照
図は本発明の一実施例に係るアッシング装置の構造図を
示す。図において、１は気密容器であり、２はオゾン供
給系であり、オゾナイザ２２と配管２３とノズル２１と
よりなる。３は排気系である。４は半導体ウェーハ６を
支持する半導体支持台であり、加熱手段５と一体とされ
る場合が多い。Referring to FIG. 1, a structural diagram of an ashing device according to an embodiment of the present invention is shown. In the figure, 1 is an airtight container, and 2 is an ozone supply system, which includes an ozonizer 22, piping 23, and a nozzle 21. 3 is an exhaust system. 4 is a semiconductor support stand that supports the semiconductor wafer 6, and is often integrated with the heating means 5.
７が本発明の要旨に係る多孔板であり、この例において
は１０ｍｍ間隔をもって径１ 、５ｍｍの孔が格子状に
配置されており、半導体ウェー八６の面との間隔が１０
ｍｍ以下になるように配置されている。Reference numeral 7 denotes a perforated plate according to the gist of the present invention, and in this example, holes with diameters of 1 and 5 mm are arranged in a lattice shape at 10 mm intervals, and the distance from the surface of the semiconductor wafer 8 is 10 mm.
mm or less.
アッシングの実施にあたっては、アッシング装置の半導
体ウェーハ支持台４に半導体ウェーハ６を乗せ、オゾン
と酸素との混合ガス（総流量は５ＳＬＭ、オゾン濃度は
約５％）を供給して内圧は１気圧に保持し、加熱手段５
を使用して、内部温度を約２８０°Ｃに制御する。To carry out ashing, the semiconductor wafer 6 is placed on the semiconductor wafer support 4 of the ashing device, and a mixed gas of ozone and oxygen (total flow rate is 5SLM, ozone concentration is approximately 5%) is supplied to bring the internal pressure to 1 atm. Holding and heating means 5
to control the internal temperature at approximately 280°C.
以上の工程により、４０，０００ｍｍ２以下の面積を有
する半導体ウェーハに対して１ｐ、ｍ７分のアッシング
レートが実現する。Through the above steps, an ashing rate of 1p, m7 is achieved for a semiconductor wafer having an area of 40,000 mm2 or less.
以上説明せるとおり、本発明に係るアッシング装置（オ
ゾン供給系と排気系と半導体ウェーハ支持台と加熱手段
とを有する気密容器よりなるアッシング装置）には、半
導体ウェーハ支持台に支持される半導体ウェーハに向っ
てオゾンを分布供給する多孔板が設けられており、多孔
板と半導体ウェーハとの間隔は１０ｍｍ以下とされてい
るので、広い面積の半導体ウェーハ面に塗布されている
レジスト等を均一に、しかも迅速に、除去することがで
きる。As explained above, the ashing apparatus according to the present invention (the ashing apparatus consisting of an airtight container having an ozone supply system, an exhaust system, a semiconductor wafer support stand, and a heating means) has the following features: A perforated plate is provided to distribute ozone to the semiconductor wafer, and the distance between the perforated plate and the semiconductor wafer is set to 10 mm or less, so that the resist applied over a wide area of the semiconductor wafer can be uniformly applied. Can be removed quickly.
第１図は、本発明の一実施例に係るアッシング装置の構
成図である。
第２図は、従来技術に係るアッシング装置の構成図であ
る。
第３図は、本発明の詳細な説明する図である。
第４図は、本発明の着想具体化のための実験に使用され
た多孔板の図である。
第５図は、本発明の効果を示すグラフである。
１・・・気密容器、
２０拳・オゾン供給系、
２１・・・ノズル、
２２１１・・オゾナイザ、
２３・・・配管、
３・・・排気系、
４・Φ−半導体ウェーハ支持台、
５・争・加熱手段、
６拳・・半導体ウェーハ、
７・・拳多孔板。
Ｆ 哨
口FIG. 1 is a configuration diagram of an ashing device according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an ashing device according to the prior art. FIG. 3 is a diagram illustrating the present invention in detail. FIG. 4 is a diagram of a perforated plate used in an experiment to realize the idea of the present invention. FIG. 5 is a graph showing the effects of the present invention. 1... Airtight container, 20 ozone supply system, 21... Nozzle, 2211... Ozonizer, 23... Piping, 3... Exhaust system, 4. Φ-Semiconductor wafer support stand, 5. War・Heating means, 6. Semiconductor wafer, 7. Perforated plate. F guard gate
Claims (1)
支持台（４）と加熱手段（５）とを有する気密容器（１
）よりなるアッシング装置において、 前記アッシング装置には、前記半導体ウェーハ支持台（
４）に支持される半導体ウェーハ（６）に向ってオゾン
を分布供給する多孔板（７）が設けられており、該多孔
板（７）と前記半導体ウェーハ（６）との間隔は１０ｍ
ｍ以下とされてなることを特徴とするアッシング装置。[Claims] An airtight container (1) having an ozone supply system (2), an exhaust system (3), a semiconductor wafer support stand (4), and a heating means (5).
), wherein the ashing device includes the semiconductor wafer support (
A perforated plate (7) is provided that supplies ozone in a distributed manner toward the semiconductor wafer (6) supported by the semiconductor wafer (6), and the distance between the perforated plate (7) and the semiconductor wafer (6) is 10 m.
An ashing device characterized in that it has an ashing capacity of less than m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27009886A JPS63124414A (en) | 1986-11-13 | 1986-11-13 | Ashing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27009886A JPS63124414A (en) | 1986-11-13 | 1986-11-13 | Ashing apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63124414A true JPS63124414A (en) | 1988-05-27 |
Family
ID=17481505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27009886A Pending JPS63124414A (en) | 1986-11-13 | 1986-11-13 | Ashing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63124414A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164218A (en) * | 1986-12-25 | 1988-07-07 | Tokyo Electron Ltd | Ashing device |
| JPH02183526A (en) * | 1989-01-10 | 1990-07-18 | Ulvac Corp | Plasma ashing device |
| KR20030065217A (en) * | 2002-01-31 | 2003-08-06 | 삼성전자주식회사 | Wafer chuck and apparatus for processing of wafer having the same |
-
1986
- 1986-11-13 JP JP27009886A patent/JPS63124414A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164218A (en) * | 1986-12-25 | 1988-07-07 | Tokyo Electron Ltd | Ashing device |
| JPH06103661B2 (en) * | 1986-12-25 | 1994-12-14 | 東京エレクトロン株式会社 | Asssing device |
| JPH02183526A (en) * | 1989-01-10 | 1990-07-18 | Ulvac Corp | Plasma ashing device |
| KR20030065217A (en) * | 2002-01-31 | 2003-08-06 | 삼성전자주식회사 | Wafer chuck and apparatus for processing of wafer having the same |
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