JPS63119288A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPS63119288A JPS63119288A JP61265078A JP26507886A JPS63119288A JP S63119288 A JPS63119288 A JP S63119288A JP 61265078 A JP61265078 A JP 61265078A JP 26507886 A JP26507886 A JP 26507886A JP S63119288 A JPS63119288 A JP S63119288A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- chip
- resin film
- semiconductor chip
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えばＩＣカード等に用いられる回路基板
に関し、特にその薄肉化手段に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit board used, for example, in an IC card, and particularly to a means for thinning the circuit board.
Ｃ従来の技術〕
ＩＣ，ＬＳＩ等の半導体チップを基板上に実装する手段
として、これまでのワイヤーボンディング法の他に、最
近では回路全体の厚みを薄クシたりあるいは量産性を高
めるために、フィルムキャリヤ方式（テープキャリヤ方
式、ＴＡＢとも言う）が開発されている。C. Prior Art] In addition to the traditional wire bonding method, film bonding has recently been used as a means of mounting semiconductor chips such as ICs and LSIs on substrates in order to reduce the overall thickness of the circuit or to improve mass production. A carrier method (also called tape carrier method, TAB) has been developed.
そのような方式による回路基板の一例を第２図に示す。An example of a circuit board using such a system is shown in FIG.
即ちこの回路基板は、表面に配線パターン６が形成され
たポリイミドフィルム等の樹脂フィルム４の六８内にＩ
Ｃ，ＬＳＩ等の半導体チップ１０を収納してそれと配線
パターン６間をＣｕリード１４で電気的に接続したもの
を、プリント基板等の基板２上に実装して成る。１２は
、半導体チップ１０接続用のＡｕバンプである。That is, this circuit board has I in 68 of a resin film 4 such as a polyimide film on which a wiring pattern 6 is formed.
A semiconductor chip 10 such as C, LSI, etc. is housed, and a wiring pattern 6 is electrically connected to the semiconductor chip 10 by a Cu lead 14, which is mounted on a substrate 2 such as a printed circuit board. 12 is an Au bump for connecting the semiconductor chip 10.
ところが従来の上記のような回路基板においては、半導
体チップ１０の周辺のコンデンサ、抵抗器、バリスタ、
ダイオード等のチップ部品１６については、図示例のよ
うに樹脂フィルム４上に別付けされており、これが当該
回路基板全体の薄肉化を妨げていた。However, in the conventional circuit board as described above, capacitors, resistors, varistors,
Chip components 16 such as diodes are attached separately on the resin film 4 as shown in the illustrated example, which prevents the overall thickness of the circuit board from being made thinner.
そこでこの発明は、そのような点を改善して一層の薄肉
化を図ることができる回路基板を提供することを目的と
する。Therefore, an object of the present invention is to provide a circuit board that can improve the above-mentioned points and achieve further thinning.
この発明の回路基板は、表面に配線パターンが形成され
た樹脂フィルムの穴内に半導体チップおよびそれとは別
のチップ部品を収納して半導体チップおよびチップ部品
と配線パターン間を電気的に接続したものを基板上に実
装して成ることを特徴とする。The circuit board of the present invention stores a semiconductor chip and another chip component in a hole in a resin film having a wiring pattern formed on its surface, and electrically connects the semiconductor chip, chip component, and wiring pattern. It is characterized by being mounted on a board.
半導体チップと同様にチップ部品をも樹脂フィルム内に
収納しているので、回路基板全体の厚みを一層薄くする
ことができる。Since the chip components are housed within the resin film in the same way as the semiconductor chips, the overall thickness of the circuit board can be made even thinner.
第１図は、この発明の一実施例に係る回路基板を示す概
略断面図である。第２図と同等部分には同一符号を付し
、ここでは従来例との相違点を主に説明する。FIG. 1 is a schematic cross-sectional view showing a circuit board according to an embodiment of the present invention. Components equivalent to those in FIG. 2 are given the same reference numerals, and differences from the conventional example will be mainly explained here.
即ちこの実施例の回路基板は、前述したような樹脂フィ
ルム４に半導体チップ１０収納用の穴８ａとは別に幾つ
かのチップ部品１６収納用の穴８ｂを設け、それぞれの
穴８ａ、８ｂにＩＣ，、ＬＳＩ等の半導体チップ１０お
よびコンデンサ、抵抗器、バリスタ、ダイオード等のチ
ップ部品１６を収納してそれらと配線パターン１６間を
例えばＣｕリード１４で電気的に接続したものを基板ｚ
上に実装して成る。１８はチップ部品１６接続用の半田
バンプである。That is, in the circuit board of this embodiment, in addition to the holes 8a for accommodating semiconductor chips 10, holes 8b for accommodating several chip components 16 are provided in the resin film 4 as described above, and ICs are placed in each of the holes 8a, 8b. ,, A substrate z includes a semiconductor chip 10 such as an LSI and chip components 16 such as capacitors, resistors, varistors, diodes, etc., and electrically connects them and wiring patterns 16 with, for example, Cu leads 14.
It is implemented on top. 18 is a solder bump for connecting the chip component 16.
その場合、チップ部品１６は例えば、半導体チップ１０
をボンディングするのと同時に、またはその前後にボン
ディングすることによって樹脂フィルム４内に埋め込む
ことができる。またチップ部品１６の種類、数量、配線
の仕方等は、所望とする回路構成に応じて適宜選定され
る。In that case, the chip component 16 is, for example, a semiconductor chip 10.
It can be embedded in the resin film 4 by bonding at the same time as, or before and after bonding. Further, the type, quantity, wiring method, etc. of the chip components 16 are appropriately selected depending on the desired circuit configuration.
上記回路基板においては、従来のようにチップ部品１６
を上部に別付けするのと違って、半導体チップ１０と同
様にチップ部品１６をも樹脂フィルム４内に埋め込んで
いるので、回路基板全体の厚みを一層薄くすることがで
きる。In the above circuit board, the chip component 16 is
Since the chip component 16 is also embedded in the resin film 4 in the same way as the semiconductor chip 10, the thickness of the entire circuit board can be made even thinner.
従って上記回路基板は、例えばＩＣカード等のように極
めて薄肉でしかも高実装密度が要求されるものに好適で
ある。尚、ＩＣカードに使用する場合は、必要に応じて
例えば、当該回路基板の上部側（図において上側）には
封止材およびオーバーシートが設けられ、基板２の下面
側には接触電極パターンおよびそれに対応する位置に穴
を有するオーバーシートが設けられる。Therefore, the above-mentioned circuit board is suitable for devices that are extremely thin and require high packaging density, such as IC cards. When used in an IC card, for example, a sealing material and an oversheet are provided on the upper side of the circuit board (upper side in the figure), and a contact electrode pattern and an oversheet are provided on the lower side of the circuit board 2 as necessary. An oversheet is provided with holes in corresponding positions.
１ 以上のようにこの発明によれば、半導体チップと同
様にチップ部品をも樹脂フィルム内に埋め込んでいるの
で、回路基板の一層の薄肉化を図ることができる。1 As described above, according to the present invention, since the chip components are also embedded in the resin film in the same way as the semiconductor chips, it is possible to further reduce the thickness of the circuit board.
第１図は、この発明の一実施例に係る回路基板を示す概
略断面図である。第２図は、従来の回路基板の一例を示
す概略断面図である。
２・・・基板、４・・・樹脂フィルム、６・・・配線パ
ターン、８ａ、８ｂ・・・穴、１０・・・半導体チップ
・ １６・・・チ・ノブ部品。FIG. 1 is a schematic cross-sectional view showing a circuit board according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing an example of a conventional circuit board. 2... Board, 4... Resin film, 6... Wiring pattern, 8a, 8b... Hole, 10... Semiconductor chip, 16... Chi/knob parts.
Claims (1)
穴内に半導体チップおよびそれとは別のチップ部品を収
納して半導体チップおよびチップ部品と配線パターン間
を電気的に接続したものを基板上に実装して成ることを
特徴とする回路基板。(1) A semiconductor chip and other chip components are housed in holes in a resin film with a wiring pattern formed on its surface, and the semiconductor chip, chip components, and wiring pattern are electrically connected and mounted on a board. A circuit board characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265078A JPS63119288A (en) | 1986-11-06 | 1986-11-06 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265078A JPS63119288A (en) | 1986-11-06 | 1986-11-06 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63119288A true JPS63119288A (en) | 1988-05-23 |
Family
ID=17412290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61265078A Pending JPS63119288A (en) | 1986-11-06 | 1986-11-06 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119288A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236476U (en) * | 1988-08-31 | 1990-03-09 | ||
| JPH07321438A (en) * | 1995-04-10 | 1995-12-08 | Sony Corp | Printed-circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197797A (en) * | 1982-05-13 | 1983-11-17 | 株式会社東芝 | Method of forming multilayer wirings |
-
1986
- 1986-11-06 JP JP61265078A patent/JPS63119288A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197797A (en) * | 1982-05-13 | 1983-11-17 | 株式会社東芝 | Method of forming multilayer wirings |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236476U (en) * | 1988-08-31 | 1990-03-09 | ||
| JPH07321438A (en) * | 1995-04-10 | 1995-12-08 | Sony Corp | Printed-circuit board |
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