JPS6290017A - Digital roll-off filter - Google Patents

Digital roll-off filter

Info

Publication number
JPS6290017A
JPS6290017A JP22868085A JP22868085A JPS6290017A JP S6290017 A JPS6290017 A JP S6290017A JP 22868085 A JP22868085 A JP 22868085A JP 22868085 A JP22868085 A JP 22868085A JP S6290017 A JPS6290017 A JP S6290017A
Authority
JP
Japan
Prior art keywords
filter
digital
delay
roll
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22868085A
Other languages
Japanese (ja)
Inventor
Tatsuya Kameyama
達也 亀山
Hiroshi Takatori
鷹取 洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22868085A priority Critical patent/JPS6290017A/en
Publication of JPS6290017A publication Critical patent/JPS6290017A/en
Pending legal-status Critical Current

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  • Filters And Equalizers (AREA)

Abstract

PURPOSE:To attain sufficient attenuation to harmonic components by constituting the titled filter with the combination of a delay element and an adder so as to simplify the circuit. CONSTITUTION:A transmission signal in a basic frequency fS is sampled at a frequency NfS by an A/D converter 2 to form a digital X1. The signals X1 are connected serially and fed to a digital roll-off filter comprising filters 3 5. The filter 3 adds an input signal to a delay element 6-1 (delay time 1/NfS) by an adder 7-1. The filter 4 is series connection of seven delay elements (delay time T2=1/MfS), the signal of each input/output terminal is added by an adder 7-2 and its output is connected serially to a circuit comprising the delay element and an adder 7-3. In equation, an integral number M is oneover an integral number of N. The filter 5 is three delay elements serial (delay time T3=1/fS), and the input/output signal of each element is added by an adder 7-4. Thus, the filter has a characteristic being the overall digital filter characteristics of plural stages connected in series, the roll-off characteristic is realized in a frequency 2fN or below and the characteristic is a prescribed value Sth or below at a broad band of frequency band 2fN-NfS.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はディジタルロールオフフィルタ、更に詳しく言
えば、ディジタル信号の伝送において波〔従来技術およ
び従来技術の問題〕 ロールオフフィルタは、信号の高域成分を除き、特にパ
ルス信号を処理する場合、符号量干渉を除くため、ディ
ジタル伝送用波形等化器等に使用さヤパシタを用いたも
のが知られている(昭和58年度電子通信学会総合全国
大会、539[スイツチドキャパシタを用いた5等化器
LSIの試作」銘木、鷹取他)。しかし、伝送信号の周
波数が高い場合、スイッチドキャパシタ回路で実現する
場合、十分な精度が得られない。又上記スイッチドキャ
パシタ回路の原理に基づく、ロールオフフィルタの伝達
関数を演算処理によるデイジタルフイルタで実現するこ
とが考えられるが、乗算器等を必要とし、回路が高価な
ものとなる。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital roll-off filter, and more particularly, to a digital roll-off filter, which uses waves in the transmission of digital signals [prior art and problems of the prior art]. In order to eliminate code amount interference, especially when processing pulse signals in addition to frequency components, it is known to use Yapacita, which is used in waveform equalizers for digital transmission. Conference, 539 [Prototype of 5-equalizer LSI using switched capacitors] Meiki, Takatori et al.). However, when the frequency of the transmission signal is high, sufficient accuracy cannot be obtained when implemented with a switched capacitor circuit. Furthermore, it is conceivable to realize the transfer function of a roll-off filter based on the principle of the switched capacitor circuit described above using a digital filter through arithmetic processing, but this requires a multiplier and the like, making the circuit expensive.

又後で説明するように、簡単な回路としてコサインロー
ルオフ特性を遅延素子と加算器の組合せによって実現す
ることができるが、この回路では高調波成分を除くこと
ができないため、ロールオフフィルタの入力側に高次の
アナログローパスフィルタを置かなければならいため、
ロールオフフィルタを簡単な回路で実現した効果が相殺
されてしまう。
As will be explained later, the cosine roll-off characteristic can be realized as a simple circuit by combining a delay element and an adder, but since this circuit cannot remove harmonic components, the input of the roll-off filter Because it is necessary to place a high-order analog low-pass filter on the side,
The effect of realizing the roll-off filter with a simple circuit is canceled out.

〔問題を解決するための手段〕[Means to solve the problem]

従って、本発明の目的は、遅延素子と加算器の組合せで
構成して回路を簡単とすると同時に、高調波成分に対し
て十分な減衰を与える機能を有するディジタルロールオ
フフィルタを実現することである。
Therefore, an object of the present invention is to realize a digital roll-off filter that is configured by a combination of delay elements and adders to simplify the circuit and at the same time has the function of providing sufficient attenuation to harmonic components. .

上記目的を達成するため、濾波されるディジタル伝送信
号をその伝送速度の整数倍の周波数の標本化周波数で標
本化してディジタル信号とし、遅延素子と加算器で構成
されるディジタルフィルタを複数段直ダ1月妾続すると
共に、かつ、伝送信号のティキス1−周波数と上記標本
化周波数との間で多くの零点を持つように、上記複数段
のディジタルフィルタの特性を持つように構成した。
In order to achieve the above purpose, the digital transmission signal to be filtered is sampled at a sampling frequency that is an integer multiple of the transmission speed, and is converted into a digital signal. It was configured to have the characteristics of the multi-stage digital filter, so as to have many zero points between the Tiki frequency of the transmission signal and the sampling frequency.

〔実施例〕〔Example〕

以下実施例によって本発明の詳細な説明する。 The present invention will be explained in detail below with reference to Examples.

第1図は本発明によるディジタルロールオフフィルタの
一実施例の構成を示す図である。
FIG. 1 is a diagram showing the configuration of an embodiment of a digital roll-off filter according to the present invention.

入力端子1にはフィルタリングされるアナログ信号、す
なわち、ディジタル信号のパルスがアナログ信号として
加えられる。このパルスの基本周期をTS(周波数又は
伝送速度fs=−と表わす)s とする。この伝送信号は、A/D変換器2で標本化周波
数Nfsで標本化されディジタル信号X1となる。ディ
ジタル信号XIは、直列接続された複数段のディジタル
フィルタ3,4および5からなるディジタルロールオフ
フィルタに加えられる。
An analog signal to be filtered, that is, a pulse of a digital signal is applied to the input terminal 1 as an analog signal. Let the basic period of this pulse be TS (expressed as frequency or transmission speed fs=-). This transmission signal is sampled at the sampling frequency Nfs by the A/D converter 2 and becomes a digital signal X1. Digital signal XI is applied to a digital roll-off filter consisting of multiple stages of digital filters 3, 4 and 5 connected in series.

最初の段のディジタルフィルタ3は、単一の遅延素子6
−1 (遅延時間□)の入力端子の信号Fs を加算器7−1で加算する構成となる。従って、ディジ
タルフィルタの伝達関数をZ関数で表わすと、 (1+Z−1)/2           ・・・(1
)で表わされる。
The first stage digital filter 3 consists of a single delay element 6
-1 (delay time □) input terminal signals Fs are added by an adder 7-1. Therefore, if the transfer function of a digital filter is expressed as a Z function, (1+Z-1)/2...(1
).

又次段のディジタルフィルタ4は遅延素子(遅延時間T
 2 = −)を7個(6−2,6−3・・fs 6−8)直列接続し、各入出力端子の信号を加算器7−
2で加算し、その出力を同様の構成の遅延素子6−9〜
6−15と加算器7−3で構成された回路とに直列接続
している。ここで整数MはNの整数分の−である。従っ
てディジタルフィルタ4の伝達関数は (1+Z 1+Z ”+Z−”+Z−’+Z−6+Z−
6)”/64・・・(2)となる。
Further, the next stage digital filter 4 is a delay element (delay time T
2 = -) are connected in series (6-2, 6-3...fs 6-8), and the signals of each input and output terminal are sent to an adder 7-
2 and the output is added to delay elements 6-9 to 6-9 with similar configurations.
6-15 and a circuit constituted by an adder 7-3. Here, the integer M is an integer of N. Therefore, the transfer function of the digital filter 4 is (1+Z 1+Z "+Z-"+Z-'+Z-6+Z-
6)”/64...(2).

最終段のディジタルフィルタ5は遅延素子(遅延時間T
 a = −)を3個直列接続(6−16゜S 6−17.6−18)t、、各素子の入出力信号を加算
器7−4加算する構成となっている。従って、このディ
ジタルフィルタ5の伝達関数は(L+Z−1+Z”+Z
−3)/4     ・・(3)となる。
The final stage digital filter 5 is a delay element (delay time T
a = -) are connected in series (6-16°S 6-17, 6-18)t, and the input and output signals of each element are added by an adder 7-4. Therefore, the transfer function of this digital filter 5 is (L+Z-1+Z''+Z
-3)/4...(3).

これらの遅延素子はクロック端子はD型フリップフロッ
プ回路で構成される。
The clock terminals of these delay elements are constituted by D-type flip-flop circuits.

〔発明の効果〕〔Effect of the invention〕

伝送速度(基本周波数)fNの伝送信号に対し、理相的
ロールオフ特性である第2図に示すようなフルコサイン
ロールオフフィルタ特性 を実現するためには高次のアナログフィルタを必要とす
る。
In order to realize a full cosine roll-off filter characteristic as shown in FIG. 2, which is a logical roll-off characteristic, for a transmission signal having a transmission rate (fundamental frequency) fN, a high-order analog filter is required.

これをディジタル回路で実現する場合、第3図のように
、遅延素子6(遅延時間T=−)の入N 出力を加算器7で加算する簡単なディジタルフィルタを
2段接続することによって、伝達関数が実際される。し
かし、このフィルタ特性は第4図に示す如く、周波数2
f〜以下は第2図のフルコサインロールオフ特性と一致
するが、サンプリング周波数の整数倍の成分も通過帯域
とする(すなわち折り返し周波数成分が生じる。)従っ
て、第3図のようなディジタルフィルタをロールオフフ
ィルタとして使用する場合には、高周波数成分を除くた
めに、フィルタの前段に高次のアナログローパスフィル
タが必要となる。すなわち周波数2fN近傍において急
岐な立下り特性を持つアナログフィルタを用いらなけれ
ばならないが、そのい。これに対し、本発明のディジタ
ルロールオフフィルタは、例えば、第5図に示すように
、直列接続された複数段のディジタルフィルタの特性を
総合したものとなり5周波数2f〜以下ではロールオフ
特性を実現でき1周波数イIF域2fN NFsの広帯
域では、一定値S+、h以下となり、実際上の遮断が実
現できる。従って、ロールオフフィルタの前段におかれ
るアナログローパスフィルタ1次か2次の簡単なアナロ
グフィルタで実現でき、折り返し成分NFs を容易に
除くことができる。
When realizing this with a digital circuit, as shown in FIG. The function is actually performed. However, as shown in Fig. 4, this filter characteristic is
f~ and below corresponds to the full cosine roll-off characteristic shown in Figure 2, but components that are integral multiples of the sampling frequency are also included in the passband (that is, aliased frequency components occur). Therefore, the digital filter shown in Figure 3 is When used as a roll-off filter, a high-order analog low-pass filter is required before the filter in order to remove high frequency components. That is, it is necessary to use an analog filter that has a sharp falling characteristic near the frequency 2fN, but this is not possible. On the other hand, the digital roll-off filter of the present invention, for example, as shown in FIG. In the wide band of 1 frequency IF range 2fN NFs, the value is less than the constant value S+,h, and practical cutoff can be realized. Therefore, it can be realized by a simple analog filter such as a first-order or second-order analog low-pass filter placed before the roll-off filter, and the aliasing component NFs can be easily removed.

なお、遅延素子の遅延時間を、各段のディジタルフィル
タによって異ならせること、又入力信号の標本化周波数
を高くしていることは欠点のように考えられるが、実際
には、他の回路、例えばコーダ、デコーダと一緒にLS
I化されるが、そのような場合、オーバーサンプル形の
コーダ、デコーダ′には高い周波数の標本化、クロック
信号回路が使用されるので、これらの回路を共用するこ
とによって、回路楕成上の経済性、小形化の間層となる
ことはない。
Although it may seem like a drawback that the delay time of the delay element is different depending on the digital filter in each stage, and that the sampling frequency of the input signal is increased, in reality, it is difficult to use other circuits, e.g. LS with coder and decoder
However, in such a case, high frequency sampling and clock signal circuits are used for the oversampled coder and decoder', so by sharing these circuits, circuit ellipse There is no gap between economy and miniaturization.

上述の如く、本発明によれば、乗算器を用いることなく
、しかも、高周波成分を有効に除き、実際の使用におい
て、ロールオフフィルタの前におくプレフィルタを簡易
な低次のフィルタで構成できるため、他の回路と一体的
にLSIに組込むことが容易となると共に、低消費電力
、チップのLSI小形化に有効な手段となる。
As described above, according to the present invention, high frequency components can be effectively removed without using a multiplier, and in actual use, the pre-filter placed before the roll-off filter can be configured with a simple low-order filter. Therefore, it is easy to integrate it into an LSI with other circuits, and it is an effective means for reducing power consumption and downsizing the LSI chip.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるディジタルロールオフフィルタの
一実施例の構成図、第2図はロールオフフィルタ特性図
、第3図は従来のディジタルロールオフフィルタの構成
図、第4図は第3図のロールオフフィルタの特性図、第
5図は本発明によるディジタルロールオフフィルタの特
性図である。 2・・・A/D変換器、3,4.5・・ディジタルフィ
ルタ、6・・・遅延素子、7・・・加算器。
Fig. 1 is a block diagram of an embodiment of a digital roll-off filter according to the present invention, Fig. 2 is a roll-off filter characteristic diagram, Fig. 3 is a block diagram of a conventional digital roll-off filter, and Fig. 4 is a block diagram of a conventional digital roll-off filter. FIG. 5 is a characteristic diagram of a digital roll-off filter according to the present invention. 2... A/D converter, 3, 4.5... Digital filter, 6... Delay element, 7... Adder.

Claims (1)

【特許請求の範囲】 1、デイジタル伝送における伝送信号の伝送速度の2以
上の整数倍でA/D変換されたデイジタル信号を入力信
号とし、1ないし複数個の縦続接続された遅延素子と、
その遅延素子の入出力を加算する加算器とからなるデイ
ジタルフイルタを複数段直列接続して構成され、上記複
数段のデイジタルフイルタの遅延素子の遅延時間を、初
段が最も短かく、後段になるに従つて初段遅延時間の整
数倍に設定されて構成されたことを特徴とするデイジタ
ルロールオフフイルタ。 2、第1項記載のデイジタルロールオフフイルタにおい
て、初段のデイジタルフイルタの遅延素子の遅延時間は
上記A/D変換される標本化周期に等しく、最終段のデ
イジタルフイルタの遅延素子の遅延時間が上記伝送信号
の基本周期に等しく設定されたデイジタルロールオフフ
イルタ。
[Scope of Claims] 1. A digital signal that has been A/D converted at an integral multiple of 2 or more of the transmission speed of a transmission signal in digital transmission is used as an input signal, and one or more cascade-connected delay elements;
It is constructed by connecting multiple stages of digital filters in series, each consisting of an adder that adds the input and output of the delay elements, and the delay time of the delay elements of the multiple stages of digital filters is the shortest in the first stage, and the delay time in the later stages is the shortest. Therefore, a digital roll-off filter is characterized in that it is configured to be set to an integral multiple of the initial stage delay time. 2. In the digital roll-off filter described in item 1, the delay time of the delay element of the first-stage digital filter is equal to the sampling period for A/D conversion, and the delay time of the delay element of the final-stage digital filter is equal to the above-mentioned sampling period. A digital roll-off filter set equal to the fundamental period of the transmitted signal.
JP22868085A 1985-10-16 1985-10-16 Digital roll-off filter Pending JPS6290017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22868085A JPS6290017A (en) 1985-10-16 1985-10-16 Digital roll-off filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22868085A JPS6290017A (en) 1985-10-16 1985-10-16 Digital roll-off filter

Publications (1)

Publication Number Publication Date
JPS6290017A true JPS6290017A (en) 1987-04-24

Family

ID=16880128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22868085A Pending JPS6290017A (en) 1985-10-16 1985-10-16 Digital roll-off filter

Country Status (1)

Country Link
JP (1) JPS6290017A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5007757A (en) * 1988-09-02 1991-04-16 Yoshino Kogyosho Co., Ltd. Liquid container
JPH04367113A (en) * 1991-06-14 1992-12-18 Matsushita Electric Ind Co Ltd Roll off filtering device
WO2004079905A1 (en) * 2003-03-03 2004-09-16 Neuro Solution Corp. Digital filter design method and device, digital filter design program, digital filter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5180245A (en) * 1988-06-02 1993-01-19 Yoshino Kogyosho Co., Ltd. Liquid container with specific valve
US5007757A (en) * 1988-09-02 1991-04-16 Yoshino Kogyosho Co., Ltd. Liquid container
US5251992A (en) * 1988-09-02 1993-10-12 Yoshino Kogyosho Co., Ltd. Liquid container with variable shaped tip
JPH04367113A (en) * 1991-06-14 1992-12-18 Matsushita Electric Ind Co Ltd Roll off filtering device
WO2004079905A1 (en) * 2003-03-03 2004-09-16 Neuro Solution Corp. Digital filter design method and device, digital filter design program, digital filter
JPWO2004079905A1 (en) * 2003-03-03 2006-06-08 有限会社ニューロソリューション Digital filter design method and apparatus, digital filter design program, and digital filter

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