JPS6286333A - Bias voltage generating circuit for liquid crystal driving device - Google Patents

Bias voltage generating circuit for liquid crystal driving device

Info

Publication number
JPS6286333A
JPS6286333A JP22629285A JP22629285A JPS6286333A JP S6286333 A JPS6286333 A JP S6286333A JP 22629285 A JP22629285 A JP 22629285A JP 22629285 A JP22629285 A JP 22629285A JP S6286333 A JPS6286333 A JP S6286333A
Authority
JP
Japan
Prior art keywords
liquid crystal
signal
crystal driving
voltages
bias voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22629285A
Other languages
Japanese (ja)
Inventor
Minoru Usui
臼井 実
Saburo Kobayashi
三朗 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP22629285A priority Critical patent/JPS6286333A/en
Publication of JPS6286333A publication Critical patent/JPS6286333A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To prevent picture quality from deterioration due to stringiness by variably controlling the reference voltage of a scanning electrode signal. CONSTITUTION:A liquid crystal driving voltage consisting of a fixed voltage Vb is impressed between both the terminals of a serial circuit. Reference driving voltages V0, V5 from both the terminals of the serial circuit, voltages V2, V3 from respective nodes between a variable resistor VR13 and a resistor R12 and between the resistor R12 and a variable resistor VR11 and voltages V1, V4 from respective needles of the variable resistors VR13, VR11 are respectively extracted. The reference voltages V1, V4 are constituted so as to be variably adjusted by the variable resistors VR11, VR13.

Description

【発明の詳細な説明】 [発明の技術分野] この発明は、マトリクス形液晶表示素子を電源平均化方
式により駆動する液晶装置のバイアス電圧発生回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bias voltage generation circuit for a liquid crystal device that drives a matrix type liquid crystal display element using a power supply averaging method.

[従来技術とその問題点コ 液晶テレビジョン受像機等に使用される液晶表示装置(
LCD)において、表示部に「nxmJのマトリクス表
示を行なう場合、n本の走査電極とm本の信号電極に対
して、それぞれ第3図(a)に示すような走査電極信号
および(b)に示すような信号電極信号が必要とされて
いる。そして、上記走査電極信号および信号電極信号は
、例えば第4図または第5図に示すような電圧平均化方
式のバイアス電圧発生回路によって作成されている。
[Prior art and its problems] Liquid crystal display devices used in liquid crystal television receivers, etc.
LCD), when performing a matrix display of nxmJ on the display section, the scanning electrode signals as shown in Fig. 3(a) and the scanning electrode signals as shown in Fig. 3(b) are displayed for n scanning electrodes and m signal electrodes, respectively. Signal electrode signals such as those shown in FIG. There is.

第4図は、基準液晶駆動電圧vO〜v5を作成する回路
である。第4図において、Vaは液晶駆動電源で、この
電源Vaは、直列接続されたR1−R5の両端に印加さ
れている。なお、上記抵抗R3の係数mは、液晶表示の
デユーティを1/Nとすると、 m−=’N+1 が一番有利で通常、この値が用いられる。このようにし
て、上記電源vaが分圧されて基準液晶駆動電圧VO−
V5が作成される。この電圧VO〜V5は走査電極駆動
回路(図示せず)、信号電極駆動回路(図示せず)に送
られている。そして、上記走査電極駆動回路は上記電圧
VO,V1゜V4.V5の電圧を選択して、LCDに第
3図(a)に示すような走査電極駆動信号を出力してい
る。また、上記信号電極駆動回路は上記電圧VO,V2
.V3.V5の電圧を選択し、第3図(b)に示すよう
な信号電極駆動信号をLCDに出力する。
FIG. 4 shows a circuit for creating reference liquid crystal drive voltages vO to v5. In FIG. 4, Va is a liquid crystal driving power supply, and this power supply Va is applied to both ends of R1 to R5 connected in series. Note that the coefficient m of the resistor R3 is most advantageously m-='N+1, assuming that the duty of the liquid crystal display is 1/N, and this value is usually used. In this way, the power supply va is divided into the reference liquid crystal drive voltage VO-
V5 is created. These voltages VO to V5 are sent to a scan electrode drive circuit (not shown) and a signal electrode drive circuit (not shown). The scan electrode drive circuit operates at the voltages VO, V1°V4. The voltage V5 is selected and a scanning electrode drive signal as shown in FIG. 3(a) is output to the LCD. Further, the signal electrode drive circuit operates at the voltages VO and V2.
.. V3. The voltage V5 is selected and a signal electrode drive signal as shown in FIG. 3(b) is output to the LCD.

また、第4図に示したような分圧回路の各出力端に、第
5図に示すようにバッファ回路10a、10b、10c
・・・をそれぞれ設けて構成することも行われている。
Further, buffer circuits 10a, 10b, 10c as shown in FIG. 5 are connected to each output terminal of the voltage dividing circuit as shown in FIG.
. . . are also provided and configured.

このようにして、上記第4図または第5図のようなバイ
アス電圧発生回路で、走査電極信号および信号電極信号
を作成し、液晶表示素子の走査電極および信号電極に印
加する。ここで、上記液晶表示素子は、第6図に示すよ
うな等何回路で表わせる。すなわち液晶表示素子は、ネ
サ抵抗等の配線抵抗r1ど抵抗r2との間に、並列に接
続されたコンデンサCおよび抵抗r3が接続された構成
になっている。なお、上記抵抗r3は、その抵抗値が大
きいので無視できるものである。このようにして、液晶
表示素子は、コンデンサCと等価になるため、その容量
性のため、第7図(a)。
In this way, a scanning electrode signal and a signal electrode signal are generated by the bias voltage generating circuit shown in FIG. 4 or 5, and applied to the scanning electrode and signal electrode of the liquid crystal display element. Here, the liquid crystal display element can be represented by any number of circuits as shown in FIG. That is, the liquid crystal display element has a configuration in which a capacitor C and a resistor r3 are connected in parallel between wiring resistors r1 and r2 such as Nesa resistors. Note that the resistance r3 can be ignored since its resistance value is large. In this way, the liquid crystal display element becomes equivalent to a capacitor C, due to its capacitive nature, as shown in FIG. 7(a).

(b)、(C)に示すように、信号電極信号Yの立ち上
がり時と、立ち下がり時に、走査電極信号Xに微分波形
があられれるような影響を与えてしまう。そして、この
微分波形は出力インピーダンス等の関係から、その正お
よび負方向で異なっている。このため、信号電極信号Y
と走査電極信号Xを合成した(C)図に示す液晶印加電
圧信号Y−Xが、直流的に「0」を中心にして見た場合
、その立ち上がり特性と立ち下がり特性に差が存在する
ようなアンバランスを生じてしまう。そして、このDC
アンバランスは糸引き等のクロストークを引き起こすも
のである。
As shown in (b) and (C), when the signal electrode signal Y rises and falls, the scan electrode signal X is affected by a differential waveform. This differential waveform differs in its positive and negative directions due to the relationship of output impedance and the like. Therefore, the signal electrode signal Y
When the liquid crystal applied voltage signal Y-X shown in figure (C), which is a composite of the and scanning electrode signals This creates an imbalance. And this DC
Imbalance causes crosstalk such as stringiness.

[発明の目的] この発明は、上記のような点に鑑みなされたもので、走
査電極信号の歪みから生じる液晶印加電圧信号のDCア
ンバランスを改善し、マトリックス形液晶表示素子を駆
動した際の糸引き等の画像劣化を防止することができる
液晶駆動装置のバイアス電圧発生回路を提供しようとす
るものである。
[Object of the Invention] The present invention has been made in view of the above points, and improves the DC imbalance of the liquid crystal applied voltage signal caused by the distortion of the scanning electrode signal, and improves the DC imbalance when driving a matrix type liquid crystal display element. The present invention aims to provide a bias voltage generation circuit for a liquid crystal drive device that can prevent image deterioration such as stringiness.

[発明の要点] すなわち、この発明に係わる液晶駆動装置のバイアス電
圧発生回路にあっては、液晶駆動電源が印加される直列
接続された複数の抵抗のうち、基準となる走査電極信号
を発生させる抵抗を可変できるように構成する。そして
、この抵抗器によってバイアス比を可変させ、液晶表示
装置に印加される印加実効電圧信号を変化させることに
より、印加実効電圧信号のDCアンバランスを改善し、
糸引きによる画像劣化を防止する。
[Summary of the Invention] That is, in the bias voltage generation circuit for a liquid crystal driving device according to the present invention, a scan electrode signal serving as a reference is generated from among a plurality of series-connected resistors to which liquid crystal driving power is applied. Configure so that the resistance can be varied. Then, by varying the bias ratio using this resistor and changing the applied effective voltage signal applied to the liquid crystal display device, the DC imbalance of the applied effective voltage signal is improved.
Prevents image deterioration due to stringiness.

[発明の実施例コ 以下図面を参照して、この発明の一実施例を説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

第1図は、基準液晶駆動電圧■0〜v5を作成するバイ
アス電圧発生回路を示している。
FIG. 1 shows a bias voltage generation circuit that generates reference liquid crystal drive voltages 0 to v5.

このバイアス電圧発生回路は、可変抵抗VR11、抵抗
R12および可変抵抗V R13が直列に接続して構成
されている。そして、この直列回路の両端間に一定の電
圧vbでなる液晶駆動電圧を印加設定する。そして、こ
の直列回路の両端から基準駆動電圧VOおよびv5、ま
た可変抵抗V R13と抵抗R12,抵抗R12と可変
抵抗VR11のそれぞれ接続点からV2およびV3、可
変抵抗V R13およびVRllのそれぞれ可動子から
■1およびv4を取り出すようにする。そして、上記基
準電圧V1および■4は、上記可変抵抗VR11および
V R13によって可変調整できるように構成されてい
る。ここで、上記可変抵抗V R11およびV R13
の各々の抵抗値を2Rとすると抵抗R12の抵抗値は、
1/Nをデユーティ比とするとmRとなる。
This bias voltage generation circuit is constructed by connecting a variable resistor VR11, a resistor R12, and a variable resistor VR13 in series. Then, a liquid crystal drive voltage of a constant voltage vb is applied and set across both ends of this series circuit. Then, reference drive voltages VO and v5 are applied from both ends of this series circuit, V2 and V3 are applied from the respective connection points of variable resistor V R13 and resistor R12, resistor R12 and variable resistor VR11, and variable resistors V R13 and VRll are applied from the movable element. ■Make sure to take out 1 and v4. The reference voltages V1 and 4 are configured to be variably adjusted by the variable resistors VR11 and VR13. Here, the variable resistors V R11 and V R13
Assuming that the resistance value of each of is 2R, the resistance value of resistor R12 is
If 1/N is the duty ratio, it becomes mR.

ここで m =JN+1 そして、上記電圧VO〜V5に基づき走査電極駆動回路
(図示せず)において電圧VO,V1゜V4.V5が選
択されて走査電極駆動回路が作成されると共に、信号電
極駆動回路(図示せず)において電圧VO,V2.V3
.V5が選択されて信号電極駆動信号が作成される。
Here, m = JN+1 Then, based on the voltages VO to V5, a scan electrode drive circuit (not shown) changes voltages VO, V1°V4. V5 is selected to create a scan electrode drive circuit, and voltages VO, V2 . V3
.. V5 is selected and a signal electrode drive signal is created.

ここで、前記第7図に示したように、走査電極信号Xは
、信号電極信号Yの立ち上がり時と、立−〇− ち下がり時に影響を受ける。そして、この影響は信号電
極信号Yの立ち上がり時と、立ち下がり時において異な
る。このため、上記信号電極信号Yと走査電極信号Xと
を合成した印加電圧信号Y−XがDCアンバランスにな
る。そこで、上記バイアス電圧発生回路では、上記可変
抵抗VR11およびVR13の抵抗値を可変させること
により、走査電極信号Xの基準電圧v1および■4のレ
ベルを平均値化したレベルに調整するようにしている。
Here, as shown in FIG. 7, the scanning electrode signal X is affected when the signal electrode signal Y rises and falls. This influence differs between when the signal electrode signal Y rises and when it falls. Therefore, the applied voltage signal Y-X, which is a combination of the signal electrode signal Y and the scanning electrode signal X, becomes DC unbalanced. Therefore, in the bias voltage generation circuit, the levels of the reference voltages v1 and 4 of the scanning electrode signal X are adjusted to the averaged level by varying the resistance values of the variable resistors VR11 and VR13. .

すなわち、例えば第7図(C)に示すような印加電圧信
号Y−Xに対しては、可変抵抗VR11によって走査電
極信号Xの基準電圧■1のレベルを適当に上げてやり、
また可変抵抗VR13によって基準電圧■4のレベルを
適当に下げてやる。このようにして、信号電極信号Yと
走査電極信号Xとを合成して形成される印加電圧信号1
−XのDCアンバランスを平均化し、糸引きによる画像
劣化を防ぐものである。
That is, for example, for the applied voltage signal Y-X as shown in FIG. 7(C), the level of the reference voltage 1 of the scanning electrode signal X is appropriately increased by the variable resistor VR11.
Further, the level of the reference voltage (4) is appropriately lowered by the variable resistor VR13. In this way, the applied voltage signal 1 is formed by combining the signal electrode signal Y and the scanning electrode signal X.
-X DC unbalance is averaged to prevent image deterioration due to stringiness.

また、上記第1図に示したバイアス電圧発生回路の各出
力端に、第2図に示すようなバッファ回路12a、12
b、12c・・・をそれぞれ設けて構成することもでき
、上記第1図のバイアス電圧発生回路と同様にして液晶
表示装置を駆動するものである。
Furthermore, buffer circuits 12a and 12 as shown in FIG. 2 are connected to each output terminal of the bias voltage generation circuit shown in FIG.
b, 12c, . . . may be provided, and the liquid crystal display device is driven in the same manner as the bias voltage generating circuit shown in FIG. 1 above.

[発明の効果] 以上のようにこの発明によれば、走査電極信号の基準電
圧を可変調節させることにより、液晶印加電圧信号のD
Cアンバランスを改善することができる。このため、糸
引きによる画像劣化を防止できるものである。
[Effects of the Invention] As described above, according to the present invention, by variably adjusting the reference voltage of the scanning electrode signal, the D of the liquid crystal applied voltage signal can be adjusted.
C imbalance can be improved. Therefore, image deterioration due to stringiness can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例に係わる液晶駆動装置のバ
イアス電圧発生回路を説明する図、第2図は上記第1図
のバイアス電圧発生回路にバッファ回路を設けた場合の
回路図、第3図(a)は走査電極信号を示す図、第3図
(b)は信号電極信号を示す図、第4図および第5図は
従来のバイアス電圧発生回路による電圧制御方式を説明
する図、第6図は液晶表示素子の等価回路図、第7図(
a)は電圧■0〜■2および■3〜■5の信号電極信号
を示す図、第7図(b)は上記信号電極信号に対する電
圧V1およびV4の走査電極信号を示す図、第7図(C
)は上記信号電極信号と走査電極信号によって得られる
液晶印加電圧信号を示す図である。 VO〜v5・・・基準電圧、R1−R5およびR12・
・・抵抗、VRllおよびV R13・・・可変抵抗、
ioa 。 10b、 10cおよび12a、 12b、 12cm
・・バッファ回路。 出願人代理人 弁理士 鈴江 武彦 □5−■5 /10b □□4メニ■2 Vり 第4図      第5図 第6図 (a) (b) (C) 第7図
FIG. 1 is a diagram explaining a bias voltage generation circuit of a liquid crystal driving device according to an embodiment of the present invention, FIG. 2 is a circuit diagram when a buffer circuit is provided in the bias voltage generation circuit of FIG. 1, and FIG. 3(a) is a diagram showing a scanning electrode signal, FIG. 3(b) is a diagram showing a signal electrode signal, FIGS. 4 and 5 are diagrams explaining a voltage control method using a conventional bias voltage generation circuit, Figure 6 is an equivalent circuit diagram of a liquid crystal display element, Figure 7 (
a) is a diagram showing signal electrode signals of voltages ■0 to ■2 and ■3 to ■5; FIG. 7(b) is a diagram showing scanning electrode signals of voltages V1 and V4 with respect to the signal electrode signals; FIG. (C
) is a diagram showing a liquid crystal applied voltage signal obtained by the signal electrode signal and scanning electrode signal. VO~v5...Reference voltage, R1-R5 and R12.
...Resistance, VRll and VR13...Variable resistance,
ioa. 10b, 10c and 12a, 12b, 12cm
...Buffer circuit. Applicant's agent Patent attorney Takehiko Suzue□5-■5 /10b □□4meni■2 Vri Figure 4 Figure 5 Figure 6 (a) (b) (C) Figure 7

Claims (1)

【特許請求の範囲】 液晶駆動電源から得られる電圧を分圧して複数の基準液
晶駆動電圧を形成している液晶駆動装置のバイアス電圧
発生回路において、 上記液晶駆動電源が印加される直列接続された複数の抵
抗のうち、走査電極信号の基準となる電圧を発生する抵
抗を可変用素子によって構成し、液晶表示素子に印加さ
れる印加実効電圧を変化させるようにしたことを特徴と
する液晶駆動装置のバイアス電圧発生回路。
[Claims] In a bias voltage generation circuit for a liquid crystal driving device which forms a plurality of reference liquid crystal driving voltages by dividing a voltage obtained from a liquid crystal driving power source, there is provided a bias voltage generating circuit for a liquid crystal driving device which divides a voltage obtained from a liquid crystal driving power source to form a plurality of reference liquid crystal driving voltages. A liquid crystal drive device characterized in that, among the plurality of resistors, a resistor that generates a reference voltage for a scanning electrode signal is configured by a variable element, so that an applied effective voltage applied to a liquid crystal display element is varied. Bias voltage generation circuit.
JP22629285A 1985-10-11 1985-10-11 Bias voltage generating circuit for liquid crystal driving device Pending JPS6286333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22629285A JPS6286333A (en) 1985-10-11 1985-10-11 Bias voltage generating circuit for liquid crystal driving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22629285A JPS6286333A (en) 1985-10-11 1985-10-11 Bias voltage generating circuit for liquid crystal driving device

Publications (1)

Publication Number Publication Date
JPS6286333A true JPS6286333A (en) 1987-04-20

Family

ID=16842922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22629285A Pending JPS6286333A (en) 1985-10-11 1985-10-11 Bias voltage generating circuit for liquid crystal driving device

Country Status (1)

Country Link
JP (1) JPS6286333A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302722A (en) * 1989-05-17 1990-12-14 Hitachi Ltd Liquid crystal display device
US5301047A (en) * 1989-05-17 1994-04-05 Hitachi, Ltd. Liquid crystal display
KR19990011353A (en) * 1997-07-23 1999-02-18 윤종용 Driving circuit of liquid crystal display device
KR20040021464A (en) * 2002-09-04 2004-03-10 엘지.필립스 엘시디 주식회사 Gamma voltage generating circuit and generating method of tft-lcd

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302722A (en) * 1989-05-17 1990-12-14 Hitachi Ltd Liquid crystal display device
US5301047A (en) * 1989-05-17 1994-04-05 Hitachi, Ltd. Liquid crystal display
KR19990011353A (en) * 1997-07-23 1999-02-18 윤종용 Driving circuit of liquid crystal display device
KR20040021464A (en) * 2002-09-04 2004-03-10 엘지.필립스 엘시디 주식회사 Gamma voltage generating circuit and generating method of tft-lcd

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