JP2003295842A - Display device and its driving method - Google Patents
Display device and its driving methodInfo
- Publication number
- JP2003295842A JP2003295842A JP2003024327A JP2003024327A JP2003295842A JP 2003295842 A JP2003295842 A JP 2003295842A JP 2003024327 A JP2003024327 A JP 2003024327A JP 2003024327 A JP2003024327 A JP 2003024327A JP 2003295842 A JP2003295842 A JP 2003295842A
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- voltage
- display device
- signal line
- generation circuit
- gradation
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- Liquid Crystal Display Device Control (AREA)
- Picture Signal Circuits (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、信号線に供給され
る信号線電圧に対してγ補正を行う表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which performs γ correction on a signal line voltage supplied to a signal line.
【０００２】[0002]
【従来の技術】一般に、液晶表示装置や有機ＥＬ表示装
置等の平面表示装置では、画素の輝度に応じた電圧を信
号線に供給して表示動作を行う。ところが、画面の明る
さは信号線電圧に正比例せず、信号線電圧に対して指数
関数的に変化する。例えば、一般の液晶表示装置にあっ
ては、信号線電圧が小さいときは明るさの変化が緩やか
で、信号線電圧が大きくなるほど明るさが急激に変化す
る。2. Description of the Related Art Generally, in a flat display device such as a liquid crystal display device or an organic EL display device, a voltage corresponding to the brightness of a pixel is supplied to a signal line to perform a display operation. However, the brightness of the screen is not directly proportional to the signal line voltage and changes exponentially with respect to the signal line voltage. For example, in a general liquid crystal display device, when the signal line voltage is small, the change in brightness is gradual, and as the signal line voltage increases, the brightness changes rapidly.
【０００３】個々の液晶表示装置は、固有のガンマ値を
持っているため、ガンマ値に合わせて明るさを調整する
ガンマ（γ）補正を行うのが一般的である。Since each liquid crystal display device has a unique gamma value, it is general to perform gamma (γ) correction for adjusting the brightness according to the gamma value.
【０００４】[0004]
【発明が解決しようとする課題】従来は、対向電極に供
給されるコモン電圧の振幅を調整することにより、γ補
正を行っていた。この方式では、その調整によっては、
ノーマリホワイト（電圧無印加時に最大輝度を表示する
モード）の場合、黒色が白っぽくなる等の不具合が生
じ、表示品質が劣化してしまう。Conventionally, γ correction has been performed by adjusting the amplitude of the common voltage supplied to the counter electrode. With this method, depending on the adjustment,
In the case of normally white (a mode in which the maximum brightness is displayed when no voltage is applied), a defect such as a blackish whitish occurs and display quality deteriorates.
【０００５】本発明は、このような点に鑑みてなされた
ものであり、その目的は、ガンマ補正を精度よく行える
表示装置を提供することにある。The present invention has been made in view of the above points, and an object thereof is to provide a display device capable of performing gamma correction with high accuracy.
【０００６】[0006]
【課題を解決するための手段】上述した課題を解決する
ために、本発明は、列設された信号線および走査線と、
前記信号線および走査線の交点付近に形成される表示画
素と、２種類の基準電圧を複数の抵抗素子で抵抗分圧し
て、前記信号線に供給される階調電圧を生成する階調電
圧生成回路と、前記複数の抵抗素子間の少なくとも一つ
の接続経路に印加されるγ補正用電圧を生成するγ補正
電圧生成回路と、前記階調電圧生成回路で生成された階
調電圧の中から、デジタル画素データに応じた階調電圧
を選択して対応する信号線に供給する信号線電圧生成回
路と、を備える。In order to solve the above-mentioned problems, the present invention provides a signal line and a scanning line arranged in a row,
A display pixel formed in the vicinity of the intersection of the signal line and the scanning line, and a gradation voltage generation for generating a gradation voltage to be supplied to the signal line by resistance-dividing two kinds of reference voltages with a plurality of resistance elements. A circuit, a γ correction voltage generation circuit that generates a γ correction voltage applied to at least one connection path between the plurality of resistance elements, and a gradation voltage generated by the gradation voltage generation circuit, And a signal line voltage generation circuit that selects a gradation voltage according to digital pixel data and supplies the selected gradation voltage to a corresponding signal line.
【０００７】[0007]
【発明の実施の形態】以下、本発明に係る表示装置につ
いて、図面を参照しながら具体的に説明する。図１は本
発明に係る表示装置の一実施形態の概略構成を示すブロ
ック図であり、液晶表示装置の構成を示している。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a display device according to the present invention, showing a configuration of a liquid crystal display device.
【０００８】図１の液晶表示装置は、画素アレイ部１と
駆動回路部２とに大きく分けられる。画素アレイ部１
は、例えばガラス基板上に複数本列設された信号線Ｓお
よび走査線Ｇと、信号線Ｓおよび走査線Ｇの交点付近に
形成される画素ＴＦＴ３と、画素ＴＦＴ３に接続される
画素電極５と、画素電極５と対向電極６との間に形成さ
れる液晶容量Ｃ１と、画素電極5と補助容量電極７との
間に形成される補助容量Ｃ２とを有する。The liquid crystal display device of FIG. 1 is roughly divided into a pixel array section 1 and a drive circuit section 2. Pixel array section 1
Are, for example, a plurality of signal lines S and scanning lines G arranged in a row on a glass substrate, a pixel TFT 3 formed near the intersection of the signal lines S and scanning lines G, and a pixel electrode 5 connected to the pixel TFT 3. The liquid crystal capacitor C1 is formed between the pixel electrode 5 and the counter electrode 6, and the auxiliary capacitor C2 is formed between the pixel electrode 5 and the auxiliary capacitor electrode 7.
【０００９】駆動回路部２は、不図示のホストコンピュ
ータから同期信号やデジタル画素データ等を取り込む入
力インタフェース回路１１と、画素ＴＦＴ３のゲート電
圧を制御するゲートドライバ１２と、γ補正電圧を生成
するγ補正電圧生成回路１３と、階調電圧を生成する階
調電圧生成回路１４と、対向電極６に印加するコモン電
圧Ｖcomを生成するコモン電圧生成回路１５と、画素Ｔ
ＦＴ３のソース端子に接続され信号線の電圧を制御する
ソースドライバ１６と、全体の制御を行う制御ＩＣ１７
とを備えている。The drive circuit section 2 has an input interface circuit 11 for taking in a synchronizing signal, digital pixel data, etc. from a host computer (not shown), a gate driver 12 for controlling the gate voltage of the pixel TFT 3, and a γ correction voltage γ. A correction voltage generation circuit 13, a gradation voltage generation circuit 14 that generates a gradation voltage, a common voltage generation circuit 15 that generates a common voltage Vcom applied to the counter electrode 6, and a pixel T.
A source driver 16 connected to the source terminal of the FT3 to control the voltage of the signal line, and a control IC 17 for overall control
It has and.
【００１０】ソースドライバ１６は、画素アレイ部１の
複数の信号線ごとに複数個設けられる、例えばＴＣＰ
（テープ・キャリア・パッケージ）で構成される。各ソー
スドライバ１６には、階調電圧生成回路１４から出力さ
れた階調基準電圧Ｖ０〜Ｖ９と、入力インタフェース回
路１１で取り込んだデジタル画素データとが入力され
る。各ソースドライバ１６は、デジタル画素データの値
に応じた階調電圧を階調基準電圧に基づいて生成し、所
望の電圧を対応信号線に供給する。A plurality of source drivers 16 are provided for each of the plurality of signal lines of the pixel array section 1, for example, TCP.
(Tape carrier package). The gradation reference voltages V0 to V9 output from the gradation voltage generation circuit 14 and the digital pixel data captured by the input interface circuit 11 are input to each source driver 16. Each source driver 16 generates a gradation voltage according to the value of the digital pixel data based on the gradation reference voltage, and supplies a desired voltage to the corresponding signal line.
【００１１】図２は階調電圧生成回路１４の内部構成を
示す回路図である。図示のように、階調電圧生成回路１
４は、直列接続された複数の抵抗素子からなる抵抗アレ
イ１８を有し、抵抗アレイ１８の両端には互いに反転す
る基準電圧Ｖref1，Ｖref2（例えば、一方が０Ｖで他方
が５Ｖ）が供給される。これら基準電圧Ｖref1，Ｖref2
の電圧レベルは、液晶表示装置の焼き付き、あるいはフ
リッカを低減するために１水平ライン等の所定の水平ラ
インごとや１フレームごとに反転する。FIG. 2 is a circuit diagram showing the internal structure of the gradation voltage generating circuit 14. As shown, the gradation voltage generation circuit 1
Reference numeral 4 denotes a resistance array 18 including a plurality of resistance elements connected in series, and reference voltages Vref1 and Vref2 (for example, one of which is 0V and the other of which is 5V) that are mutually inverted are supplied to both ends of the resistance array 18. . These reference voltages Vref1 and Vref2
The voltage level is inverted every predetermined horizontal line such as one horizontal line or every frame in order to reduce burn-in or flicker of the liquid crystal display device.
【００１２】図２の複数の直列接続された抵抗素子の段
間から階調電圧Ｖ０〜Ｖ９が抵抗分圧されて出力され
る。階調電圧Ｖ０〜Ｖ９は、複数の抵抗素子の抵抗比に
応じた電圧レベルになる。The gradation voltages V0 to V9 are resistance-divided and output from between the stages of the plurality of resistance elements connected in series in FIG. The gradation voltages V0 to V9 have voltage levels according to the resistance ratio of the plurality of resistance elements.
【００１３】複数の抵抗素子の段間のうち、少なくとも
一箇所に対して、γ補正電圧生成回路１３からのγ補正
電圧が印加される。図２では、階調電圧V1,V2を出力す
るノードａ，ｂにγ補正電圧を印加する例を示してい
る。The γ correction voltage from the γ correction voltage generation circuit 13 is applied to at least one of the stages of the plurality of resistance elements. FIG. 2 shows an example in which the γ correction voltage is applied to the nodes a and b that output the gradation voltages V1 and V2.
【００１４】図３はγ補正電圧生成回路１３の内部構成
の一例を示す回路図である。図３のγ補正電圧生成回路
１３は、オペアンプｏｐ１，ｏｐ２と、入力端子CONTと
オペアンプｏｐ１の出力端子との間に接続される抵抗素
子Ｒ11，Ｒ12と、オペアンプｏｐ１の正入力端子に接続
される抵抗Ｒ13，Ｒ14と、オペアンプｏｐ１の出力端子
とオペアンプｏｐ２の負入力端子との間に直列接続され
る抵抗素子Ｒ15、キャパシタＣ３および抵抗素子Ｒ16
と、オペアンプｏｐ１の出力電圧を極性ＰＯＬに応じた
電圧に変換するトランジスタＴｒ１、ダイオードＤ１お
よび抵抗素子Ｒ17，Ｒ18と、オペアンプｏｐ２の負入力
端子と出力端子との間に接続される抵抗調整回路２１
と、オペアンプｏｐ２の正入力端子に接続される抵抗調
整回路２２と、オペアンプｏｐ２の出力端子に接続され
るプシュプル回路２３とを有する。抵抗調整回路２２に
は、コモン電圧生成回路１５に供給される外部電源電圧
Ｖccと同じ電圧が印加される。FIG. 3 is a circuit diagram showing an example of the internal configuration of the γ correction voltage generation circuit 13. The γ-correction voltage generation circuit 13 in FIG. 3 is connected to operational amplifiers op1 and op2, resistance elements R11 and R12 connected between the input terminal CONT and the output terminal of the operational amplifier op1, and the positive input terminal of the operational amplifier op1. A resistor element R15, a capacitor C3, and a resistor element R16 connected in series between the resistors R13 and R14 and the output terminal of the operational amplifier op1 and the negative input terminal of the operational amplifier op2.
A transistor Tr1, a diode D1 and resistance elements R17 and R18 for converting the output voltage of the operational amplifier op1 into a voltage according to the polarity POL, and a resistance adjusting circuit 21 connected between the negative input terminal and the output terminal of the operational amplifier op2.
And a resistance adjustment circuit 22 connected to the positive input terminal of the operational amplifier op2, and a push-pull circuit 23 connected to the output terminal of the operational amplifier op2. The same voltage as the external power supply voltage Vcc supplied to the common voltage generation circuit 15 is applied to the resistance adjustment circuit 22.
【００１５】図３の回路において、入力端子CONTには０
〜３．３Ｖの範囲内の直流電圧が印加される。オペアン
プｏｐ１の出力電圧（ノードｃ）は、図４に示すように
入力端子CONTの電圧により決まる直流電圧になる。キャ
パシタＣ３の両端のノードｄ，ｅはそれぞれ図５および
図６に示すように、極性信号ＰＯＬにより変化する矩形
波電圧になる。オペアンプｏｐ２の出力電圧（ノード
ｆ）は、図７に示すように入力端子CONTが０Ｖと３．３
Ｖのときは同一電圧になり、CONTが1.65Ｖのときは極性
信号ＰＯＬに依存しない直流電圧になる。In the circuit of FIG. 3, 0 is input to the input terminal CONT.
A DC voltage in the range of -3.3V is applied. The output voltage (node c) of the operational amplifier op1 becomes a DC voltage determined by the voltage of the input terminal CONT as shown in FIG. The nodes d and e on both ends of the capacitor C3 become a rectangular wave voltage that changes according to the polarity signal POL, as shown in FIGS. 5 and 6, respectively. The output voltage (node f) of the operational amplifier op2 is 3.3V when the input terminal CONT is 0V and 3.3V as shown in FIG.
When it is V, it becomes the same voltage, and when CONT is 1.65V, it becomes a DC voltage which does not depend on the polarity signal POL.
【００１６】入力端子CONTには、コモン電圧生成回路１
５に供給されるコモン電圧生成用の外部電圧が印加され
る。すなわち、γ補正電圧生成回路１３は、コモン電圧
生成回路１５に供給されるコモン電圧生成用の外部電圧
を用いてγ補正電圧を生成する。このため、γ補正電圧
を生成するための専用の電源電圧を設ける必要がなく、
回路構成を簡略化できる。The common voltage generating circuit 1 is connected to the input terminal CONT.
An external voltage for generating a common voltage supplied to 5 is applied. That is, the γ correction voltage generation circuit 13 generates the γ correction voltage using the external voltage for common voltage generation supplied to the common voltage generation circuit 15. Therefore, there is no need to provide a dedicated power supply voltage for generating the γ correction voltage,
The circuit configuration can be simplified.
【００１７】図４〜図７に示すように、γ補正電圧生成
回路１３から出力されるγ補正電圧は、入力端子CONTに
印加される電圧に応じて変化する電圧である。γ補正電
圧は、階調電圧生成回路１４内の複数の抵抗素子の段間
（例えば、図２では、ノードａ，ｂ）に印加される。こ
れにより、複数の抵抗素子から出力される階調電圧の電
圧レベルを個別に調整できる。As shown in FIGS. 4 to 7, the γ correction voltage output from the γ correction voltage generating circuit 13 is a voltage that changes according to the voltage applied to the input terminal CONT. The γ correction voltage is applied between the stages of the plurality of resistance elements in the gradation voltage generation circuit 14 (for example, nodes a and b in FIG. 2). As a result, the voltage level of the gradation voltage output from the plurality of resistance elements can be individually adjusted.
【００１８】図８はデジタル画素データの値と階調電圧
との関係を示す図である。本実施形態の場合、点線のよ
うな線形な特性にはならず、実線のように非線形な特性
になる。これにより、中間調での表示特性を向上でき
る。FIG. 8 is a diagram showing the relationship between the value of digital pixel data and the gradation voltage. In the case of the present embodiment, the characteristic does not have a linear characteristic like a dotted line but has a nonlinear characteristic like a solid line. As a result, the display characteristics in the halftone can be improved.
【００１９】図２では、ノードａ，ｂにγ補正電圧を印
加する例を示しているが、γ補正電圧を印加する場所は
特に制限されない。実際には、個々の液晶表示装置の特
性に合わせてγ補正電圧を印加する場所を決定するのが
望ましい。Although FIG. 2 shows an example in which the γ correction voltage is applied to the nodes a and b, the place where the γ correction voltage is applied is not particularly limited. In practice, it is desirable to determine the place to apply the γ correction voltage according to the characteristics of each liquid crystal display device.
【００２０】このように、本実施形態では、階調電圧生
成回路１４内の複数の抵抗素子の段間の少なくとも一部
に、γ補正電圧を印加するようにしたため、個々の液晶
表示装置のガンマ値に合わせてγ補正を精度よく行うこ
とができ、表示品質を向上できる。このため、個々の液
晶表示装置ごとにガンマ値にばらつきがあっても、ガン
マ補正電圧を印加する場所と電圧レベルを制御すること
により、そのばらつきの影響を受けなくなる。As described above, in the present embodiment, since the γ correction voltage is applied to at least a part of the stages of the plurality of resistance elements in the grayscale voltage generation circuit 14, the γ correction voltage of each liquid crystal display device is applied. Γ correction can be performed accurately according to the value, and the display quality can be improved. Therefore, even if the gamma value varies among the individual liquid crystal display devices, it is not affected by the variation by controlling the location to apply the gamma correction voltage and the voltage level.
【００２１】上述した実施形態では、γ補正電圧生成回
路１３と階調電圧生成回路１４をソースドライバ１６と
は別個に設ける例を説明したが、γ補正電圧生成回路１
３と階調電圧生成回路１４の少なくとも一方をソースド
ライバ１６の内部に設けてもよい。In the above-described embodiment, an example in which the γ correction voltage generation circuit 13 and the gradation voltage generation circuit 14 are provided separately from the source driver 16 has been described, but the γ correction voltage generation circuit 1
At least one of 3 and the gradation voltage generation circuit 14 may be provided inside the source driver 16.
【００２２】また、上述した実施形態では、本発明に係
る表示装置を液晶表示装置に適用した例を説明したが、
本発明は列設された信号線を駆動制御する他の表示装置
（例えば、プラズマディスプレイやＥＬ表示装置など）
にも適用可能である。Further, in the above-described embodiment, an example in which the display device according to the present invention is applied to a liquid crystal display device has been described.
The present invention is another display device (for example, a plasma display or an EL display device) that drives and controls signal lines arranged in a row.
It is also applicable to.
【００２３】[0023]
【発明の効果】以上詳細に説明したように、本発明によ
れば、複数の抵抗素子間の接続ノードの少なくとも一部
にγ補正電圧を印加した状態で階調電圧を生成するた
め、個々の表示装置の特性に合わせた精度のよいγ補正
を行うことができる。As described above in detail, according to the present invention, since the gray scale voltage is generated in the state where the γ correction voltage is applied to at least a part of the connection nodes between the plurality of resistance elements, the individual gray scale voltages are generated. It is possible to perform accurate γ correction according to the characteristics of the display device.
【図１】本発明に係る表示装置の一実施形態の概略構成
を示すブロック図。FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a display device according to the present invention.
【図２】階調電圧生成回路の内部構成を示す回路図。FIG. 2 is a circuit diagram showing an internal configuration of a grayscale voltage generation circuit.
【図３】γ補正電圧生成回路１３の内部構成の一例を示
す回路図。FIG. 3 is a circuit diagram showing an example of an internal configuration of a γ correction voltage generation circuit 13.
【図４】ノードｃの電圧波形図。FIG. 4 is a voltage waveform diagram of a node c.
【図５】ノードｄの電圧波形図。FIG. 5 is a voltage waveform diagram of a node d.
【図６】ノードeの電圧波形図。FIG. 6 is a voltage waveform diagram of a node e.
【図７】ノードｆの電圧波形図。FIG. 7 is a voltage waveform diagram of a node f.
【図８】デジタル画素データの値と階調電圧との関係を
示す図。FIG. 8 is a diagram showing a relationship between digital pixel data values and gradation voltages.
１ 画素アレイ部 ２ 駆動回路部 ３ 画素ＴＦＴ １１ 入力インタフェース回路 １２ ゲートドライバ １３ ソースドライバ １４ 階調電圧生成回路 １５ コモン電圧生成回路 １６ ソースドライバ １７ 制御ＩＣ 1 Pixel array section 2 drive circuit section 3 pixel TFT 11 Input interface circuit 12 Gate driver 13 Source driver 14 Grayscale voltage generation circuit 15 Common voltage generation circuit 16 Source driver 17 Control IC
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｇ０９Ｇ 3/20 ６２４ Ｇ０９Ｇ 3/20 ６２４Ｄ ６４１ ６４１Ｃ ６４１Ｑ Ｈ０４Ｎ 5/202 Ｈ０４Ｎ 5/202 5/66 １０２ 5/66 １０２Ｂ Ｆターム(参考） 2H093 NA16 NA32 NA51 NC03 NC13 NC16 ND06 ND58 5C006 AA16 AC21 AC25 AF46 AF51 AF52 AF53 AF61 AF71 AF83 BB16 BC03 BC12 BF25 BF43 FA18 FA56 5C021 PA95 PA99 XA34 XA35 5C058 AA09 BA01 BA13 5C080 AA10 BB05 DD04 EE29 FF03 JJ02 JJ03 JJ04 JJ05 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) G09G 3/20 624 G09G 3/20 624D 641 641C 641Q H04N 5/202 H04N 5/202 5/66 102 5 / 66 102B F term (reference) 2H093 NA16 NA32 NA51 NC03 NC13 NC16 ND06 ND58 5C006 AA16 AC21 AC25 AF46 AF51 AF52 AF53 AF61 AF71 AF83 BB16 BC03 BC12 BF25 BF43 FA18 FA56 5C021 PA95 PA99 XA34 XA35 5C013 BB05A01 BA01 BA0508ABB0901 JJ03 JJ04 JJ05
Claims (10)
素と、 ２種類の基準電圧を複数の抵抗素子で抵抗分圧して、前
記信号線に供給される階調電圧を生成する階調電圧生成
回路と、 前記複数の抵抗素子間の少なくとも一つの接続経路に印
加されるγ補正用電圧を生成するγ補正電圧生成回路
と、 前記階調電圧生成回路で生成された階調電圧の中から、
デジタル画素データに応じた階調電圧を選択して対応す
る信号線に供給する信号線電圧生成回路と、を備えるこ
とを特徴とする表示装置。1. A signal line and a scanning line arranged in a row, a display pixel formed near an intersection of the signal line and the scanning line, and two types of reference voltages are resistance-divided by a plurality of resistance elements, A gradation voltage generating circuit for generating a gradation voltage supplied to a signal line; a γ correction voltage generating circuit for generating a γ correction voltage applied to at least one connection path between the plurality of resistance elements; From the gradation voltages generated by the gradation voltage generation circuit,
A signal line voltage generation circuit that selects a gradation voltage according to digital pixel data and supplies the selected signal line to a corresponding signal line.
接する前記抵抗素子間の接続経路のうち、少なくとも一
つの接続経路に前記γ補正用電圧が印加されることを特
徴とする請求項１に記載の表示装置。2. The plurality of resistance elements are connected in series, and the γ correction voltage is applied to at least one connection path among connection paths between the adjacent resistance elements. The display device according to 1.
接する前記抵抗素子間の接続経路のうち、少なくとも二
つの接続経路に前記γ補正用電圧が印加され、 前記γ補正電圧生成回路は、前記少なくとも二つの接続
経路のそれぞれに印加される前記γ補正用電圧の電圧レ
ベルを個別に制御することを特徴とする請求項１に記載
の表示装置。3. The plurality of resistance elements are connected in series, and the γ correction voltage is applied to at least two connection paths among connection paths between the adjacent resistance elements, and the γ correction voltage generation circuit is 2. The display device according to claim 1, wherein the voltage level of the γ correction voltage applied to each of the at least two connection paths is individually controlled.
と階調電圧とが非線形な関係になるような電圧値に設定
されることを特徴とする請求項１及至３のいずれかに記
載の表示装置。4. The gamma correction voltage is set to a voltage value such that the digital pixel data and the gradation voltage have a non-linear relationship. Display device.
および極性信号に応じた電圧レベルの前記γ補正用電圧
を生成することを特徴とする請求項１及至４のいずれか
に記載の表示装置。5. The display according to claim 1, wherein the γ correction voltage generation circuit generates the γ correction voltage having a voltage level according to an input control signal and a polarity signal. apparatus.
路に供給される前記２種類の基準電圧の間の電圧である
ことを特徴とする請求項５に記載の表示装置。6. The display device according to claim 5, wherein the input control signal is a voltage between the two types of reference voltages supplied to the grayscale voltage generation circuit.
種類の直流電圧信号のいずれかであることを特徴とする
請求項５または６に記載の表示装置。7. The display device according to claim 5, wherein the input control signal is one of a plurality of preset DC voltage signals.
電圧は前記入力制御信号に基づいて設定されることを特
徴とする請求項５及至７のいずれかに記載の表示装置。8. The display device according to claim 5, wherein a voltage of a counter electrode arranged to face the display device is set based on the input control signal.
れる対向基板と、を備え、 前記画素アレイ基板は、 列設された信号線および走査線と、 前記信号線および走査線の交点付近に形成される表示画
素と、 ２種類の基準電圧を複数の抵抗素子で抵抗分圧して、前
記信号線に供給される階調電圧を生成する階調電圧生成
回路と、 前記複数の抵抗素子間の少なくとも一つの接続経路に印
加されるγ補正用電圧を生成するγ補正電圧生成回路
と、 前記階調電圧生成回路で生成された階調電圧の中から、
デジタル画素データに応じた階調電圧を選択して対応す
る信号線に供給する信号線電圧生成回路と、を有するこ
とを特徴とする表示装置。9. A pixel array substrate, and a counter substrate which is arranged to face the pixel array substrate and has a counter electrode formed thereon, wherein the pixel array substrate includes signal lines and scan lines arranged in a row, A display pixel formed near the intersection of the signal line and the scanning line, and a gradation voltage generation circuit for generating a gradation voltage supplied to the signal line by resistance-dividing two kinds of reference voltages with a plurality of resistance elements. A γ correction voltage generation circuit for generating a γ correction voltage applied to at least one connection path between the plurality of resistance elements, and a gray scale voltage generated by the gray scale voltage generation circuit,
And a signal line voltage generation circuit that selects a gradation voltage according to digital pixel data and supplies the selected signal to a corresponding signal line.
素と、を備えた表示装置の駆動方法は、 ２種類の基準電圧を複数の抵抗素子で抵抗分圧して、前
記信号線に供給される階調電圧を生成し、 前記複数の抵抗素子間の少なくとも一つの接続経路に印
加されるγ補正用電圧を生成し、 前記生成された階調電圧の中から、デジタル画素データ
に応じた階調電圧を選択して対応する信号線に供給する
ことを特徴とする表示装置の駆動方法。10. A method of driving a display device, comprising: a signal line and a scanning line arranged in a row; and a display pixel formed near an intersection of the signal line and the scanning line. Resistance-dividing the resistance element to generate a gradation voltage to be supplied to the signal line, generate a γ-correction voltage applied to at least one connection path between the plurality of resistance elements, and A method of driving a display device, wherein a grayscale voltage corresponding to digital pixel data is selected from the grayscale voltages and supplied to a corresponding signal line.
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| JP2003024327A JP2003295842A (en) | 2002-01-31 | 2003-01-31 | Display device and its driving method |
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| JP2002-24257 | 2002-01-31 | ||
| JP2002024257 | 2002-01-31 | ||
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005081218A1 (en) * | 2004-02-23 | 2005-09-01 | Toshiba Matsushita Display Technology Co., Ltd. | Display signal processing apparatus and display apparatus |
| JP2008102235A (en) * | 2006-10-18 | 2008-05-01 | Sony Corp | Display device |
| US8847941B2 (en) | 2008-09-30 | 2014-09-30 | Fujitsu Ten Limited | Display device and display control device |
-
2003
- 2003-01-31 JP JP2003024327A patent/JP2003295842A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005081218A1 (en) * | 2004-02-23 | 2005-09-01 | Toshiba Matsushita Display Technology Co., Ltd. | Display signal processing apparatus and display apparatus |
| KR100766632B1 (en) * | 2004-02-23 | 2007-10-15 | 도시바 마쯔시따 디스플레이 테크놀로지 컴퍼니, 리미티드 | Display signal processing apparatus and display apparatus |
| US8698720B2 (en) | 2004-02-23 | 2014-04-15 | Japan Display Inc. | Display signal processing device and display device |
| JP2008102235A (en) * | 2006-10-18 | 2008-05-01 | Sony Corp | Display device |
| US8847941B2 (en) | 2008-09-30 | 2014-09-30 | Fujitsu Ten Limited | Display device and display control device |
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