JPS6284612A - Automatic frequency controller - Google Patents

Automatic frequency controller

Info

Publication number
JPS6284612A
JPS6284612A JP60225142A JP22514285A JPS6284612A JP S6284612 A JPS6284612 A JP S6284612A JP 60225142 A JP60225142 A JP 60225142A JP 22514285 A JP22514285 A JP 22514285A JP S6284612 A JPS6284612 A JP S6284612A
Authority
JP
Japan
Prior art keywords
signal
period
voltage
frequency
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60225142A
Other languages
Japanese (ja)
Other versions
JPH0374967B2 (en
Inventor
Toshihide Tanaka
田中 年秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60225142A priority Critical patent/JPS6284612A/en
Publication of JPS6284612A publication Critical patent/JPS6284612A/en
Publication of JPH0374967B2 publication Critical patent/JPH0374967B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To stabilize an oscillation frequency by inserting an IF reference oscillation frequency signal in a video signal period, clamping the detection output of this signal in a reference signal period in terms of DC and applying the clamped signal to two contrast clamping circuits, and detecting DC voltages in a feedback period and a synchronous period and then feeding the comparison value back to a local oscillator. CONSTITUTION:An IF signal outputted by a buffer amplifier 6 is applied to a gate switch circuit 8 through a frequency divider 7 and switched with pulses (e) within a feedback period to obtain an output (p). The output signal of a reference frequency oscillator 9 is switched with pulses (f) having the opposite polarity from the pulses (e) to obtain an output (q). The composite signal (r) of the outputs (p) and (q) is detected by an FM detector 13, whose detected DC voltage has its DC voltage part clamped with pulses (g) except during the feedback period; and voltage detection gate clamping circuit 15 and 16 clamp the inputs with pulses (h) and (i) having pulse width shown in a figure to obtain a DC current (s) corresponding to local frequency variation in the feedback period and a constant DC voltage (t) corresponding to the reference frequency which is not within the feedback period, and the difference between both voltages is detected by a voltage comparator 17 and applied to a voltage- controlled oscillation circuit 2 through a switch circuit 20.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はFM変調されたテレビ信号の受信機等における
自動周波数制御回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic frequency control circuit in a receiver of an FM-modulated television signal.

従来の技術 従来のムFG(自動周波数制御)回路例を第5図に示す
。同図でFMテレビ信号aをミキサ回路1に加え、ロー
カル発振回路2からのローカル信号すとによpIF信号
信号数り出し、バンドパスフィルタ(B、P、F)3を
経てIF増幅器4に加え、FM復調器6でビデオ出力信
号dを得る一方、ビデオ出力信号dをゲートパルス発生
器3oに加えてTVの水平期間または垂直期間のゲート
パルスmを得る。工F増幅器4の一部をバッファ増幅器
6で増幅して、7M検波器29に加えてベースバンド復
調し、その出力の基準直流電圧部分をゲートクランプ回
路31でゲートパルスmによυゲートクランプして検出
し、このクランプ電圧と直流比較基準電圧33とを電圧
比較器32で比較しその出力を低域フィルタ34を通し
、制御直流電圧kを得る。この制御直流電圧をローカル
発振器に加えてローカル発振周波数を安定化している。
2. Description of the Related Art An example of a conventional FG (automatic frequency control) circuit is shown in FIG. In the same figure, FM TV signal a is added to mixer circuit 1, the pIF signal number is calculated by the local signal from local oscillation circuit 2, and it is sent to IF amplifier 4 through bandpass filter (B, P, F) 3. In addition, the FM demodulator 6 obtains a video output signal d, and the video output signal d is applied to a gate pulse generator 3o to obtain a gate pulse m for the horizontal period or vertical period of the TV. A part of the F amplifier 4 is amplified by a buffer amplifier 6, and is added to a 7M detector 29 for baseband demodulation, and the reference DC voltage portion of the output is gate clamped by a gate pulse m by a gate clamp circuit 31. This clamp voltage is compared with a DC comparison reference voltage 33 by a voltage comparator 32, and its output is passed through a low-pass filter 34 to obtain a control DC voltage k. This control DC voltage is applied to the local oscillator to stabilize the local oscillation frequency.

jはチャンネル選局用の同調電圧である。一般にテレビ
信号のFM変調波では、水平あるいは垂直帰線期間等で
は周波数の変動しない周波数一定期間が存在するので、
この周波数一定期間に同期するゲートパルスでFMテレ
ビ信号のFM復調出力をゲートクランプすれば一定直流
電圧が得られ、このことを利用して従来はローカル発振
器を安定化している。すなわち第4図でローカル発振周
波数が変動するとIF倍信号の周波数が変化するので、
7M検波器7の出力直流電圧が変動し、その結果、ゲー
トクランプ回路31の出力直流電圧も変動する。この出
力直流電圧を電圧比較器32に加え、基準直流電圧33
と比較し、その出力を低域フィルタ34を通して、制御
直流電圧kを得てローカル発振器2にフィードバックし
、ローカル周波数を安定化している。
j is a tuning voltage for channel selection. In general, in the FM modulated wave of a television signal, there is a constant frequency period in which the frequency does not fluctuate during the horizontal or vertical retrace period, etc.
If the FM demodulated output of the FM television signal is gate-clamped using gate pulses synchronized with this fixed frequency period, a constant DC voltage can be obtained, and this has conventionally been used to stabilize the local oscillator. In other words, in Fig. 4, when the local oscillation frequency changes, the frequency of the IF multiplied signal changes, so
The output DC voltage of the 7M detector 7 fluctuates, and as a result, the output DC voltage of the gate clamp circuit 31 also fluctuates. This output DC voltage is applied to the voltage comparator 32, and the reference DC voltage 33
The output is passed through a low-pass filter 34 to obtain a control DC voltage k, which is fed back to the local oscillator 2 to stabilize the local frequency.

発明が解決しようとする問題点 このような従来の回路では、FM検波器におけるリミッ
タの不完全性、あるいは温度変化の影響等により、7M
検波直流電圧レベルが変動しローカル発振周波数の温度
等による安定性が良くなく、また基準直流電圧33も温
度特性の良いものが要求されていた。
Problems to be Solved by the Invention In such conventional circuits, 7M
The detected DC voltage level fluctuates and the stability of the local oscillation frequency due to temperature etc. is poor, and the reference DC voltage 33 is also required to have good temperature characteristics.

本発明はかかる点に鑑みてなされたもので、簡単な構成
でローカル発振周波数の安定で温度特性のすぐれた自動
周波数制御回路を提供することを目的としている。
The present invention has been made in view of these points, and it is an object of the present invention to provide an automatic frequency control circuit with a simple configuration, stable local oscillation frequency, and excellent temperature characteristics.

問題点を解決するだめの手段 本発明は上記問題点を解決するために、IF搬送波と同
じ周波数の固定基準発振器をもち、このIF基準発振周
波数信号をFM変調波のIF倍信号水平および垂直帰線
期間以外(すなわち映像信号期間)に挿入し、この基準
信号挿入IF倍信号同一のFM検波器で検波し、この直
流出力電圧をまず基準信号期間内でI)Cクランプして
基準信号期間内の直流レベルを固定する。次にこの出力
を二つの対照な回路のゲートクランプ回路に加え、一方
は水平または垂直帰線期間内のゲートパルスでDCクラ
ンプして帰線期間内の直流電圧を検出し、他方は基準信
号期間内のゲートパルスでDCクランプして同期間内の
直流電圧を検出し、この直流電圧と前記帰線期間内検出
直流電圧を電圧比較器に加え、その出力をR7周波数を
17周波数に変換する周波数変換器のローカル発振器に
フィードバックすることによりローカル発掘周波数を安
定化するものである。
Means for Solving the Problems In order to solve the above problems, the present invention has a fixed reference oscillator with the same frequency as the IF carrier wave, and converts this IF reference oscillation frequency signal into IF multiplied signals of the FM modulation wave, horizontally and vertically. This reference signal is inserted in a period other than the line period (that is, the video signal period), this reference signal inserted IF multiplied signal is detected by the same FM detector, and this DC output voltage is first I)C clamped within the reference signal period. fix the DC level. This output is then applied to the gate clamp circuits of two contrasting circuits, one is DC clamped by the gate pulse within the horizontal or vertical retrace period to detect the DC voltage within the retrace period, and the other is during the reference signal period. Detect the DC voltage within the same period by clamping the DC voltage with the gate pulse within, apply this DC voltage and the DC voltage detected within the retrace period to a voltage comparator, and convert the output from the R7 frequency to the 17 frequency. It stabilizes the local excavation frequency by feeding back to the local oscillator of the converter.

作用 本発明は上記した構成により、固定基準発振周波数にI
F搬送波周波数をロック出来るとともに、周波数変動を
検出するFM検波器の出力をまず基準発振周波数期間で
クランプしているので、FM検波器の出力直流電圧レベ
ルが温度等で変動しても基準発振周波数期間の直流電圧
レベルはほとんど変化しないし、直流電圧レベルはクラ
ンプレベルを調整することにより任意に設定出来るので
電圧比較器の動作最適レベルに持っていける。さらに、
クランプ出力直流電圧の帰線期間部と、基準発振周波数
期間部の直流電圧を同型の2個の対照なりランプ回路で
別々にクランプ検出して各部の直流電圧を抽出してホー
ルドし、各検出直流電圧を電圧比較器に加えるので、た
とえ2つのクランプ回路で温度変化があっても二つの回
路を同型で対照に構成しているので、二つの検出直流電
圧の温度変化による差も十分に押えることが出来る。
Effect The present invention has the above-described configuration, and the fixed reference oscillation frequency is
In addition to being able to lock the F carrier frequency, the output of the FM detector that detects frequency fluctuations is first clamped at the reference oscillation frequency period, so even if the output DC voltage level of the FM detector fluctuates due to temperature etc., the reference oscillation frequency remains unchanged. The DC voltage level during the period hardly changes, and since the DC voltage level can be set arbitrarily by adjusting the clamp level, it can be brought to the optimum level for the operation of the voltage comparator. moreover,
The DC voltages in the retrace period part and the reference oscillation frequency period part of the clamp output DC voltage are clamped and detected separately using two symmetric lamp circuits of the same type, and the DC voltages at each part are extracted and held, and each detected DC voltage is Since the voltage is applied to the voltage comparator, even if there is a temperature change in the two clamp circuits, the two circuits are of the same type and are configured symmetrically, so the difference due to temperature change in the two detected DC voltages can be sufficiently suppressed. I can do it.

すなわち、本構成によれば、電圧比較器に加わる直流電
圧レベルの温度による絶対値の変動を押えるとともに、
電圧比較器へ加わえる二つの制御直流電圧間の温度変化
も十分押えることが出来るので、周波数制御信号として
非常に安定な発振周波数制御電圧が得られる自動周波数
制御回路を形成することが出来、この出力電圧で電圧制
御発振器を制御すれば非常に安定なローカル発振信号を
得ることが出来る。
That is, according to this configuration, fluctuations in the absolute value due to temperature of the DC voltage level applied to the voltage comparator are suppressed, and
Since the temperature change between the two control DC voltages applied to the voltage comparator can be sufficiently suppressed, it is possible to form an automatic frequency control circuit that can obtain a very stable oscillation frequency control voltage as a frequency control signal. If a voltage controlled oscillator is controlled by the output voltage, a very stable local oscillation signal can be obtained.

実施例 第1図は本発明の人FG回路における発振周波数制御信
号検出回路の一実施例を示すプロ’Vり図である。第1
図において、aは入力FMテレビ信号、bは電圧制御L
oc2L1発振器2から発生するローカル信号で両信号
はミキサ回路1で混合されてIP(中間周波数)信号C
が出力され、3のB、P、F 、 4のIF増幅器を通
シ5のFM復調器テ検波すれベースバンドビデオ信号d
を得る。6はIF用バッファ増幅器で4のIF増幅器か
らのIF倍信号、バッファ増幅し、一部をIF倍信出力
lとして出し、残りをRの分周器7に加え、その分周出
力を第1のゲートスイッチ回路8に加え、水平又は垂直
等の帰線期間内パルスeで帰線期間部のみスイッチされ
出力pとなり、信号合成器12に加えられ、基準周波数
発振器9かもの基準周波数信号を第2のゲートスイ・ノ
チ回路10でパルスeと逆極性のパルスfでスイ・ソチ
され出力qとなり、pと同様信号合成器12に加えられ
、その出力として合成信号rが得られる。この合成信号
rはFM検波器13で検波され、二つのレベルをもつ直
流電圧、すなわち1つはローカル周波数の変化に追従し
て直流レベルが変わる帰線期間内での電圧と、他は直流
レベルが基本的に変化しない帰線期間以外の基準周波数
信号期間での電圧とを持つ。この検波直流電圧は、クラ
ンプ回路14でパルスfの期間内でパルスfよりパルス
幅の狭いクランプパルスgにより帰線期間以外の直流電
圧部がクランプされ一定に保持され、電圧検出ゲートク
ランプ回路15.16に加えられて、パルス0の期間内
でパルスeよυパルス幅が同等以下のパルスh1および
パルスfの期間内でパルスfよりパルス幅の狭いパルス
1(パルスqと同じでもよい)によりゲートクランプす
る事により、帰線期間内のローカル周波数変化に対応す
る直流電圧Sおよび帰線期間外の基準周波数に対応する
一定直流電圧tを得、それらを電圧比較器17で二つの
電圧差に対応する出力電圧を増幅して検出し、ローパス
フィルタ18を通し、コントロールを圧にとしてスイッ
チ回路20を通して電圧制御ローカル発振回路2に加え
てローカル発振周波数を安定化している。スイッチ回路
20はゲートパルスeを検出する回路21により制御さ
れ、ゲート・パルスeが存在する時はコントロール電圧
kを通過させ、ゲートパルス0が存在しない時は直流電
圧スイッチ回路2oがはたらきコントロール電圧にの代
わりに固定電圧22が強制的にローカル発振回路2に加
えられる。これは受信機の電源オン時にゲートパルスが
発生するまでの期間のみローカル発振回路2の制御電圧
を一定にし、映像信号、ゲートパルス信号を発生しやす
くするためである。
Embodiment FIG. 1 is a schematic diagram showing an embodiment of the oscillation frequency control signal detection circuit in the human FG circuit of the present invention. 1st
In the figure, a is the input FM television signal, b is the voltage control L
oc2L1 A local signal generated from oscillator 2. Both signals are mixed in mixer circuit 1 to produce IP (intermediate frequency) signal C.
is output, and the baseband video signal d is detected by the FM demodulator (5) through the IF amplifier (3), B, P, F (3), and the IF amplifier (4).
get. Reference numeral 6 is an IF buffer amplifier which buffer-amplifies the IF multiplied signal from the IF amplifier 4, outputs a part as the IF doubler output l, adds the remainder to the frequency divider 7 of R, and outputs the frequency divided output to the first In addition to the gate switch circuit 8, only the retrace period part is switched by the horizontal or vertical retrace period pulse e, and the output p is applied to the signal synthesizer 12, and the reference frequency signal of the reference frequency oscillator 9 is switched to the output p. In the gate switching circuit 10 of No. 2, the signal is switched with a pulse f having a polarity opposite to that of the pulse e, resulting in an output q, which is added to the signal synthesizer 12 in the same way as p, and a synthesized signal r is obtained as its output. This composite signal r is detected by the FM detector 13, and has two levels of DC voltage, one is the voltage during the retrace period where the DC level changes according to the change in the local frequency, and the other is the DC level. has a voltage in the reference frequency signal period other than the retrace period that basically does not change. This detected DC voltage is held constant within the period of pulse f by clamping the DC voltage portion other than the retrace period by clamp pulse g having a narrower pulse width than pulse f within the period of pulse f, and voltage detection gate clamp circuit 15. In addition to 16, the gate is gated by a pulse h1 whose pulse width is equal to or less than the pulse e within the pulse 0 period, and a pulse 1 (which may be the same as the pulse q) whose pulse width is narrower than the pulse f within the pulse f period. By clamping, a DC voltage S corresponding to the local frequency change within the retrace period and a constant DC voltage t corresponding to the reference frequency outside the retrace period are obtained, and the voltage comparator 17 uses them to correspond to the difference between the two voltages. The output voltage is amplified and detected, passed through a low-pass filter 18, and applied to the voltage-controlled local oscillation circuit 2 through a switch circuit 20 using a control voltage to stabilize the local oscillation frequency. The switch circuit 20 is controlled by a circuit 21 that detects the gate pulse e, and when the gate pulse e is present, the control voltage k is passed through, and when the gate pulse 0 is not present, the DC voltage switch circuit 2o operates and changes the control voltage to the control voltage. Instead, a fixed voltage 22 is forcibly applied to the local oscillation circuit 2. This is to keep the control voltage of the local oscillation circuit 2 constant only during the period until a gate pulse is generated when the receiver is powered on, thereby making it easier to generate a video signal and a gate pulse signal.

19は発振周波数制御信号検出回路部を示している。ま
たlはIF信号出力の一部で音声信号復調器等へ供給す
るだめのものである。
Reference numeral 19 indicates an oscillation frequency control signal detection circuit section. Further, l is a part of the IF signal output and is not to be supplied to an audio signal demodulator or the like.

第2図は第1図の中の発振周波数制御信号検出回路部1
9の具体回路例を示す。同図でFM検波器13からの検
波直流電圧をエミッタフォロアトランジスタTR1を通
した後、映像信号通過コンデンサC1を通してFET 
トランジスタTR2のド1/インに加え、ゲートパルス
gによりソース。
Figure 2 shows the oscillation frequency control signal detection circuit section 1 in Figure 1.
9 shows a specific circuit example. In the same figure, the detected DC voltage from the FM detector 13 is passed through the emitter follower transistor TR1, and then passed through the video signal passing capacitor C1 to the FET.
In addition to the do1/in of transistor TR2, the gate pulse g causes the source.

マース間コンデン、すC2と抵抗R2+ R4及び可変
抵抗R3で決定される直流電圧にクランプされ次段のゲ
ートクランプ用FET)ランジスタTR3およびTR4
の各ソースに加えられる。TR3。
It is clamped to the DC voltage determined by the Mars capacitor, C2, resistor R2+ R4 and variable resistor R3, and is connected to the next stage gate clamp FET) transistors TR3 and TR4.
added to each sauce. TR3.

TR4のゲートにはゲートパルス丘、iが加わり、各ド
レイン端子に各ゲートクランプ出力電圧を得、TR5,
TR6のソースフォロアFET)ランジスタの各ソース
より取り出され、各出力直流電圧を電圧比較器17に加
え、ローパスフィルタ18を通してコントロール電圧k
が取り出される。同図でR4はエミッタ抵抗、R5,R
6はゲート抵抗、c3.c4はクランプ用コンデンサ、
R,、R8はゲート入力抵抗、Rtp r Joはソー
ス抵抗(例、R,:=1にΩ。
A gate pulse hill, i, is added to the gate of TR4, and each gate clamp output voltage is obtained at each drain terminal, and TR5,
Source follower FET of TR6
is taken out. In the same figure, R4 is the emitter resistance, R5, R
6 is a gate resistance, c3. c4 is a clamp capacitor,
R,, R8 is the gate input resistance, and Rtp r Jo is the source resistance (eg, R,:=1 is Ω.

R1o=10にΩ)で、TR5の出力ソース電圧を分圧
し、R11,R52はソース抵抗(例、R,、:2にΩ
R1o = 10Ω) divides the output source voltage of TR5, and R11 and R52 are source resistances (e.g., R, , :2 = Ω).
.

R,2= 9 KΩ)で、R,+ R,、o= R,、
+ R1□としTl’t6.TR6の全ソース抵抗を同
じとして、R11の可変抵抗で電圧比較器の基準電圧を
最適に調整出来るようにし、第1図のムFC回路の動作
時に発振周波数の微調整を行なうようにしている。第2
図の回路例ではTR2でFM検波直流電圧をクランプし
ているのでその以前の回路での直流電圧レベルの温度に
よる変動は影響なく、また、TR2のクランプ回路以降
もTR3,TR4およびTR5゜TR6が全く対称なの
で温度による影響も同じと考えられるから電圧比較器1
70入力S、Tの差の温度の影響による変動は殆んどな
くなり、安定な電圧比較器出力が得られ、その結果、温
度安定度の良いAFC回路を構成することが出来る。
R,2= 9 KΩ), and R,+R,,o=R,,
+R1□ and Tl't6. With all the source resistances of TR6 being the same, the reference voltage of the voltage comparator can be optimally adjusted using the variable resistor R11, and the oscillation frequency can be finely adjusted during operation of the FC circuit shown in FIG. Second
In the circuit example shown in the figure, the FM detection DC voltage is clamped by TR2, so the temperature-related fluctuations in the DC voltage level in the previous circuit have no effect, and TR3, TR4, and TR5゜TR6 are also used after the clamp circuit of TR2. Since it is completely symmetrical, the influence of temperature can be considered to be the same, so voltage comparator 1
There is almost no variation in the difference between the inputs S and T due to the influence of temperature, and a stable voltage comparator output is obtained. As a result, an AFC circuit with good temperature stability can be constructed.

第3図にビデオ信号dに対する各信号の時間位置関係を
示している。同図でビデオ信号dのT1は水平(又は垂
直)走査期間、T2は水平(又は垂直)帰線期間で、T
3は帰線期間間のペデスタル等の一定直流電圧期間(ま
たは多重キャリア信号挿入期間)で、T4はT5以外の
期間、Uは水平(または垂直)同期信号である。CはI
F中間周波信号でFM変調波なので、少くともT3期間
は無変調の一定周波数IF信号(または多重された一定
周波数キャリア信号のIF倍信号となり、eのゲートパ
ルスは前述の73期の一定周波数IF濡号のみゲートし
、信号pを得fのゲートパルスはeの逆極性パルスで基
準発振周波数信号をゲートし信号qを得、この信号pと
qは第1図の合成器12でゲートパルスeあるいはfに
よりスイッチ切り換え合成され第3図の合成信号rを得
る。
FIG. 3 shows the temporal positional relationship of each signal with respect to the video signal d. In the figure, T1 of the video signal d is a horizontal (or vertical) scanning period, T2 is a horizontal (or vertical) retrace period, and T
3 is a constant DC voltage period (or multicarrier signal insertion period) such as a pedestal between blanking periods, T4 is a period other than T5, and U is a horizontal (or vertical) synchronization signal. C is I
Since it is an F intermediate frequency signal and an FM modulated wave, at least during the T3 period it becomes an unmodulated constant frequency IF signal (or an IF multiplied signal of the multiplexed constant frequency carrier signal, and the gate pulse of e is the constant frequency IF signal of the 73rd period mentioned above). The gate pulse of f gates the reference oscillation frequency signal with the opposite polarity pulse of e to obtain the signal q, and these signals p and q are converted into the gate pulse e by the synthesizer 12 in FIG. Alternatively, the signals are switched and synthesized by f to obtain the synthesized signal r shown in FIG.

ゲートパルスgは信号rの中のT4期間(基準発振周波
数期間)の一部をゲートするパルスで、hはT5期間内
のゲートパルス、iはで4期間内のゲートパルスである
The gate pulse g is a pulse that gates a part of the T4 period (reference oscillation frequency period) in the signal r, h is the gate pulse within the T5 period, and i is the gate pulse within the 4th period.

第4図に他の実施例を示す。同図で同一番号は同一物を
示し、23は第2の電圧制御ローカル発振器で、24は
第2のミキサ回路、26は第2IFのバンドパスフィル
タ、26は第2IFの工F増幅器、27は分周器、28
は基準周波数発振器である。第4図の構成では入力RF
信号はダブルコンバータで第2IF周波数を低くしてい
るので、信号処理がやり易い。、また、帰期期間に音声
信号。
FIG. 4 shows another embodiment. In the figure, the same numbers indicate the same things, 23 is the second voltage controlled local oscillator, 24 is the second mixer circuit, 26 is the band pass filter of the second IF, 26 is the engineered frequency amplifier of the second IF, and 27 is the second IF amplifier. Frequency divider, 28
is the reference frequency oscillator. In the configuration shown in Figure 4, the input RF
Since the signal uses a double converter to lower the second IF frequency, signal processing is easy. , and also the audio signal during the return period.

データ信号等をQ、 P、 S、 KあるいはB、 P
、 S、 K変調等でRF多重挿入されている信号を復
調する場合もIF倍信出力lを低くしておくと各復調回
路も取シ扱い易い。またB、P、S、K 、 Q、P、
S、に変調波を復調する場合、変調キャリア周波数は非
常に安定なものが要求されるので、設計に自由度をもた
せるため第2ミキサ回路を導入し、IF周波数を下げ、
第20−カル発振器を十分安定な人FC回路で制御する
ことにより、精度良い第2IF周波数を得ている。
Q, P, S, K or B, P for data signals etc.
When demodulating a signal subjected to RF multiplex insertion using , S, K modulation, etc., each demodulation circuit can be easily handled by keeping the IF doubling output l low. Also B, P, S, K, Q, P,
When demodulating the modulated wave to
By controlling the 20th Cal oscillator with a sufficiently stable human FC circuit, a highly accurate second IF frequency is obtained.

発明の効果 以上述べたように、本発明によれば、簡単な回路構成で
、従来より安定で温度特性の良い自動周波数制御回路を
得られるので、周波数精度の良い中間周波数信号を得る
ことが出来、Q、 P、 S、 K等のディジタル変調
信号の復調用受信機等に特に有効である。
Effects of the Invention As described above, according to the present invention, it is possible to obtain an automatic frequency control circuit with a simple circuit configuration that is more stable and has better temperature characteristics than the conventional one, so it is possible to obtain an intermediate frequency signal with high frequency accuracy. , Q, P, S, K, etc., is particularly effective for demodulating receivers and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における自動周波数制御装置
のブロック図、第2図は第1図の発振周波数制御信号検
出回路部の具体回路図、第3図は第1図の各入出力端子
、各ゲート端子における信号波形図、第4図は本発明の
他の実施例における自動周波数制御装置のブロック図、
第5図は従来の自動周波数制御装置のブロック図である
。 1・・・・・・ミキサ回路、2 ・・・・ローカル発振
回路、8.10・・・・・ゲートスイッチ回路、12・
・・・・・信号合成器、9・・・・・・基準周波数発振
器、14・・・・・クランプ回路、15.16・・・・
・・電圧検出ゲートクランプ回路、17・・・・・・電
圧比較器、2o・・・・・直流電圧スイ・ソチ回路 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第3
図 第4図
Fig. 1 is a block diagram of an automatic frequency control device according to an embodiment of the present invention, Fig. 2 is a specific circuit diagram of the oscillation frequency control signal detection circuit section of Fig. 1, and Fig. 3 is each input/output shown in Fig. 1. Terminal, signal waveform diagram at each gate terminal, FIG. 4 is a block diagram of an automatic frequency control device in another embodiment of the present invention,
FIG. 5 is a block diagram of a conventional automatic frequency control device. 1...Mixer circuit, 2...Local oscillation circuit, 8.10...Gate switch circuit, 12...
... Signal synthesizer, 9 ... Reference frequency oscillator, 14 ... Clamp circuit, 15.16 ...
...Voltage detection gate clamp circuit, 17...Voltage comparator, 2o...DC voltage switch Sochi circuit Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4

Claims (5)

【特許請求の範囲】[Claims] (1)周期的に一定周波数搬送波期間となる被変調波R
F信号とローカル発振器よりのローカル信号とをミキサ
回路で混合して得た中間周波数信号と、基準周波数発生
器からの基準周波数信号とを信号切換回路で周期的に入
れ換えることにより、前記一定周波数搬送波期間以外の
期間内に基準周波数信号を挿入してできた比較用合成中
間周波信号を周波数検波回路あるいは位相検波回路に加
えて検波直流電圧を得るとともに、この検波直流電圧の
基準周波数信号期間を第1のゲートパルスでクランプし
、このクランプ出力の前記一定周波数搬送波期間および
前記基準周波数信号期間の各直流電圧を第2および第3
のゲートパルスでゲート検出して第1および第2の検出
直流電圧を取り出し、この第1および第2の検出直流電
圧を電圧比較器に加え、その出力直流電圧で前記ローカ
ル発振器の周波数を制御することを特徴とする自動周波
数制御装置。
(1) Modulated wave R that periodically has a constant frequency carrier wave period
By periodically switching between an intermediate frequency signal obtained by mixing the F signal and a local signal from a local oscillator in a mixer circuit and a reference frequency signal from a reference frequency generator in a signal switching circuit, the constant frequency carrier wave is A comparison synthetic intermediate frequency signal generated by inserting a reference frequency signal in a period other than the period is added to a frequency detection circuit or a phase detection circuit to obtain a detected DC voltage, and the reference frequency signal period of this detected DC voltage is 1 gate pulse, and the respective DC voltages of the constant frequency carrier wave period and the reference frequency signal period of this clamp output are applied to the second and third gate pulses.
Gate detection is performed using a gate pulse of , and first and second detected DC voltages are extracted, and the first and second detected DC voltages are applied to a voltage comparator, and the frequency of the local oscillator is controlled by the output DC voltage. An automatic frequency control device characterized by:
(2)合成中間周波信号において、中間周波数の期間を
前記一定周波数搬送波期間を含みかつ、この一定周波数
搬送波期間より長くし、かつ、第2のゲートパルス期間
を一定周波数搬送波期間より短かくした事を特徴とする
特許請求の範囲第1項記載の自動周波数制御装置。
(2) In the composite intermediate frequency signal, the intermediate frequency period includes the constant frequency carrier period and is longer than the constant frequency carrier period, and the second gate pulse period is shorter than the constant frequency carrier period. An automatic frequency control device according to claim 1, characterized in that:
(3)第1及び第3のゲートパルスを同一としたことを
特徴とする特許請求の範囲第1項または第2項記載の自
動周波数制御装置。
(3) The automatic frequency control device according to claim 1 or 2, wherein the first and third gate pulses are the same.
(4)中間周波信号および前記基準周波数信号のうち少
なくとも一方を分周し、両者の周波数をほゞ同一にした
後、前記信号切り換え回路に加えて周期的に入れ換える
ことにより前記比較用合成中間周波信号を得ることを特
徴とする特許請求の範囲第1項または第2項または第3
項記載の自動周波数制御装置。
(4) After dividing at least one of the intermediate frequency signal and the reference frequency signal to make both frequencies substantially the same, the composite intermediate frequency signal for comparison is added to the signal switching circuit and periodically switched. Claim 1 or 2 or 3 characterized in that the signal is obtained.
The automatic frequency control device described in Section 1.
(5)ゲートパルス信号あるいは信号切換用スイッチン
グパルスが存在しない場合、ローカル発振制御電圧とし
て固定直流電圧に切り換えることを特徴とする特許請求
の範囲第1項または第2項または第3項または第4項記
載の自動周波数制御装置。
(5) If there is no gate pulse signal or signal switching switching pulse, the local oscillation control voltage is switched to a fixed DC voltage. The automatic frequency control device described in Section 1.
JP60225142A 1985-10-09 1985-10-09 Automatic frequency controller Granted JPS6284612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60225142A JPS6284612A (en) 1985-10-09 1985-10-09 Automatic frequency controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60225142A JPS6284612A (en) 1985-10-09 1985-10-09 Automatic frequency controller

Publications (2)

Publication Number Publication Date
JPS6284612A true JPS6284612A (en) 1987-04-18
JPH0374967B2 JPH0374967B2 (en) 1991-11-28

Family

ID=16824607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60225142A Granted JPS6284612A (en) 1985-10-09 1985-10-09 Automatic frequency controller

Country Status (1)

Country Link
JP (1) JPS6284612A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941050A (en) * 1988-04-27 1990-07-10 U.S. Philips Corporation An afc arrangement for tuning a television receiving apparatus to a select transmission having an actual carrier frequency which differs from a nominal carrrier frequency

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941050A (en) * 1988-04-27 1990-07-10 U.S. Philips Corporation An afc arrangement for tuning a television receiving apparatus to a select transmission having an actual carrier frequency which differs from a nominal carrrier frequency

Also Published As

Publication number Publication date
JPH0374967B2 (en) 1991-11-28

Similar Documents

Publication Publication Date Title
WO1994010751A1 (en) Clipper circuitry
JPS6284612A (en) Automatic frequency controller
CA1091340A (en) Television receiver having a synchronous detection circuit and a frequency deviation-detection circuit
US3780219A (en) Signal processing circuit
JPS5943036B2 (en) Circuit layout in color television encoder
US4362906A (en) FM Receiver
US4589016A (en) FM television signal receiving circuit
US4486782A (en) Frequency stabilization of a VCO FM modulator
KR100278524B1 (en) Television receiver with auxiliary video clamp
US5122865A (en) Chroma key signal generator for a video editing apparatus
US4158211A (en) Automatic frequency control apparatus for television receiver
US4263609A (en) Automatic deviation limit control circuit for secam encoders
KR100231501B1 (en) Chroma signal processing apparatus
KR100459692B1 (en) Radio Frequency Modulation Device Using Phase-Locked Loop
US3733562A (en) Signal processing circuit for a color television receiver
JP2947573B2 (en) Demodulator
JPS6111517B2 (en)
KR850001618Y1 (en) Switched afpc loop filter with off set voltage cancellation
JPS5926681Y2 (en) stereo demodulation circuit
JPH04188960A (en) Vertical synchronizing signal switching device
JP2670275B2 (en) Television receiver
JPH036070Y2 (en)
KR900005318Y1 (en) Audio carrier automatic selecting circuit for satellite broadcast receiver
GB2048610A (en) Automatic limit control for S.E.C.A.M. encoder
JPH0141062B2 (en)