JPS6284546A - Protective circuit for output - Google Patents
Protective circuit for outputInfo
- Publication number
- JPS6284546A JPS6284546A JP60225256A JP22525685A JPS6284546A JP S6284546 A JPS6284546 A JP S6284546A JP 60225256 A JP60225256 A JP 60225256A JP 22525685 A JP22525685 A JP 22525685A JP S6284546 A JPS6284546 A JP S6284546A
- Authority
- JP
- Japan
- Prior art keywords
- output
- junction type
- series
- resistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract description 4
- 230000005669 field effect Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は出力保護回路に関し、特に絶縁ゲート型電界効
果トランジスタ集積回路の出力保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output protection circuit, and more particularly to an output protection circuit for an insulated gate field effect transistor integrated circuit.
従来、この種の出力保護回路は、出力インピーダンスの
規格ヲ滴たす程度の抵抗体(約tom)を挿入し、出力
トランジスタのオン抵抗を十分小さくすることにより行
なってい友。Conventionally, this type of output protection circuit has been implemented by inserting a resistor (approximately tom) that satisfies the output impedance standard and sufficiently reducing the on-resistance of the output transistor.
第2図は従来の出力保護回路の一例の回路図である。FIG. 2 is a circuit diagram of an example of a conventional output protection circuit.
第2図に示すように、対をなす出力用の絶縁ゲート型電
界効果トランジスタ(以下、MO8FETと記す)11
.13のドレインを接続し、その接続点の節点9に抵抗
体12の一端を接続し、抵抗体12の他端を出力端子8
に接続している。As shown in FIG. 2, a pair of output insulated gate field effect transistors (hereinafter referred to as MO8FET) 11
.. 13, one end of the resistor 12 is connected to the node 9 of the connection point, and the other end of the resistor 12 is connected to the output terminal 8.
is connected to.
このような構成では、MO8FET 11.13に要求
される電流量が大きい場合、すなわちMO8FET11
.13のオン抵抗が小さい場合には、挿入しうる抵抗体
12の抵抗値に制限を生じ、抵抗値は100又はそれ以
下になる。In such a configuration, if the amount of current required for MO8FET 11.13 is large, that is, MO8FET 11.
.. When the on-resistance of the resistor 13 is small, there is a restriction on the resistance value of the resistor 12 that can be inserted, and the resistance value becomes 100 or less.
一方、抵抗体12を挿入することによる出力保護の機能
は、抵抗値が大きい程発揮され、通常、500以上を必
要とする。On the other hand, the function of output protection by inserting the resistor 12 is improved as the resistance value increases, and usually requires 500 or more.
上述した従来の出力保護回路は、大電流出力を必要とす
る場合、出力インピーダンスを確保する友めにトランジ
スタサイズを大きくする必要があるとともに、抵抗値が
100又はそれ以下になるので、保護素子として機能し
なくなるという問題点がある。In the conventional output protection circuit described above, when a large current output is required, it is necessary to increase the transistor size to ensure output impedance, and the resistance value is 100 or less, so it is not suitable as a protection element. The problem is that it no longer functions.
本発明の目的は、個個のトランジスタサイズを大きくす
る必要がなく、かつ抵抗値を高くできる出力保護回路を
提供することにある。An object of the present invention is to provide an output protection circuit that does not require increasing the size of each transistor and can increase the resistance value.
c問題点を解決するための手段〕
本発明の出力保護回路は、対をなす出力トランジスタの
一方をM(Mは2以上の整数)個に分割しt第1の絶縁
ゲート型電界効果トランジスタ群と、前記出力トランジ
スタの他方2N(Nは2以上の整数)個に分割し之第2
の絶縁ゲート型電界効果トランジスタ群と、一端が前記
第1及び第2の絶縁ゲート型電界効果トランジスタ群の
それぞれの絶縁ゲート型電界効果トランジスタに直列接
続される非接合型抵抗体と、一方が非接合型抵抗体の他
端に接続され他方が出力端子に接続される金属配線とを
含んで構成される。[Means for Solving Problem c] The output protection circuit of the present invention divides one of the output transistors in a pair into M (M is an integer of 2 or more), and divides one of the output transistors into a first insulated gate field effect transistor group. and the other of the output transistors is divided into 2N (N is an integer of 2 or more).
a non-junction resistor having one end connected in series with each insulated gate field effect transistor of the first and second insulated gate field effect transistor groups; The metal wiring is connected to the other end of the junction type resistor and the other end is connected to the output terminal.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
第1図に示すように、本実施例は対をなす出力用のMO
SFETのPチャネル側のMO8FFJT 1に非接合
型抵抗体(例えば、多結晶シリコン層)2の一端金直列
に接続しt単位回路5−1〜5−Nと。As shown in FIG. 1, this embodiment has a pair of output MO
One end of a non-junction type resistor (for example, a polycrystalline silicon layer) 2 is connected in series with gold to the MO8FFJT 1 on the P channel side of the SFET, and t unit circuits 5-1 to 5-N are connected.
Nチャネル側のMOSFET aに非接合型抵抗体4の
一端を直列に接続した単位回路6−1〜5−M抵抗体2
.4の他端と出力端子8とをアルミニウム等の金属配線
で接続している。なお、それぞれのMOSFET 1及
び3のドレイン・ソース間には保護ダイオード7が並列
に接続されている。Unit circuits 6-1 to 5-M resistor 2 in which one end of non-junction type resistor 4 is connected in series to MOSFET a on the N-channel side.
.. The other end of 4 and the output terminal 8 are connected by metal wiring such as aluminum. Note that a protection diode 7 is connected in parallel between the drain and source of each MOSFET 1 and 3.
このように構成することにより、Pチャ′ネル側ではN
倍、Nチャネル側ではM倍の抵抗値會有す。With this configuration, N on the P channel side
On the N channel side, the resistance value is M times as high.
る抵抗体管挿入できるので、個個のMOSFETに対す
る保護能力が増大する。Since a resistor tube can be inserted into the MOSFET, the protection ability for each MOSFET is increased.
さらに、静電気を放電する経路がそれぞれN倍。Furthermore, the number of paths for discharging static electricity is N times larger.
M倍となり、それぞれの保護ダイオード7及び非接合型
抵抗体2.4にかかる応力yt/N、x/Mにできる。M times, and the stress applied to each protective diode 7 and non-junction type resistor 2.4 becomes yt/N and x/M.
なお、上記実施例では0MO8FET を用いたが、N
チャネル型MO8FET% Pチャネル型MO8FET
でも同様に本発明を適用できる。In addition, although 0MO8FET was used in the above example, N
Channel type MO8FET% P channel type MO8FET
However, the present invention can be similarly applied.
以上説明したように本発明の出力保護回路は、MOSF
ETと非接合型抵抗体とを直列に接続し文単位回路を複
数個並列に接続することによシ、各MO8FETのサイ
ズを大きくする必要がなく、かりそれぞれの非接合型抵
抗体の抵抗値を高くできるので、出力保護機能を向上で
きるといケ効果がある。As explained above, the output protection circuit of the present invention is a MOSFET.
By connecting an ET and a non-junction type resistor in series and connecting multiple sentence unit circuits in parallel, there is no need to increase the size of each MO8FET, and the resistance value of each non-junction type resistor can be reduced. This has the effect of improving the output protection function.
さらに、静電気保護機能を向上できるという副次的効果
がある。Furthermore, there is a secondary effect that the electrostatic protection function can be improved.
第1図は本発明の一実施例の回路図、第2図は従来の出
力保護回路の一例の回路図である。
2.4・・・・・・非接合型抵抗体、5−1〜5−N。
6−1〜6−M・・・・・・単位回路、7・・・・・・
保護ダイオード、8・・・・・・出力端子。
代理人 弁理士 内 原 旨 ゛(、FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional output protection circuit. 2.4...Non-junction type resistor, 5-1 to 5-N. 6-1 to 6-M...Unit circuit, 7...
Protection diode, 8... Output terminal. Agent Patent Attorney Uchihara Uji ゛(,
Claims (1)
数)個に分割した第1の絶縁ゲート型電界効果トランジ
スタ群と、前記出力トランジスタの他方をN(Nは2以
上の整数)個に分割した第2の絶縁ゲート型電界効果ト
ランジスタ群と、一端が前記第1及び第2の絶縁ゲート
型電界効果トランジスタ群のそれぞれの絶縁ゲート型電
界効果トランジスタに直列接続される非接合型抵抗体と
、一方が該非接合型抵抗体の他端に接続され他方が出力
端子に接続される金属配線とを含むことを特徴とする出
力保護回路。A first insulated gate field effect transistor group in which one of the pair of output transistors is divided into M (M is an integer of 2 or more), and the other output transistor is divided into N (N is an integer of 2 or more). a divided second insulated gate field effect transistor group; and a non-junction resistor whose one end is connected in series to each insulated gate field effect transistor of the first and second insulated gate field effect transistor groups. , and a metal wire, one end of which is connected to the other end of the non-junction type resistor and the other end of which is connected to an output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60225256A JPS6284546A (en) | 1985-10-08 | 1985-10-08 | Protective circuit for output |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60225256A JPS6284546A (en) | 1985-10-08 | 1985-10-08 | Protective circuit for output |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6284546A true JPS6284546A (en) | 1987-04-18 |
Family
ID=16826458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60225256A Pending JPS6284546A (en) | 1985-10-08 | 1985-10-08 | Protective circuit for output |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6284546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4990802A (en) * | 1988-11-22 | 1991-02-05 | At&T Bell Laboratories | ESD protection for output buffers |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6037156A (en) * | 1983-08-08 | 1985-02-26 | Nec Corp | Protective circuit for output |
JPS60158671A (en) * | 1983-12-22 | 1985-08-20 | テキサス インスツルメンツ インコーポレイテツド | Insulated gate electrode field effect transistor |
-
1985
- 1985-10-08 JP JP60225256A patent/JPS6284546A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6037156A (en) * | 1983-08-08 | 1985-02-26 | Nec Corp | Protective circuit for output |
JPS60158671A (en) * | 1983-12-22 | 1985-08-20 | テキサス インスツルメンツ インコーポレイテツド | Insulated gate electrode field effect transistor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4990802A (en) * | 1988-11-22 | 1991-02-05 | At&T Bell Laboratories | ESD protection for output buffers |
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