JPS6447038U - - Google Patents
Info
- Publication number
- JPS6447038U JPS6447038U JP14145487U JP14145487U JPS6447038U JP S6447038 U JPS6447038 U JP S6447038U JP 14145487 U JP14145487 U JP 14145487U JP 14145487 U JP14145487 U JP 14145487U JP S6447038 U JPS6447038 U JP S6447038U
- Authority
- JP
- Japan
- Prior art keywords
- pattern portion
- conductor pattern
- integrated device
- hybrid integrated
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 239000011889 copper foil Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000009825 accumulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は本考案に係る混成集積装置の要部にお
ける平面図、第２図は同じくその正面部分断面図
、第３図は同じく別の実施例における要部の平面
図、第４図は同じくその正面部分断面図、第５図
は従来の混成集積装置の要部の平面図、第６図は
同じくその正面部分断面図、第７図は従来の混成
集積装置の問題点を説明するための要部の平面図
、第８図は同じくその正面部分断面図である。
１……絶縁基板、２……導体パターン部、３…
…ダイ材、４……半導体チツプ、７……リング状
導体パターン。
Fig. 1 is a plan view of the main part of the hybrid accumulation device according to the present invention, Fig. 2 is a front partial sectional view thereof, Fig. 3 is a plan view of the main part of another embodiment, and Fig. 4 is the same. 5 is a plan view of the main parts of the conventional hybrid accumulation device, FIG. 6 is a partial front sectional view of the same, and FIG. 7 is a diagram for explaining the problems of the conventional hybrid accumulation device. A plan view of the main part, and FIG. 8 is also a partial front sectional view thereof. 1... Insulating substrate, 2... Conductor pattern section, 3...
...Die material, 4...Semiconductor chip, 7...Ring-shaped conductor pattern.
Claims (1)
半導体チツプを接着した混成集積装置において、
前記導体パターン部の周囲に、この導体パターン
部を間隔を隔てて囲むリング状導体パターン部を
形成したことを特徴とする混成集積装置。 (2) 前記リング状導体パターン部は、前記導体
パターン部と電気的に接続させたことを特徴とす
る実用新案登録請求の範囲第１項に記載の混成集
積装置。 (3) 前記リング状導体パターン部は、銅箔でな
ることを特徴とする実用新案登録請求の範囲第１
項に記載の混成集積装置。 (4) 前記リング状導体パターン部は、Ｃｕ―Ｎ
ｉ―ＡｕもしくはＡｇ―Ｐｄでなることを特徴と
する実用新案登録請求の範囲第１項または第２項
に記載の混成集積装置。[Scope of claims for utility model registration] (1) In a hybrid integrated device in which a semiconductor chip is bonded to a conductive pattern portion formed on an insulating substrate,
A hybrid integrated device characterized in that a ring-shaped conductor pattern portion is formed around the conductor pattern portion to surround the conductor pattern portion at intervals. (2) The hybrid integrated device according to claim 1, wherein the ring-shaped conductor pattern portion is electrically connected to the conductor pattern portion. (3) Utility model registration claim 1, characterized in that the ring-shaped conductor pattern portion is made of copper foil.
The hybrid integrated device described in Section 1. (4) The ring-shaped conductor pattern portion is made of Cu—N
The hybrid integrated device according to claim 1 or 2, characterized in that it is made of i-Au or Ag-Pd.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14145487U JPS6447038U (en) | 1987-09-16 | 1987-09-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14145487U JPS6447038U (en) | 1987-09-16 | 1987-09-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6447038U true JPS6447038U (en) | 1989-03-23 |
Family
ID=31406527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14145487U Pending JPS6447038U (en) | 1987-09-16 | 1987-09-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6447038U (en) |
-
1987
- 1987-09-16 JP JP14145487U patent/JPS6447038U/ja active Pending