JPS6281739A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS6281739A JPS6281739A JP60222057A JP22205785A JPS6281739A JP S6281739 A JPS6281739 A JP S6281739A JP 60222057 A JP60222057 A JP 60222057A JP 22205785 A JP22205785 A JP 22205785A JP S6281739 A JPS6281739 A JP S6281739A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- carrier
- substrate
- composite structure
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＩＣを絶縁基盤に一体に担持させ、該ＩＣのリ
ードを絶縁基盤の外方へ突出させて成るＩＣパッケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an IC package in which an IC is integrally supported on an insulating substrate, and the leads of the IC protrude outside the insulating substrate.
従来技術とその問題点
従来の上記リード突出形のＩＣパッケージは絶縁基盤と
してセラミックを用い、該セラミック基盤に配線パター
ンを形成しておき、リードを同基盤に穿けた孔に単ピン
毎植付けて配線パターンの一端と接続し、配線パターン
の他端をＩＣと接続し、１−記配線パターンを施した面
へ別のセラミック板を張り合せ隠蔽するという構成を採
るのが通例であったが、製造工数が多く、リードと配線
パターン間、配線パターンとＩＣ間の夫々において訓常
に精緻な接続作業を要求され、加えてリードの植込に手
間を要し、セラミックを使用することもあって製造単価
が非常に高価なものとなる。又高度な製造技術が要求さ
れ生産性も悪い。加えて接続点が多く、不良率が高い等
の問題もある。Conventional technology and its problems The conventional IC package with the above lead protrusion uses ceramic as an insulating base, a wiring pattern is formed on the ceramic base, and the leads are wired by planting single pins into holes drilled in the base. It was customary to connect one end of the wiring pattern, connect the other end of the wiring pattern to the IC, and cover it by pasting another ceramic plate on the surface on which the wiring pattern was applied. It requires a lot of man-hours, requires precise connection work between the leads and the wiring pattern, and between the wiring pattern and the IC.In addition, it takes time to implant the leads, and because ceramic is used, the manufacturing cost is low. becomes very expensive. Moreover, it requires advanced manufacturing technology and has poor productivity. In addition, there are problems such as a large number of connection points and a high failure rate.
−発明の目的
本発明は上記ＩＣパッケージの大＋［Ｊなローコスト化
、量産化を達成すると共に需要増進を意図して提供され
たものであって、ＩＣ器体たる絶縁基盤を合成樹脂の一
体成形構造としつつ、該一体成形基盤内へのリード組込
が容易且つ精度高く行えるようにし、同基盤内線路形成
、リードとＩＣの接続機構を著しく簡素化したＩＣパッ
ケージを提供するものである。-Purpose of the Invention The present invention was provided with the intention of achieving low cost and mass production of the above-mentioned IC package, as well as increasing demand, in which the insulating base, which is the IC body, is integrated with synthetic resin. The present invention provides an IC package which has a molded structure, allows easy and highly accurate integration of leads into the integrally molded base, and greatly simplifies line formation within the base and a connection mechanism between the leads and the IC.
発明の構成
本発明は上記目的を達成するため、以下の実施例にて詳
述するように、ＩＣ器体たる絶縁基盤を合成樹脂成形基
盤にて形成する一方、複数のリードを整列状態で保有せ
るリード担体を形成し、該リード担体をＩＣパッケージ
全体のリードパターンを有する単一担体とするか、又は
部分に分割された複数単位の担体とし、これを上記合成
樹脂成形基盤に一体成形にて複合構造とし、これによっ
てリードの一端部を基盤外へ突出させると共に、上記リ
ード担体をリード他端部においてＩＣ収容室内へ露出さ
せる等して同リード他端を同室内へ露出させＩＣと接続
するように構成したものである。Structure of the Invention In order to achieve the above object, the present invention, as detailed in the following embodiments, forms an insulating base serving as an IC body from a synthetic resin molded base while holding a plurality of leads in an aligned state. The lead carrier is formed into a single carrier having the lead pattern of the entire IC package, or it is made into a plurality of units divided into parts, and this is integrally molded on the synthetic resin molded base. A composite structure is adopted, whereby one end of the lead protrudes outside the base, and the lead carrier is exposed at the other end of the lead into the IC housing chamber, thereby exposing the other end of the lead into the same chamber and connecting it to the IC. It is configured as follows.
発明の実施例 以下本発明の実施例を図面に基いて説明する。Examples of the invention Embodiments of the present invention will be described below based on the drawings.
各図においてｌはＩＣ器体たる基盤を示す。該２Ｓ：盤
１は合成樹脂にて一体成形構造とし、その上面中央部に
ＩＣ収容室２を該一体成形において画成する。In each figure, l indicates a board which is an IC body. 2S: The board 1 is integrally molded from synthetic resin, and an IC storage chamber 2 is defined in the center of its upper surface by the integral molding.
他方３はリード担体を示す。該リード担体３は複数のり
一ド４を所定ピッチで整列して担持する。On the other hand, 3 indicates a lead carrier. The lead carrier 3 carries a plurality of glues 4 arranged at a predetermined pitch.
該リード４は金属帯板材より打抜形成し、担体３は絶縁
物より形成する。The leads 4 are formed by punching from a metal strip material, and the carrier 3 is formed from an insulating material.
該リード４を担体３に担持させる手段として第６図乃至
第８図は担体３の表面にリード４を露出状ｊｇ５で接着
する実施例を示す、リード４は担体３表面に接着しつつ
、一端を担体３の一側方へ延出させ、該延出部を第７図
に仮想線で示す平条片の状態から］形に曲げ形成する。As means for supporting the lead 4 on the carrier 3, FIGS. 6 to 8 show an embodiment in which the lead 4 is bonded to the surface of the carrier 3 in an exposed state jg5.The lead 4 is bonded to the surface of the carrier 3 while one end is is extended to one side of the carrier 3, and the extended portion is bent into the shape of a flat strip shown in phantom lines in FIG.
上記リード４は第７図、第８図に示すように上記の如く
露出状態にして同担体３の上面と下面に取り付け、一方
で外側の列のリード群を、他方で内側の列のリード群を
構成する。As shown in FIGS. 7 and 8, the leads 4 are attached to the upper and lower surfaces of the carrier 3 in an exposed state as described above, with the outer row of leads on one side and the inner row of leads on the other hand. Configure.
実施に応じ第８図に示すように上記リード４を担体３の
上面又は下面の一方のみに配することができる。Depending on the implementation, the leads 4 can be arranged only on either the upper surface or the lower surface of the carrier 3, as shown in FIG.
」二記リード一端の］形曲げ片を外部接続端子４ｂとし
、他端をＩＣ接続端子４ａとする。ＩＣ接続端子４ａは
担体３の表面に配置するか、又は担体３の他側面より突
出する。2. The bent piece at one end of the lead is used as an external connection terminal 4b, and the other end is used as an IC connection terminal 4a. The IC connection terminal 4a is arranged on the surface of the carrier 3 or protrudes from the other side of the carrier 3.
又上記リード４を担体３に担持させる他側として第９図
乃至第１１図に示すように、該リード４を担体３に貫通
させ一体構造とすることができる。該貫通構造は担体３
の成形に際し、リード４をインサート成形によって得ら
れる。又は担体３に予めリード植付孔又は溝を列穿して
おき、リード４を圧入することによって貫装形のリード
担体を構成できる。前記表面露出形担体と同様、上記リ
ード４を上下二段に貫装しその一方で外側の列のリード
群を、他方で内側の列のリード群を夫々構成する。第１
０図Ａ、Ｂ図に示すようにリード４はその一端を担体３
の一側面より突出させ、他端を同他側面より延出して］
形曲げ片を外部接続端子４ｂとし、上記突出端をＩＣ接
続端子４ａとする。Further, as the other side on which the lead 4 is carried by the carrier 3, the lead 4 can be passed through the carrier 3 to form an integral structure, as shown in FIGS. 9 to 11. The penetrating structure is the carrier 3
When molding, the leads 4 are obtained by insert molding. Alternatively, a penetrating lead carrier can be constructed by previously drilling lead planting holes or grooves in the carrier 3 and press-fitting the leads 4 therein. Similar to the surface-exposed carrier, the leads 4 are passed through the carrier in two stages, upper and lower, one of which constitutes an outer row of lead groups, and the other one of which constitutes an inner row of lead groups. 1st
As shown in Figures A and B, the lead 4 has one end attached to the carrier 3.
[with the other end extending from the same side]
The bent piece is used as an external connection terminal 4b, and the protruding end is used as an IC connection terminal 4a.
上記の如くして形成されたり一ド担体３を合成樹脂成形
基盤１の一体成形に際しインサート成形して複合構造と
する。The single support 3 formed as described above is insert molded when integrally molding the synthetic resin molded base 1 to form a composite structure.
第１図乃至第４図は前記表面露出形のリード担体３を上
記成形によって鋳込み複合構造とした場合を、第５図は
前記貫装形のリード担体３を上記成形によって複合構造
とした場合を夫々示す。FIGS. 1 to 4 show the case where the surface-exposed lead carrier 3 is made into a cast composite structure by the above molding, and FIG. 5 shows the case where the penetrating lead carrier 3 is made into a composite structure by the above molding. Show each.
」−記複合構造において第２図、第５図に示すように上
記リード４の一端（外部接続端子４ｂ）を合成樹脂成形
基ＩＭ１の外方へ突出させると共に、他端（ＩＣ接続端
子４ａ）を前記基盤上面に画成したＩＣ収容室２に露出
させる。同図に示すようにリード担体３の側端をＩＣ収
容室２内に露出させることによって上記ＩＣ接続端子４
ａの露出状態を得る。In the composite structure described above, as shown in FIGS. 2 and 5, one end (external connection terminal 4b) of the lead 4 is made to protrude outward from the synthetic resin molded base IM1, and the other end (IC connection terminal 4a) is exposed to the IC storage chamber 2 defined on the upper surface of the substrate. As shown in the figure, by exposing the side ends of the lead carrier 3 into the IC housing chamber 2, the IC connection terminals 4 are
Obtain the exposure state of a.
斯くしてＩＣ５を第３図に示すようにＩＣ収容室２内に
収容し、上記露出状態にあるＩＣ接続端子４ａと該ＩＣ
５とを接続する。同図は導線６によって接続した例を示
す。In this way, the IC 5 is housed in the IC storage chamber 2 as shown in FIG. 3, and the exposed IC connection terminal 4a and the IC
Connect with 5. The figure shows an example in which a conductor 6 is used for connection.
該リード４へ接続したＩＣ５を保有する収容室２は苫で
密閉するか、又は第４図に示すように流動合成樹脂を充
填し封止する。７は該封止体を示す。The housing chamber 2 holding the IC 5 connected to the lead 4 is sealed with a sealant or filled with fluid synthetic resin as shown in FIG. 4. 7 indicates the sealed body.
実施に応じ上記ＩＣ収容室２の底面には基盤１と一体に
ＩＣの座板８を設け、該座板８上にＩＣ５を載せ上記接
続を行う。該ＩＣ座板８は金属板又はセラミック板にて
形成する。ＩＣ５と座板８とは接着し固定しても良い。Depending on the implementation, an IC seat plate 8 is provided on the bottom surface of the IC housing chamber 2 integrally with the base plate 1, and the IC 5 is placed on the seat plate 8 to perform the above connection. The IC seat plate 8 is formed of a metal plate or a ceramic plate. The IC 5 and the seat plate 8 may be bonded and fixed.
上記リード担体３は第６図に示すようにＩＣパー、ケー
ジ全体のリードパターンを有する単一担体とするか、又
は第９図に示すように部分に分割された複数単位の担体
とし、これを合成樹脂成形基盤１に一体成形して複合構
造とする。第９図は四方向のリード群を四単位に分離し
た担体３に担持させ、各単位を基盤ｌ内で一体とした場
合を示す。第６図に示すように単一担体とする場合には
方形枠体形とする。単一担体とする場合にも、複数単位
の担体とする場合にも前記リード露出形、或はリード貫
挿形とすることができる。The lead carrier 3 may be a single carrier having a lead pattern of the entire IC par or cage as shown in FIG. 6, or it may be a carrier divided into multiple units as shown in FIG. It is integrally molded onto a synthetic resin molded base 1 to form a composite structure. FIG. 9 shows a case where lead groups in four directions are supported on a carrier 3 separated into four units, and each unit is integrated within a base l. As shown in FIG. 6, when a single carrier is used, it has a rectangular frame shape. Whether it is a single carrier or a plurality of carriers, the above-mentioned lead-exposed type or lead-through type can be used.
発明の効果
本発明は以上説明したように、ＩＣ器体たる絶縁基盤を
合成樹脂の一体成形基盤としつつ、複数のリードを整列
状態で保有するり一ド担体を上記合成樹脂成形基盤に一
体成形にて複合構造としたので、同基盤に対するリード
組込及び定ピツチ配列が極めて容易に行え、該複合構造
化によってリード一端を上記基盤外へ突出させ、同他端
を同基盤のＩＣ収容室内へ露出させＩＣと接続する構成
としたので、ＩＣとリードの接続点を最小限にできると
共に、リードとＩＣの接続及び基盤内線路形成を著しく
簡素化する長所がある。Effects of the Invention As explained above, the present invention uses an insulating substrate, which is an IC device body, as an integrally molded synthetic resin substrate, and a linear carrier holding a plurality of leads in an aligned state is integrally molded on the synthetic resin molded substrate. Since it has a composite structure, it is extremely easy to incorporate the leads into the same board and arrange them at a fixed pitch.The composite structure allows one end of the lead to protrude outside the board, and the other end to enter the IC storage chamber of the board. Since it is configured to be exposed and connected to the IC, it has the advantage that the number of connection points between the IC and the lead can be minimized, and the connection between the lead and the IC and the formation of a line in the board can be significantly simplified.
−Ｉ―記によって、ＩＣパッケージの量産化を助長し、
ローコスト化を達成でき、需要に応えることができる。-I- will encourage mass production of IC packages,
It is possible to achieve low cost and meet demand.
第１図は本発明の実施例を示すＩＣパッケージを構成す
る合成樹脂成形基盤斜視図、第２図は同断面図、第３図
はＩＣを組込せる同基盤断面図。
第４図はＩＣを封止せる同基盤断面図、第５図は他側を
示す合成樹脂成形基盤断面図、第６図は単一担体とした
ＩＣ担体平面図、第７図は両面にＩＣを担持せる露出形
リード担体断面図、第８図は片面にＩＣを担持せる露出
形リード担体断面図、第９図は複数単位に分離したＩＣ
担体平面図、第１Ｏ図Ａ図はリードを二段に貫装した貫
装形り一ド１１体をリード折曲前の状態を以って示す断
面図、回Ｂ図は同リード折曲後の断面図、第１１図は同
リードを一段に貫装した貫装形リード担体断面図である
。
１・・・ＩＣ器体たる合成樹脂成形基盤、２・・・ＩＣ
収容室、３・・・リード担体、４・・・リード、４ａ・
・・ＩＣ接続端子、４ｂ・・・外部接続端子、５・・・
ＩＣ。
特許出願人 山−′ＦｒＬ機工業株式会社第１図
第２図
区 機■
味
の
区 区
〇 −
啼１１
味 蛙FIG. 1 is a perspective view of a synthetic resin molded substrate constituting an IC package showing an embodiment of the present invention, FIG. 2 is a sectional view of the same, and FIG. 3 is a sectional view of the same substrate into which an IC can be incorporated. Fig. 4 is a cross-sectional view of the same substrate that seals the IC, Fig. 5 is a cross-sectional view of the synthetic resin molded substrate showing the other side, Fig. 6 is a plan view of the IC carrier as a single carrier, and Fig. 7 is a cross-sectional view of the same substrate that seals the IC. 8 is a sectional view of an exposed lead carrier that can support an IC on one side, and FIG. 9 is a sectional view of an exposed lead carrier that can support an IC on one side.
Planar view of the carrier, Figure 1A is a sectional view showing the 11 pieces of the lead-through structure with leads inserted in two stages before the lead is bent, and Figure B is the same after the lead is bent. FIG. 11 is a sectional view of a penetrating lead carrier in which the leads are inserted in one step. 1...Synthetic resin molded base serving as an IC body, 2...IC
Containment chamber, 3... Lead carrier, 4... Lead, 4a.
...IC connection terminal, 4b...external connection terminal, 5...
I.C. Patent Applicant Yama-'FrL Machine Industry Co., Ltd. Figure 1 Figure 2 Ward Machine
Claims (2)
を形成し、該リード担体を合成樹脂成形基盤に一体成形
して複合構造とし、該複合構造において上記リードの一
端を上記合成樹脂成形基盤の外方へ突出させると共に、
他端を同基盤の上面に画成せるＩＣ収容室に露出させＩ
Ｃと接続する構成としたことを特徴とするＩＣパッケー
ジ。(1) A lead carrier having a plurality of leads at a predetermined pitch is formed, the lead carrier is integrally molded on a synthetic resin molded base to form a composite structure, and in the composite structure, one end of the lead is attached to the synthetic resin molded base. Along with protruding outward,
The other end is exposed to the IC storage chamber defined on the top surface of the board.
An IC package characterized in that it is configured to be connected to a C.
する特許請求の範囲第１項記載の発明。(2) The invention according to claim 1, wherein the lead carrier is composed of a plurality of carriers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60222057A JPH069223B2 (en) | 1985-10-05 | 1985-10-05 | IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60222057A JPH069223B2 (en) | 1985-10-05 | 1985-10-05 | IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6281739A true JPS6281739A (en) | 1987-04-15 |
| JPH069223B2 JPH069223B2 (en) | 1994-02-02 |
Family
ID=16776424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60222057A Expired - Lifetime JPH069223B2 (en) | 1985-10-05 | 1985-10-05 | IC package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH069223B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411356A (en) * | 1987-07-06 | 1989-01-13 | Sony Corp | Hollow package for semiconductor device |
| US5023700A (en) * | 1988-06-17 | 1991-06-11 | Ngk Insulators, Ltd. | Minutely patterned structure |
| US5133433A (en) * | 1989-12-26 | 1992-07-28 | Nihon Plast Co., Ltd. | Rotary damper |
| US5142738A (en) * | 1990-07-24 | 1992-09-01 | Nhk Spring Co., Ltd. | Hinge device |
| WO1995024733A1 (en) * | 1994-03-11 | 1995-09-14 | The Panda Project | Prefabricated semiconductor chip carrier |
| EP0752720A3 (en) * | 1995-07-07 | 1998-06-03 | Mitsubishi Denki Kabushiki Kaisha | Lead for semiconductor device |
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115339A (en) * | 1979-02-26 | 1980-09-05 | Fujitsu Ltd | Ic stem |
| JPS57115254U (en) * | 1981-01-10 | 1982-07-16 | ||
| JPS5856446U (en) * | 1981-10-12 | 1983-04-16 | 日本電気株式会社 | Resin-encapsulated semiconductor device |
| JPS58155851U (en) * | 1982-04-14 | 1983-10-18 | 日本電気株式会社 | Mold type semiconductor device |
| JPS5941860A (en) * | 1982-09-01 | 1984-03-08 | Nec Corp | Manufacture of case for semiconductor device |
-
1985
- 1985-10-05 JP JP60222057A patent/JPH069223B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115339A (en) * | 1979-02-26 | 1980-09-05 | Fujitsu Ltd | Ic stem |
| JPS57115254U (en) * | 1981-01-10 | 1982-07-16 | ||
| JPS5856446U (en) * | 1981-10-12 | 1983-04-16 | 日本電気株式会社 | Resin-encapsulated semiconductor device |
| JPS58155851U (en) * | 1982-04-14 | 1983-10-18 | 日本電気株式会社 | Mold type semiconductor device |
| JPS5941860A (en) * | 1982-09-01 | 1984-03-08 | Nec Corp | Manufacture of case for semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411356A (en) * | 1987-07-06 | 1989-01-13 | Sony Corp | Hollow package for semiconductor device |
| US5023700A (en) * | 1988-06-17 | 1991-06-11 | Ngk Insulators, Ltd. | Minutely patterned structure |
| US5100498A (en) * | 1988-06-17 | 1992-03-31 | Ngk Insulators, Ltd. | Method of producing a minutely patterned structure |
| US5133433A (en) * | 1989-12-26 | 1992-07-28 | Nihon Plast Co., Ltd. | Rotary damper |
| US5142738A (en) * | 1990-07-24 | 1992-09-01 | Nhk Spring Co., Ltd. | Hinge device |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
| US5819403A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Method of manufacturing a semiconductor chip carrier |
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| WO1995024733A1 (en) * | 1994-03-11 | 1995-09-14 | The Panda Project | Prefabricated semiconductor chip carrier |
| US6339191B1 (en) | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US6828511B2 (en) | 1994-03-11 | 2004-12-07 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US6977432B2 (en) | 1994-03-11 | 2005-12-20 | Quantum Leap Packaging, Inc. | Prefabricated semiconductor chip carrier |
| EP0752720A3 (en) * | 1995-07-07 | 1998-06-03 | Mitsubishi Denki Kabushiki Kaisha | Lead for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH069223B2 (en) | 1994-02-02 |
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