JPS6280449U - - Google Patents
Info
- Publication number
- JPS6280449U JPS6280449U JP17038285U JP17038285U JPS6280449U JP S6280449 U JPS6280449 U JP S6280449U JP 17038285 U JP17038285 U JP 17038285U JP 17038285 U JP17038285 U JP 17038285U JP S6280449 U JPS6280449 U JP S6280449U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- flop
- flip
- modulation circuit
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図は本考案の実施例の構成図、第２図は本
考案の動作説明図、第３図は従来技術の構成図、
第４図は従来技術の動作説明図である。
１……セレクタ、２……カウンタ、３……第１
フリツプフロツプ、４……フイルタ、５……固定
発振器、６……第２フリツプフロツプ。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the present invention, and Fig. 3 is a block diagram of a conventional technique.
FIG. 4 is an explanatory diagram of the operation of the prior art. 1... Selector, 2... Counter, 3... First
Flip-flop, 4...filter, 5...fixed oscillator, 6...second flip-flop.
Claims (1)
力しこれを予め設定した周波数でカウンタに入力
せしめ、該カウンタが分周比を変えることにより
固定発振器の周波数を分周出力し、これをフリツ
プフロツプを経由させ所定のキヤリアを復るＦＳ
Ｋ変調回路において、 上記固定発振器の発振周波数を高めると共に、
上記フリツプフロツプの前段に上記分周出力を保
持するためのフリツプフロツプを付加し、 上記と同じキヤリアを得るようにしたことを特
徴とするＦＳＫ変調回路。[Claims for Utility Model Registration] A mark or space of a modulated wave is input to a selector and inputted to a counter at a preset frequency, and the counter changes the frequency division ratio to divide and output the frequency of a fixed oscillator. The FS returns this to a predetermined carrier via a flip-flop.
In the K modulation circuit, while increasing the oscillation frequency of the fixed oscillator,
An FSK modulation circuit characterized in that a flip-flop for holding the frequency-divided output is added to the front stage of the flip-flop to obtain the same carrier as the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17038285U JPS6280449U (en) | 1985-11-07 | 1985-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17038285U JPS6280449U (en) | 1985-11-07 | 1985-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6280449U true JPS6280449U (en) | 1987-05-22 |
Family
ID=31105061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17038285U Pending JPS6280449U (en) | 1985-11-07 | 1985-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6280449U (en) |
-
1985
- 1985-11-07 JP JP17038285U patent/JPS6280449U/ja active Pending
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