JPS627582B2 - - Google Patents
Info
- Publication number
- JPS627582B2 JPS627582B2 JP56029525A JP2952581A JPS627582B2 JP S627582 B2 JPS627582 B2 JP S627582B2 JP 56029525 A JP56029525 A JP 56029525A JP 2952581 A JP2952581 A JP 2952581A JP S627582 B2 JPS627582 B2 JP S627582B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- microprocessor
- under test
- control circuit
- device under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004458 analytical method Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 238000003745 diagnosis Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims 1
- 101100328887 Caenorhabditis elegans col-34 gene Proteins 0.000 description 4
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 description 3
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000002405 diagnostic procedure Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】
本発明は、マイクロプロセツサ及びRAMや
ROM等のメモリを有するマイクロプロセツサ装
置の故障診断方式に関するものである。[Detailed Description of the Invention] The present invention provides a microprocessor and a RAM.
This invention relates to a fault diagnosis method for a microprocessor device having a memory such as ROM.
各種のデータ処理システムにおいて、主処理装
置や主記憶装置と共通バスラインを通して接続さ
れ、入出力装置の制御を司どる入出力制御装置
に、マイクロプロセツサ装置を使用することが多
くなつてきた。従来、この様なマイクロプロセツ
サ装置の故障を診断・解析する場合、被試験マイ
クロプロセツサ装置のマイクロプロセツサおよび
メモリを、一括して同様の構成をとる試験用マイ
クロプロセツサ装置と置換して故障の診断・解析
を行う置換方式、あるいは被試験装置内のマイク
ロプロセツサとメモリを接続しているバスライン
を該被試験装置から延長して外部のメモリを接続
し、故障の診断・解析を行う外部メモリ方式が用
いられている。しかし、置換方式では、被試験装
置のマイクロプロセツサおよびメモリが一括して
置換できる構造になつていなければならず、適用
範囲に制限がある。又、外部メモリ方式では、故
障解析用の情報が確実かつ多量に収集できず、正
確な解析は困難である。例えば被試験装置のマイ
クロプロセツサや、マイクロプログラムを書き込
んだROMが故障した場合は、正確に故障解析情
報を主処理装置に転送することさえ困難である。 In various data processing systems, microprocessor devices are increasingly being used as input/output control devices that are connected to main processing units and main storage devices through a common bus line and control input/output devices. Conventionally, when diagnosing and analyzing failures in such microprocessor devices, the microprocessor and memory of the microprocessor device under test are replaced all at once with a test microprocessor device with a similar configuration. A replacement method for diagnosing and analyzing failures, or extending the bus line that connects the microprocessor and memory in the device under test from the device under test to connect external memory and diagnosing and analyzing failures. An external memory method is used. However, in the replacement method, the microprocessor and memory of the device under test must be constructed so that they can be replaced all at once, and the scope of application is limited. Furthermore, with the external memory method, it is not possible to reliably collect a large amount of information for failure analysis, making accurate analysis difficult. For example, if the microprocessor of the device under test or the ROM in which the microprogram is written fails, it is difficult to accurately transfer failure analysis information to the main processing unit.
本発明の目的とするところは上述の如き従来の
問題点を除去し、マイクロプロセツサ装置のきめ
こまかな故障解析を可能にした診断方式を提供す
ることにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a diagnostic method that eliminates the above-mentioned conventional problems and enables detailed failure analysis of microprocessor devices.
しかして、本発明の特徴とするところは、マイ
クロプロセツサ内蔵の被試験装置とほゞ同一のハ
ードウエア構造を有する試験装置を該被試験装置
に接続し、被試験装置の各動作ブロツクと試験装
置の各動作ブロツクとを各種組み合せて１つのマ
イクロプロセツサ装置として機能せしめ、これに
中央処理装置からのテストプログラムを実行さ
せ、その解析結果を中央処理装置へ送り、被試験
装置の故障解析を行うものである。 Therefore, the feature of the present invention is that a test device having almost the same hardware structure as a device under test with a built-in microprocessor is connected to the device under test, and each operational block of the device under test is connected to the device under test. The various operating blocks of the device are combined to function as one microprocessor device, which executes the test program from the central processing unit, sends the analysis results to the central processing unit, and performs failure analysis of the device under test. It is something to do.
以下、本発明の一実施例につき図面を用いて詳
細に説明する。 Hereinafter, one embodiment of the present invention will be described in detail using the drawings.
図は本発明の一実施例のシステム構成図で、中
央処理装置１３や主記憶装置１４と共通バスライ
ン１５を通して入出力制御装置１０，１１，１２
が接続されている。入出力制御装置１０はマイク
ロプロセツサ１６、ランダムアクセスメモリ
（RAM）１７、リードオンリーメモリ（ROM）
１８、中央処理装置側インタフエース回路１９、
入出力装置側インタフエース回路２０及び制御回
路２２からなり、このうち、制御回路２２以外は
全て装置内の共通バスライン２１に接続されてい
る。制御回路２２は後述するように、試験装置１
の指示に基づいてプロセツサ１６、RAM１７、
ROM１８と共通バスライン２１との接続・切離
しを制御するものである。入出力制御装置１１，
１２の構成も該入出力制御装置１０と全く同じで
ある。一方、試験装置１はマイクロプロセツサ
２、RAM３，４、操作部５、制御回路７及び外
部記憶装置８からなり、このうち、制御回路７以
外は全て装置内の共通バスライン６に接続されて
いる。制御回路７は操作部５からの接続／切離し
指示によりプロセツサ２、RAM３，４と共通バ
スライン６との接続・切離しを制御すると共に、
被試験装置側の制御回路２２に接続／切離し情報
を伝える働きをする。 The figure is a system configuration diagram of an embodiment of the present invention, in which input/output control devices 10, 11, 12 are connected to a central processing unit 13, a main storage device 14, and a common bus line 15.
is connected. The input/output control device 10 includes a microprocessor 16, a random access memory (RAM) 17, and a read only memory (ROM).
18, central processing unit side interface circuit 19,
It consists of an input/output device side interface circuit 20 and a control circuit 22, of which all except the control circuit 22 are connected to a common bus line 21 within the device. The control circuit 22 is connected to the test apparatus 1 as described later.
processor 16, RAM 17,
It controls connection and disconnection between the ROM 18 and the common bus line 21. input/output control device 11,
The configuration of 12 is also exactly the same as that of the input/output control device 10. On the other hand, the test device 1 consists of a microprocessor 2, RAMs 3 and 4, an operation section 5, a control circuit 7, and an external storage device 8. Of these, all except the control circuit 7 are connected to a common bus line 6 within the device. There is. The control circuit 7 controls the connection/disconnection of the processor 2, RAMs 3, 4, and the common bus line 6 based on connection/disconnection instructions from the operation unit 5, and
It functions to convey connection/disconnection information to the control circuit 22 on the device under test side.
動作は次の通りである。中央処理装置１３から
各入出力制御装置１０，１１，１２にテストプロ
グラムを送り、その結果、例えば入出力制御装置
１０に故障のあることを発見すると、オペレータ
は試験装置１を入出力制御装置（以下、被試験装
置という）１０に接続する。具体的には、試験装
置１と被試験装置１０の装置内共通バスライン
６，２１を接続し、又、両装置の制御回路７，２
２をインタフエース信号線９を通して接続する。
試験装置１の外部記憶装置８には、予め被試験装
置１０のRAM１７、ROM１８と同一の情報が入
つており、操作部５を操作して、RAM３にRAM
１７と同一の情報を、RAM４にROM１８と同一
の情報をそれぞれロードする。次に再び操作部５
を操作して、接続／切離し情報を制御回路７、信
号線９を通して被試験装置１０の制御回路２２に
送り、マイクロプロセツサ１６、RAM１７、
ROM１８の動作を停止させ、これら３つのブロ
ツクを共通バスライン２１から切離す。このよう
にして、まずマイクロプロセツサ２、RAM３，
４の組合せにより、中央処理装置１３からテスト
プログラムを実行させ、共通バスライン１５，２
１、インタフエース回路１９、及び試験装置１の
正常動作を確認する。 The operation is as follows. When a test program is sent from the central processing unit 13 to each of the input/output control devices 10, 11, and 12 and, as a result, it is discovered that, for example, there is a failure in the input/output control device 10, the operator transfers the test device 1 to the input/output control device ( (hereinafter referred to as the device under test) 10. Specifically, the internal common bus lines 6 and 21 of the test device 1 and the device under test 10 are connected, and the control circuits 7 and 2 of both devices are connected.
2 through the interface signal line 9.
The external storage device 8 of the test device 1 contains the same information as the RAM 17 and ROM 18 of the device under test 10 in advance, and by operating the operation unit 5, the RAM 3 is loaded with the same information.
The same information as 17 and the same information as ROM 18 are loaded into RAM 4, respectively. Next, operate section 5 again.
The connection/disconnection information is sent to the control circuit 22 of the device under test 10 through the control circuit 7 and signal line 9, and the microprocessor 16, RAM 17,
The operation of the ROM 18 is stopped and these three blocks are disconnected from the common bus line 21. In this way, first, microprocessor 2, RAM 3,
By the combination of 4, the test program is executed from the central processing unit 13, and the common bus lines 15, 2
1. Check the normal operation of the interface circuit 19 and the test device 1.
次に操作部５を操作して次の３つの組合せを作
り、それぞれテストプログラムを実行する。 Next, operate the operation unit 5 to create the following three combinations, and execute a test program for each.
(a) マイクロプロセツサ２、RAM３、ROM１
８、
(b) マイクロプロセツサ２、RAM１７、RAM
４、
(c) マイクロプロセツサ１６、RAM３、RAM
４、
これらの組合せで故障のあることが分つた場
合、(a)ではROM１８の不良、(b)ではRAM１７の
不良、(c)ではマイクロプロセツサ１６の不良が発
見される。(a) Microprocessor 2, RAM3, ROM1
8, (b) Microprocessor 2, RAM17, RAM
4. (c) Microprocessor 16, RAM3, RAM
4. If it is found that there is a failure in these combinations, a failure in the ROM 18 is found in (a), a failure in the RAM 17 is found in (b), and a failure in the microprocessor 16 is found in (c).
上記(a)、(b)、(c)の組合せが全て正常と判定され
た場合には、更に操作部５を操作し、次の３つの
組合せでテストプログラムを実行する。 If all of the above combinations (a), (b), and (c) are determined to be normal, the operation unit 5 is further operated to execute the test program using the following three combinations.
(d) マイクロプロセツサ１６、RAM１７、RAM
４、
(e) マイクロプロセツサ１６、RAM３、ROM１
８、
(f) マイクロプロセツサ２、RAM１７、ROM１
８、
これらの組合せで故障のあることが分つた場
合、(d)ではマイクロプロセツサ１６とRAM１７
の両方に関係する複合不良、(e)ではマイクロプロ
セツサ１６とROM１８間の複合不良、(f)では
ROM１７とROM１８間の複合不良と判定され
る。なお、これらの組合せが全て正常と判定され
た場合は、マイクロプロセツサ１６、RAM１
７、ROM１８間の複合的な不良が発生している
と見做すことができる。(d) Microprocessor 16, RAM 17, RAM
4. (e) Microprocessor 16, RAM3, ROM1
8, (f) Microprocessor 2, RAM17, ROM1
8. If it is found that there is a failure in these combinations, in (d) the microprocessor 16 and RAM 17
(e) is a composite failure between the microprocessor 16 and ROM 18, and (f) is a composite failure related to both microprocessor 16 and ROM 18.
It is determined that there is a composite failure between ROM17 and ROM18. Note that if all of these combinations are determined to be normal, the microprocessor 16 and RAM 1
7. It can be assumed that a complex defect has occurred between the ROMs 18.
以上、被試験装置としてマイクロプロセツサを
内蔵した入出力制御装置を例に説明したが、本発
明はこれ以外のマイクロプロセツサ装置の故障の
診断・解析に適用できることは云うまでもない。 Although the above description has been made using an input/output control device with a built-in microprocessor as an example of the device under test, it goes without saying that the present invention can be applied to diagnosis and analysis of failures in other microprocessor devices.
以上の説明から明らかな如く、本発明にあつて
は次のような効果が得られる。 As is clear from the above description, the following effects can be obtained with the present invention.
(1) 故障の発生している被試験装置内の１つある
いは複数のブロツクを、試験装置内の対応する
ブロツクと順次代替えしてテストプログラムを
実行することにより、きめこまかな故障解析が
容易に達成できる。(1) Detailed failure analysis can be easily achieved by sequentially replacing one or more blocks in the equipment under test where a failure has occurred with the corresponding blocks in the test equipment and running the test program. can.
(2) 試験装置内の外部記憶装置に各種マイクロプ
ログラムを内蔵しておくことにより、各種の同
一ハードウエア構造を有するマイクロプロセツ
サ装置の故障解析に対応できる。(2) By storing various microprograms in the external storage device in the test equipment, it is possible to support failure analysis of various microprocessor devices having the same hardware structure.
(3) 試験装置が被試験装置と同一の動作を擬似的
に行うため、中央処理装置からは通常のテスト
プログラムを実行させることができ、試験装置
専用のテストプログラムを必要としない。(3) Since the test equipment simulates the same operation as the equipment under test, a normal test program can be executed from the central processing unit, and there is no need for a test program dedicated to the test equipment.
図は本発明の一実施例の構成図である。
１…試験装置、２，１６…マイクロプロセツ
サ、３，４，１７…RAM、５…操作部、６，１
５，２１…共通バスライン、７，２２…制御回
路、８…外部記憶装置、９…インタフエース信号
線、１０，１１，１２…入出力制御装置（被試験
装置）、１３…中央処理装置、１４…主記憶装
置、１８…ROM、２３…制御回路。
The figure is a configuration diagram of an embodiment of the present invention. 1... Test device, 2, 16... Microprocessor, 3, 4, 17... RAM, 5... Operation unit, 6, 1
5, 21... Common bus line, 7, 22... Control circuit, 8... External storage device, 9... Interface signal line, 10, 11, 12... Input/output control device (device under test), 13... Central processing unit, 14... Main storage device, 18... ROM, 23... Control circuit.
Claims (1)
クセスメモリとリードオンリーメモリの各機能ブ
ロツクがバスラインに共通接続されているマイク
ロプロセツサ装置における任意の一つあるいは複
数の機能ブロツクの故障を診断・解析する方式で
あつて、 前記被試験装置と同様に少なくともマイクロプ
ロセツサとランダムアクセスメモリとリードオン
リーメモリの各機能ブロツクがバスラインに共通
接続されており、更に、これらの機能ブロツクの
バスラインとの接続・切離しを制御する第１制御
回路と、操作部を備えた試験装置を設け、 前記マイクロプロセツサ装置（以下、被試験装
置と呼ぶ）内には、その各機能ブロツクのバスラ
インとの接続・切離しを制御する第２制御回路を
設け、 前記被試験装置のバスラインと前記試験装置の
バスラインとを接続すると共に、前記操作部の指
示に従い、前記第１の制御回路で前記試験装置内
の任意の機能ブロツクのバスラインとの接続・切
離しを行い、且つ、前記第２の制御回路で前記試
験装置とは相補的に前記被試験装置内の任意の機
能ブロツクのバスラインとの接続・切離しを行つ
て、前記試験装置と前記被試験装置とで一つのマ
イクロプロセツサ装置として機能させて、前記被
試験装置の故障箇所を判定することを特徴とする
マイクロプロセツサ装置の故障診断方式。[Claims] 1. Diagnosis of a failure in any one or more functional blocks in a microprocessor device in which at least the microprocessor, random access memory, and read-only memory functional blocks are commonly connected to a bus line.・An analysis method in which at least the microprocessor, random access memory, and read-only memory functional blocks are commonly connected to a bus line, as in the device under test, and the bus lines of these functional blocks are A test device is provided that includes a first control circuit that controls connection and disconnection from the microprocessor device (hereinafter referred to as the device under test), and a test device that includes a first control circuit that controls connection and disconnection from the test device. A second control circuit is provided for controlling connection/disconnection of the device under test, and connects the bus line of the device under test to the bus line of the test device, and performs the test using the first control circuit according to instructions from the operation unit. The second control circuit connects and disconnects any functional block in the device to the bus line, and the second control circuit connects the bus line of any functional block in the device under test in a complementary manner to the test device. A fault diagnosis for a microprocessor device, characterized in that the test device and the device under test are connected and disconnected to make the test device and the device under test function as one microprocessor device, and a fault location in the device under test is determined. method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56029525A JPS57143650A (en) | 1981-03-02 | 1981-03-02 | Diagnostic system for fault of microiprocessor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56029525A JPS57143650A (en) | 1981-03-02 | 1981-03-02 | Diagnostic system for fault of microiprocessor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57143650A JPS57143650A (en) | 1982-09-04 |
| JPS627582B2 true JPS627582B2 (en) | 1987-02-18 |
Family
ID=12278517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56029525A Granted JPS57143650A (en) | 1981-03-02 | 1981-03-02 | Diagnostic system for fault of microiprocessor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57143650A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8602849A (en) * | 1986-11-11 | 1988-06-01 | Philips Nv | DEVICE FOR EMULSING A MICROCONTROLLER, USING A MOTHER MICROCONTROLLER AND A DAUGHTER MICROCONTROLLER, REPRODUCING A DAUGHTER MICROCONTROLLER FOR USE IN SUCH A DEVICE, INTEGRATED USER, INTEGRATED. |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS544036A (en) * | 1977-06-10 | 1979-01-12 | Ando Electric | Microprocessor analyzer via bus switching |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152633U (en) * | 1978-04-17 | 1979-10-24 |
-
1981
- 1981-03-02 JP JP56029525A patent/JPS57143650A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS544036A (en) * | 1977-06-10 | 1979-01-12 | Ando Electric | Microprocessor analyzer via bus switching |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57143650A (en) | 1982-09-04 |
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