JPS6275597U - - Google Patents

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Publication number
JPS6275597U
JPS6275597U JP16377685U JP16377685U JPS6275597U JP S6275597 U JPS6275597 U JP S6275597U JP 16377685 U JP16377685 U JP 16377685U JP 16377685 U JP16377685 U JP 16377685U JP S6275597 U JPS6275597 U JP S6275597U
Authority
JP
Japan
Prior art keywords
alarm
output
circuit
input
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16377685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16377685U priority Critical patent/JPS6275597U/ja
Publication of JPS6275597U publication Critical patent/JPS6275597U/ja
Pending legal-status Critical Current

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  • Alarm Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例回路図。第2図は本考
案実施例動作タイミングチヤート。第3図は従来
例回路図。 1……D型フリツプフロツプ、2……アンドゲ
ート、3……オアゲート、4……分周器、5……
発振器。
FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is an operational timing chart of an embodiment of the present invention. FIG. 3 is a conventional circuit diagram. 1... D-type flip-flop, 2... AND gate, 3... OR gate, 4... Frequency divider, 5...
oscillator.

Claims (1)

【実用新案登録請求の範囲】 通信装置の警報を外部出力する警報解路におい
て、 警報入力がその入力端子に入力されるフリツプ
フロツプ1と、 前記警報入力と前記フリツプフロツプの反転出
力との論理積をとるアンド回路2と、 発振器5と、 前記アンド回路の出力をリセツト端子に入力し
、前記発振器の出力をクロツク入力端子に入力し
、その出力を前記フリツプフロツプのクロツクに
与える分周器4と、 前記フリツプフロツプの出力と前記警報入力と
の論理和をとり警報出力とするオア回路3とを備
えたことを特徴とする警報回路。
[Claims for Utility Model Registration] In an alarm release circuit that outputs an alarm from a communication device to the outside, a flip-flop 1 to which an alarm input is inputted to its input terminal, and the logical product of the alarm input and the inverted output of the flip-flop are calculated. an AND circuit 2; an oscillator 5; a frequency divider 4 that inputs the output of the AND circuit to a reset terminal, inputs the output of the oscillator to a clock input terminal, and applies the output to the clock of the flip-flop; An alarm circuit comprising: an OR circuit 3 which takes the logical sum of the output of the above and the alarm input and outputs the result as an alarm output.
JP16377685U 1985-10-25 1985-10-25 Pending JPS6275597U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16377685U JPS6275597U (en) 1985-10-25 1985-10-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16377685U JPS6275597U (en) 1985-10-25 1985-10-25

Publications (1)

Publication Number Publication Date
JPS6275597U true JPS6275597U (en) 1987-05-14

Family

ID=31092284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16377685U Pending JPS6275597U (en) 1985-10-25 1985-10-25

Country Status (1)

Country Link
JP (1) JPS6275597U (en)

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