JPS6266460U - - Google Patents
Info
- Publication number
- JPS6266460U JPS6266460U JP1986151818U JP15181886U JPS6266460U JP S6266460 U JPS6266460 U JP S6266460U JP 1986151818 U JP1986151818 U JP 1986151818U JP 15181886 U JP15181886 U JP 15181886U JP S6266460 U JPS6266460 U JP S6266460U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- horizontal scanning
- scanning period
- waveform
- binarizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 238000003384 imaging method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Facsimile Scanning Arrangements (AREA)
- Manipulation Of Pulses (AREA)
Description
第1図は被写体の撮像方法の説明図、第2図は
撮像により得られた映像信号およびその2値化信
号の波形図、第3図は被写体における照明が不均
一な場合の被写体を示す図、第4図は第3図に示
す被写体を走査して得られる映像信号の波形図、
第5図はこの考案の一実施例を示すブロツク図、
第6図は第5図の実施例における入力ビデオ信号
と出力される2値信号の各波形を示すタイミング
チヤート、第7図はこの考案の他の実施例を示す
ブロツク図、第8図は第7図の実施例における入
力ビデオ信号と出力される2値信号の各波形を示
すタイミングチヤート、第9図はこの考案の更に
他の実施例を示すブロツク図、である。
符号説明、1……黒色背景板、2……白色台紙
、3……有効画面、4……水平走査方向、5……
ビデオ信号波形、6……サンプルホールド点、7
……調整電圧、8……背景板に対応したビデオ信
号領域、9……台紙に対応したビデオ信号領域、
10……難効画面に対応したビデオ信号領域、1
1……固定しきい値、12……2値化信号波形、
13〜15……走査線、13A〜115A……ビ
デオ信号、16……適切なしきい値、17……光
電変換素子、18……増幅器、19,21……切
換器、20……ピーク値ホールド回路、22……
調整電圧発生回路、23,33……差分器、24
……比較器、25……2値化信号、31……黒レ
ベルサンプルホールド回路、34……調整分圧器
、39……加算器。
Figure 1 is an explanatory diagram of the method of imaging a subject, Figure 2 is a waveform diagram of the video signal obtained by imaging and its binary signal, and Figure 3 is a diagram showing the subject when the illumination on the subject is uneven. , FIG. 4 is a waveform diagram of a video signal obtained by scanning the subject shown in FIG. 3,
FIG. 5 is a block diagram showing an embodiment of this invention.
6 is a timing chart showing each waveform of an input video signal and an output binary signal in the embodiment of FIG. 5, FIG. 7 is a block diagram showing another embodiment of this invention, and FIG. 7 is a timing chart showing each waveform of an input video signal and an output binary signal in the embodiment, and FIG. 9 is a block diagram showing still another embodiment of this invention. Description of symbols, 1...Black background board, 2...White mount, 3...Effective screen, 4...Horizontal scanning direction, 5...
Video signal waveform, 6... Sample hold point, 7
...Adjustment voltage, 8...Video signal area corresponding to the background board, 9...Video signal area corresponding to the mount,
10...Video signal area corresponding to difficult-to-effect screens, 1
1...Fixed threshold value, 12...Binarized signal waveform,
13-15...Scanning line, 13A-115A...Video signal, 16...Appropriate threshold value, 17...Photoelectric conversion element, 18...Amplifier, 19, 21...Switcher, 20...Peak value hold Circuit, 22...
Adjustment voltage generation circuit, 23, 33...Differentiator, 24
... Comparator, 25 ... Binarized signal, 31 ... Black level sample and hold circuit, 34 ... Adjustment voltage divider, 39 ... Adder.
Claims (1)
ベル値を取り込んで少なくとも次の水平走査周期
の間はこれを記憶するホールド手段と、当該水平
走査周期に先立つ前回の走査周期における映像信
号のピークレベル値を前記ホールド手段より取り
出し、これに基づいて当該水平走査周期における
映像信号の2値化のためのしきい値レベルを決定
する手段を具備したことを特徴とする映像信号の
2値化装置。 A hold means captures the peak level value of the video signal for each horizontal scanning period and stores it at least during the next horizontal scanning period; An apparatus for binarizing a video signal, comprising means for determining a threshold level for binarizing the video signal in the horizontal scanning period based on the holding unit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986151818U JPS6266460U (en) | 1986-10-02 | 1986-10-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986151818U JPS6266460U (en) | 1986-10-02 | 1986-10-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6266460U true JPS6266460U (en) | 1987-04-24 |
Family
ID=31069235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986151818U Pending JPS6266460U (en) | 1986-10-02 | 1986-10-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6266460U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299723A (en) * | 1976-02-17 | 1977-08-22 | Sumitomo Electric Ind Ltd | Circuit for converting analogous signals to binary value signals |
JPS5345115A (en) * | 1976-10-06 | 1978-04-22 | Hitachi Denshi Ltd | Binary circuit |
JPS5350943A (en) * | 1976-10-20 | 1978-05-09 | Sumitomo Electric Ind Ltd | Binary circuit for analog signal |
JPS53145525A (en) * | 1977-05-25 | 1978-12-18 | Oki Electric Ind Co Ltd | Optical character reader |
-
1986
- 1986-10-02 JP JP1986151818U patent/JPS6266460U/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299723A (en) * | 1976-02-17 | 1977-08-22 | Sumitomo Electric Ind Ltd | Circuit for converting analogous signals to binary value signals |
JPS5345115A (en) * | 1976-10-06 | 1978-04-22 | Hitachi Denshi Ltd | Binary circuit |
JPS5350943A (en) * | 1976-10-20 | 1978-05-09 | Sumitomo Electric Ind Ltd | Binary circuit for analog signal |
JPS53145525A (en) * | 1977-05-25 | 1978-12-18 | Oki Electric Ind Co Ltd | Optical character reader |
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