JPS6257337A - Data transmission equipment - Google Patents
Data transmission equipmentInfo
- Publication number
- JPS6257337A JPS6257337A JP60197010A JP19701085A JPS6257337A JP S6257337 A JPS6257337 A JP S6257337A JP 60197010 A JP60197010 A JP 60197010A JP 19701085 A JP19701085 A JP 19701085A JP S6257337 A JPS6257337 A JP S6257337A
- Authority
- JP
- Japan
- Prior art keywords
- data
- processor
- data transmission
- signal line
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
- Small-Scale Networks (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はデータ伝送システムにおけるデータ伝送製画に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transmission planning in a data transmission system.
（従来の技術）
従来、データ伝送システム、例えばプロセッサ間ネット
ワークシステムにおいて、データ伝送路で接続されたプ
ロセッサが故障した場合、他プロセツサは通信相手先が
故障していることを知る手段がないため、通信相手先へ
のデータが発生して通信相手先へ送信すると、通信相手
先は故障のため応答は無応答となり、通信手順で定めら
れた再試行が失敗したことにより通信相手先が故障しで
いると認識し、通信相手先の予備プロセッサへデータを
転送していた。(Prior Art) Conventionally, in a data transmission system, for example, an inter-processor network system, when a processor connected via a data transmission path fails, other processors have no means of knowing that the other processor is out of order. When data is generated and sent to the communication partner, there is no response due to the communication partner being out of order. It recognized that there was a processor on the other end of the communication and transferred the data to the backup processor at the other end of the communication.
（発明が解決しようとする問題点）
上述した従来のプロセッサ間ネットワークシステムは、
通信相手先との通信が、通信手順で定められた再試行が
失敗するまで動作しないようになっているので、予備プ
ロセッサへのデータ転送機能が動作するまで長時間かか
るという欠点があり、また、予備プロセッサへのデータ
転送機能を送信元が持たなければならず、送信元の通信
制御が複雑になるという欠点がある。(Problems to be Solved by the Invention) The conventional inter-processor network system described above has the following problems:
Since communication with the communication partner does not operate until the retry specified in the communication procedure fails, there is a drawback that it takes a long time until the data transfer function to the spare processor is activated. This method has the disadvantage that the sender must have a data transfer function to the backup processor, which complicates communication control at the sender.
本発明のデータ伝送装置は、自データ伝送装雪に接続さ
れた処理装置（プロセッサ、端末装置等）および自デー
タ伝送装置と処理装置間のバスの正常／故障の情報を保
持する正常／故障情報保持手段と、正常／故障情報保持
手段が故障の情報を保持している場合にデータ伝送路受
信回路の受信データが転送される予備処理装置のアドレ
ス情報を保持する予備処理装置アドレス情報保持手段と
、正常／故障情報保持手段が故障の情報を保持している
場合に、データ伝送路からの受信データと予備処理装置
アドレス情報保持手段のアドレス情報を入力して予備プ
ロセッサ宛のデータを生成し、データ伝送路送信回路に
出力する予備処理装置宛データ生成手段を備えたことを
特徴とする。The data transmission device of the present invention has normality/failure information that holds information on the normality/failure of the processing device (processor, terminal device, etc.) connected to the own data transmission device and the bus between the own data transmission device and the processing device. holding means; and preprocessing device address information holding means for holding address information of a preprocessing device to which received data of the data transmission path receiving circuit is transferred when the normality/failure information holding means holds failure information. , when the normality/failure information holding means holds failure information, inputting received data from the data transmission path and address information of the preprocessing device address information holding means to generate data addressed to the preprocessor; The present invention is characterized by comprising means for generating data addressed to the preprocessing device that is output to the data transmission path transmission circuit.
このようにデータ伝送装置が自処理装置の故障を検出す
ると、以後故障が解除されるまで、受信データを予備処
理装置へ転送することにより、送信元は通信相手先が故
障していることを全く意識することなく、目的の送信デ
ータを目的地へ送信できる。In this way, when the data transmission device detects a failure in its own processing device, it transfers the received data to the preprocessing device until the failure is cleared, thereby ensuring that the sender has no knowledge that the communication partner is out of order. You can send the desired data to the destination without being aware of it.
次に、本発明の実施例について図面を参照しで説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のデータ伝送装置の一実施例のブロック
図、第２図は第１図のデータ伝送装置で構成されたプロ
セッサ間ネットワークシステムの一実施例のブロック図
である。FIG. 1 is a block diagram of an embodiment of a data transmission device of the present invention, and FIG. 2 is a block diagram of an embodiment of an inter-processor network system configured with the data transmission device of FIG. 1.
このプロセッサ間ネットワークシステムは、データ伝送
装置５〜８と、データ伝送装置５〜８にそれぞれ接続さ
れたプロセッサ１〜４と、これらデータ伝送装置５〜８
を結合する伝送路９かうなる。This inter-processor network system includes data transmission devices 5 to 8, processors 1 to 4 connected to the data transmission devices 5 to 8, respectively, and data transmission devices 5 to 8.
The transmission line 9 that connects the .
本実施例のデータ伝送装置（第２図中のデータ伝送装置
１５を指すものとし、他も同様の構成である）は、他の
データ伝送装置１６〜８から伝送路９を通して送られて
きたデータを信号線９０２により受信し、信号線５１３
上に送出するデータ伝送路受信回路５１２と、データ伝
送路受信回路５１２で受信した他のデータ伝送袋Ｍ６〜
８からのデータを信号線５１３．５１５により入力し、
信号線５１７により自プロセッサであるプロセッサ１へ
送信するプロセッサ送信回路５１６と、信号線５０１に
より自プロセッサであるプロセッサ１からのデータを受
信し、信号線５０２上に送出するプロセッサ受信回路５
１８と、プロセッサ受信回路５１８で受信したプロセッ
サ１からのデータを信号線５０２．５１９により入力し
、信号線９０１、伝送路９を通して他のデータ伝送袋Ｍ
６〜８に送信するデータ伝送路送信回路５０９と、自デ
ータ伝送装置に接続されたプロセッサ１および自データ
伝送装置とプロセッサ１間のバスが正常の場合“０”、
異常（故ＩＩＩ）の場合“１″を保持し、信号線５０４
．５１０に出力するプロセッサ故障表示レジスタ５０３
と、プロセッサ故障表示レジスタ５０３の信号線５１０
が“ｏ″の場合、信号線５１５に、“１”の場合、信号
線５１１に信号線５１３の接続を切換える選択回路５１
４と、ブロセ・ンサ故障表示レジスタ５０３が故ｍ％示
している場合にデータ伝送路受信回路５１２で受信した
データが転送される予備プロセッサのアドレスを保持し
ている予備プロセッサアドレスレジスタ５０５と、プロ
セッサ故障表示レジスタ５０３が故障を示している場合
にデータ伝送路受信回路５１２で受信したデータを信号
線５１１により入力し、データ中の送信先アドレスを予
備プロセッサアドレスレジスタ５０５に保持されている
予備プロセッサのアドレスで置換し、予備プロセッサ宛
のデータを生成し、信号線５０７により出力する予備プ
ロセッサ宛データ生成回路５０６と、プロセッサ故障表
示レジスタ５０３の信号線５０４が“０”の場合、信号
線５０２に、“１”の場合、信号線５０７に信号線５１
８の接続を切換える選択回路５０８から構成されでいる
。The data transmission device of this embodiment (referring to the data transmission device 15 in FIG. 2, and the others have the same configuration) transmits data sent through the transmission path 9 from other data transmission devices 16 to 8. is received by the signal line 902, and the signal line 513
The data transmission path receiving circuit 512 that sends the data to the top and other data transmission bags M6~ received by the data transmission path receiving circuit 512
Input data from 8 through signal lines 513 and 515,
A processor transmitting circuit 516 transmits data to the processor 1, which is the own processor, through a signal line 517, and a processor receiving circuit 5, which receives data from the processor 1, which is the own processor, through the signal line 501, and transmits it onto the signal line 502.
18 and the data from the processor 1 received by the processor receiving circuit 518 are inputted through signal lines 502 and 519, and transmitted to other data transmission bags M through the signal line 901 and the transmission path 9.
6 to 8, the processor 1 connected to the own data transmission device, and the bus between the own data transmission device and the processor 1 are “0”;
In the case of abnormality (late III), it holds “1” and the signal line 504
．． Processor failure indication register 503 output to 510
and the signal line 510 of the processor failure indication register 503.
A selection circuit 51 that switches the connection of the signal line 513 to the signal line 515 when it is "o" and to the signal line 511 when it is "1".
4, a spare processor address register 505 that holds the address of the spare processor to which data received by the data transmission path receiving circuit 512 is transferred when the processor failure indication register 503 indicates m% failure; When the failure indication register 503 indicates a failure, the data received by the data transmission line receiving circuit 512 is input through the signal line 511, and the destination address in the data is sent to the spare processor held in the spare processor address register 505. When the data generation circuit 506 for the backup processor replaces the address with the address, generates data addressed to the backup processor, and outputs it via the signal line 507, and the signal line 504 of the processor failure indication register 503 is "0", the signal line 502 In the case of “1”, the signal line 51 is connected to the signal line 507.
It is composed of a selection circuit 508 that switches the connections of 8.
次に、本実施例の動作を説明する。Next, the operation of this embodiment will be explained.
プロセッサ故障表示レジスタ５０３の信号線５１０゜５
０４がプロセッサ正常を示す“０″であれば、選択回路
５１４により信号線５１３と信号線５１５が接続され、
選択回路５０８により信号線５０２と信号線５１９が接
続される。したがって、信号線９０２を通してデータが
データ伝送路受信回路５１２に受信されると、データ伝
送路受信回路５１２はデータが自局アドレス宛であれば
、信号線５１３へ出力する。Signal line 510°5 of processor failure indication register 503
If 04 is "0" indicating that the processor is normal, the selection circuit 514 connects the signal line 513 and the signal line 515,
The selection circuit 508 connects the signal line 502 and the signal line 519. Therefore, when data is received by the data transmission line receiving circuit 512 through the signal line 902, the data transmission line receiving circuit 512 outputs the data to the signal line 513 if the data is addressed to its own address.
このデータは選択回路５１４を通って信号線５１５へ出
力され、プロセッサ送信回路５１６へ入力し、ざらに信
号線５１７へ出力され、プロセッサ１へ転送される。一
方、信号線５０１を通してプロセッサ１からのデータが
プロセッサ受信回路５１８で受信されると、プロセッサ
受信回路５１８は信号線５０２へ出力する。このデータ
は選択回路５０８を通って信号線５１９へ出力され、デ
ータ伝送路送信回路５０９へ入力し、信号線９０１によ
り他のデータ伝送装置６〜８へ送信される。This data is outputted to a signal line 515 through a selection circuit 514, inputted to a processor transmission circuit 516, roughly outputted to a signal line 517, and transferred to the processor 1. On the other hand, when the processor receiving circuit 518 receives data from the processor 1 through the signal line 501, the processor receiving circuit 518 outputs the data to the signal line 502. This data is outputted to the signal line 519 through the selection circuit 508, inputted to the data transmission line transmission circuit 509, and transmitted to the other data transmission devices 6 to 8 via the signal line 901.
次に、プロセッサ故障表示レジスタ５０３の信号線５０
４．５１０がプロセ・ンサ故障を示す“１″であれば、
選択回路５１４により信号線５１３と信号線５１１が接
続され、選択回路５０８により信号線５０７と信号線５
１８が接続される。したがって、信号線５１３上のデー
タは選択回路５１４を通って信号線５１１へ出力され、
予備プロセッサ宛データ生成回路５０６により、受信デ
ータ中の送信先アドレスが予備プロセッサアドレスレジ
スタ５０５のアドレスで置換され、信号線５０７へ出力
される。この予備プロセッサ宛のデータは、信号線５１
８によりデータ伝送路送信回路５０９へ入力され、さら
にデータ伝送路送信回路５０９から信号線９０１へ出力
される０以上の動作により、プロセッサ］が故障しでい
る場合、受信データは予備ブロセ・ンサヘ転送される。Next, the signal line 50 of the processor failure indication register 503
4. If 510 is “1” indicating processor failure,
The selection circuit 514 connects the signal line 513 and the signal line 511, and the selection circuit 508 connects the signal line 507 and the signal line 5.
18 are connected. Therefore, the data on the signal line 513 is output to the signal line 511 through the selection circuit 514,
The backup processor address data generation circuit 506 replaces the destination address in the received data with the address of the backup processor address register 505 and outputs it to the signal line 507. The data addressed to this spare processor is sent to the signal line 51
8 to the data transmission line transmitting circuit 509, and further output from the data transmission line transmitting circuit 509 to the signal line 901. If the processor is out of order, the received data is transferred to the backup processor. be done.
本発明は、プロセッサ以外の端末装置等を処理装置とし
たデータ伝送システムにも適用できる。The present invention can also be applied to a data transmission system in which a terminal device or the like other than a processor is used as a processing device.
以上説明したように本発明は、データ伝速装置が自プロ
セッサの故障を検出すると、以後故障が解除されるまで
、受信データを予備プロセッサへ転送することにより、
送信元は通信相手先が故障しでいることを全く意識する
ことなく、目的の送信データを目的地へ送信できるとい
う効果がある。As explained above, in the present invention, when the data transmission device detects a failure in its own processor, the received data is transferred to the standby processor until the failure is cleared.
This has the effect that the sender can send the intended transmission data to the destination without being aware that the communication partner is out of order.
第１図は本発明のデータ伝送装置の一実施例のブロック
図、第２図はプロセッサ間ネットワークシステムの構成
図である。
５０１、５０２．５０４．５０７．５１０．５１１．５
１３．５１５゜５１７、５１９．９０１．９０２・・・
信号線、５０３−・・プロセッサ故障表示レジスタ、５
０５−・・予備プロセッサアドレスレジスタ、５０６
・・・予備プロセッサ宛データ生成回路、５０８、５１
４・・・選択回路、
５０９−・・データ伝送路送信回路、
５１２・・・データ伝送路受信回路、
５１６−・・プロセッサ送信回路、
５１８・・・プロセッサ受信回路、
１．２，３．４・・・プロセッサ、
５．６，７．８・・・データ伝送装置、９・・・データ
伝送路。FIG. 1 is a block diagram of an embodiment of a data transmission device of the present invention, and FIG. 2 is a configuration diagram of an inter-processor network system. 501, 502.504.507.510.511.5
13.515°517, 519.901.902...
Signal line, 503--Processor failure indication register, 5
05--Spare processor address register, 506
...data generation circuit for backup processor, 508, 51
4... Selection circuit, 509-- Data transmission line transmitting circuit, 512... Data transmission line receiving circuit, 516-... Processor transmitting circuit, 518... Processor receiving circuit, 1.2, 3.4 ... Processor, 5.6, 7.8... Data transmission device, 9... Data transmission path.
Claims (1)
伝送装置と、これら各データ伝送装置に接続された処理
装置と、これらデータ伝送装置の間を結合するためのデ
ータ伝送路からなるデータ伝送システムにおいて、 自データ伝送装置に接続された処理装置および自データ
伝送装置と処理装置間のパスの正常／故障の情報を保持
する正常／故障情報保持手段と、 正常／故障情報保持手段が故障の情報を保持している場
合にデータ伝送路受信回路の受信データが転送される予
備処理装置のアドレス情報を保持する予備処理装置アド
レス情報保持手段と、正常／故障情報保持手段が故障の
情報を保持している場合に、データ伝送路からの受信デ
ータと予備処理装置アドレス情報保持手段のアドレス情
報を入力して予備処理装置宛のデータを生成し、データ
伝送路送信回路に出力する予備処理装置宛データ生成手
段を備えたことを特徴とするデータ伝送装置。[Scope of Claims] A plurality of data transmission devices that can serve as a transmitter or a receiver, a processing device connected to each of these data transmitters, and a data transmission path for coupling these data transmitters. A data transmission system comprising: a normality/failure information holding means for holding information on normality/failure of a processing device connected to the own data transmission device and a path between the own data transmission device and the processing device; and a normality/failure information holding means. If the means holds failure information, the preprocessor address information holding means holds the address information of the preprocessor to which the received data of the data transmission path receiving circuit is transferred, and the normal/failure information holding means malfunctions. , the received data from the data transmission path and the address information of the preprocessing device address information holding means are input to generate data addressed to the preprocessing device, and the data is output to the data transmission path transmitting circuit. A data transmission device characterized by comprising a data generation means for a preprocessing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60197010A JPS6257337A (en) | 1985-09-05 | 1985-09-05 | Data transmission equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60197010A JPS6257337A (en) | 1985-09-05 | 1985-09-05 | Data transmission equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6257337A true JPS6257337A (en) | 1987-03-13 |
Family
ID=16367283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60197010A Pending JPS6257337A (en) | 1985-09-05 | 1985-09-05 | Data transmission equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257337A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5384783A (en) * | 1990-11-20 | 1995-01-24 | Hitachi, Ltd. | Network system and line switching method used therein |
| WO2010070713A1 (en) * | 2008-12-19 | 2010-06-24 | 富士通株式会社 | Information processing device and control method |
-
1985
- 1985-09-05 JP JP60197010A patent/JPS6257337A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5384783A (en) * | 1990-11-20 | 1995-01-24 | Hitachi, Ltd. | Network system and line switching method used therein |
| WO2010070713A1 (en) * | 2008-12-19 | 2010-06-24 | 富士通株式会社 | Information processing device and control method |
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