JPS6253937B2 - - Google Patents
Info
- Publication number
- JPS6253937B2 JPS6253937B2 JP57097947A JP9794782A JPS6253937B2 JP S6253937 B2 JPS6253937 B2 JP S6253937B2 JP 57097947 A JP57097947 A JP 57097947A JP 9794782 A JP9794782 A JP 9794782A JP S6253937 B2 JPS6253937 B2 JP S6253937B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- patterns
- pattern
- wafer
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 229910000889 permalloy Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はフオト・レジストパターンの形成方
法、特に該パターン形成後に行なわれるエツチン
グの管理を容易化せしめた形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of forming a photoresist pattern, and more particularly to a forming method that facilitates the management of etching performed after the pattern is formed.
(b) 技術の背景
微細なパターンを具えたチツプの量産、例えば
磁気バルブの転送に必要な磁性体パターンとバブ
ル発生器やバルブ検出器等の導体パターン等を具
えた磁気バブルメモリ装置用チツプの量産手段と
して、複数個のチツプが採取可能なウエーハを使
用したフオト・リソグラフイ技術が用いられてい
る。即ち、GGG等にてなる前記ウエーハの表面
に或る種の磁性体（例えばガーネツト）の結晶膜
を形成し、その表面にAl―Cu等の導体層とSio2
等の絶縁層を介してパーマロイ等の磁性体層を形
成し、該導体層及び該磁性層についてはそれらの
表面にポジ・レジスト層を被着し、ステツプアン
ドリピート手段による縮小投影法で複数のチツプ
パターンを焼付け・現像したのち、該導体層及び
磁気体層を選択的にエツチングして所望のチツプ
パターンが形成される。(b) Background of the technology Mass production of chips with fine patterns, for example, chips for magnetic bubble memory devices with magnetic patterns necessary for magnetic valve transfer and conductor patterns for bubble generators, valve detectors, etc. As a means of mass production, photolithography technology is used that uses wafers from which a plurality of chips can be obtained. That is, a crystal film of a certain type of magnetic material (garnet, for example) is formed on the surface of the wafer made of GGG, etc., and a conductor layer such as Al-Cu and a SiO2 film are formed on the surface of the wafer.
A magnetic layer such as permalloy is formed through an insulating layer such as the above, and a positive resist layer is deposited on the surface of the conductor layer and the magnetic layer, and multiple layers are formed by a reduction projection method using step-and-repeat means. After the chip pattern is baked and developed, the conductor layer and magnetic layer are selectively etched to form a desired chip pattern.
(c) 従来技術と問題点
しかし、チツプパターンが微細でありポジ・レ
ジストを用いたときには、露光されないレジスト
層が可溶化されずに残るため、目視により前記エ
ツチングが終了したかどうかを確認することが非
常に困難であつた。特にチツプパターンが微小で
微細なパターンの集合体であり、かつ、該微小パ
ターンがチツプのほぼ全面に分散しているとき
は、前記確認がさらに困難となつた。(c) Prior art and problems However, when the chip pattern is fine and a positive resist is used, the unexposed resist layer remains unsolubilized, so it is necessary to visually check whether the etching has been completed. was extremely difficult. In particular, when the chip pattern is an aggregate of minute patterns and the minute patterns are dispersed over almost the entire surface of the chip, the above confirmation becomes even more difficult.
(d) 発明の目的
本発明の目的は、前記エツチングの進度確認を
容易ならしめることである。(d) Purpose of the Invention The purpose of the present invention is to facilitate confirmation of the progress of etching.
(e) 発明の構成
上記目的は、ウエーハの表面にレジスト層を被
着し、ステツプアンドリピート手段による縮小投
影法で複数のチツプパターンを焼付け、該焼付け
に際して一部のチツプパターンはそのチツプ内の
パターンのほとんどを消すべく適宜量だけずらし
て少なくとも２重に焼付け、次いで該レジスタ層
を現像したことを特徴とするフオト・レジストパ
ターンの形成方法により達成される。(e) Structure of the Invention The above object is to apply a resist layer to the surface of a wafer, and to print a plurality of chip patterns by a reduction projection method using step-and-repeat means, and during the printing, some of the chip patterns are removed from the inside of the chip. This is achieved by a method of forming a photoresist pattern, which is characterized in that the resist layer is baked at least twice, shifted by an appropriate amount to erase most of the pattern, and then the resist layer is developed.
(f) 発明の実施例
以下、本発明を磁気バブルチツプのバブル転送
路を形成するレジストパターンに適用した一実施
例に係わる第１図〜第４図を用いて本発明方法を
説明する。(f) Embodiments of the Invention The method of the present invention will be described below with reference to FIGS. 1 to 4, which relate to an embodiment in which the present invention is applied to a resist pattern forming a bubble transfer path of a magnetic bubble chip.
第１図は、所定の工程を終了したGGGウエー
ハ１の表面にポジ・レジスト層２を被着し、複数
個（図は32個）のチツプパターン３をステツプア
ンドリピート手段による縮小投影法で第１次の焼
付けをした平面図であり、第２図はチツプパター
ン３の一部分を拡大して示した平面図である。 In FIG. 1, a positive resist layer 2 is deposited on the surface of a GGG wafer 1 that has undergone a predetermined process, and a plurality of chip patterns 3 (32 in the figure) are projected using a step-and-repeat method. This is a plan view showing the first printing process, and FIG. 2 is a plan view showing a part of the chip pattern 3 in an enlarged manner.
そして、各チツプパターン３は幅が７μｍのハ
ーフデイスク形ビツトパターン４が８μｍピツチ
で整列する複数のビツト列５と６を構成し、ビツ
トパターン４が対向するように整列したビツト列
５と６は図示しないチツプ領域内でループ状に接
続して複数のバブルを転送路を構成する。ところ
で従来は第１図に示す焼付けをした次の工程で現
像処理して、露光され可溶化したビツトパターン
４に対応するレジスト層２の一部を溶去してい
た。 Each chip pattern 3 constitutes a plurality of bit rows 5 and 6 in which half-disk-shaped bit patterns 4 having a width of 7 μm are arranged at a pitch of 8 μm, and bit rows 5 and 6 are arranged so that the bit patterns 4 face each other. A plurality of bubbles are connected in a loop within a chip area (not shown) to form a transfer path. Conventionally, the resist layer 2 was developed in the next step after the baking shown in FIG. 1, and a portion of the resist layer 2 corresponding to the exposed and solubilized bit pattern 4 was dissolved away.
第３図は、第１図に示した第１次の焼付けを行
なつたのち予め選択した４箇所のチツプパターン
３―１，３―２，３―３，３―４について、図示
上方又は下方へ約３μｍずらしチツプパターン３
―1′，３―2′，３―3′，３―4′を重複させ第２次焼
付けをしたウエーハ１′の平面図であり、第４図
は該重複焼付けされたチツプパターンの一部分を
拡大して示す平面図である。 FIG. 3 shows four chip patterns 3-1 , 3-2 , 3-3 , and 3-4 selected in advance after the first baking shown in FIG. Chip pattern 3 shifted by about 3 μm to
- 1 ', 3- 2 ', 3- 3 ', 3- 4 ' is a plan view of a wafer 1' on which secondary baking has been performed, and FIG. FIG. 3 is an enlarged plan view.
第３図において、チツプパターン３―１〜４と
３―1′〜4′は同じマスクを用いて焼付けたもので
あり、チツプパターン３―1′と３―2′はチツプパ
ターン３―１と３―２より上方へ３μｍだけずら
し、チツプパターン３―3′と３―4′はチツプパタ
ーン３―３と３―４より下方へ３μｍだけずらし
てステツプさせ、かつ、第２次焼付けは第１次焼
付けより十分な時間（例えば２倍の時間）を掛け
てオーバ露光させたものである。 In Fig. 3, chip patterns 3-1 to 4 and 3-1 ' to 4 ' are printed using the same mask, and chip patterns 3-1 ' and 3-2 ' are similar to chip pattern 3-1 . Chip patterns 3-3 ' and 3-4 ' are shifted by 3 μm downward from chip patterns 3-3 and 3-4 , and the second baking is performed by the first step. Overexposure is performed over a sufficient period of time (for example, twice as long) as in the next printing.
従つて、第４図に示す如く第２次焼付けによる
ビツトパターン４′の列は、第１次焼付けによる
ビツトパターン４の列（ビツト列５と６）の中間
に焼付けられ、かつ、ビツトパターン４′はオー
バ露光させたことによりその周囲へ広がつて感光
させている。 Therefore, as shown in FIG. 4, the row of bit patterns 4' by the second baking is printed in the middle of the row of bit patterns 4 (bit rows 5 and 6) by the first baking, and ′ is overexposed and spreads around it to expose it to light.
そのため、ウエーハ１′を現像したとき重複焼
付けしないチツプパターン３はマスクに対して忠
実なレジストパターンが形成される反面、重複焼
付けした部分はほぼ全域のレジストが溶去される
ようになり、次のエツチング工程では該溶去され
た部分からエツチング進度（エツチングの終了）
を目視で確認することができる。 Therefore, when the wafer 1' is developed, a resist pattern faithful to the mask is formed in the chip pattern 3 that is not repeatedly baked, but on the other hand, almost the entire area of the resist in the overlapped part is eluted, and the next In the etching process, the etching progress (end of etching) is measured from the eluted part.
can be visually confirmed.
なお、上記実施例では完全なチツプパターンが
形成可能な４箇所で重複焼付けし、チツプ採取の
歩留りを低下させているが、重複焼付けを完全な
チツプパターンの形成できない位置に選定するこ
とにより該歩留り低下を無くすることができる。
また、重複焼付けする位置と箇所数は実施例の如
く、周囲に分散する４箇所にすることが一般的に
望ましいが、適宜に箇所数を増減し、かつ、ウエ
ーハの中央部に選定してもよい。さらに、重複焼
付けする回数とずらす方向及びずらす量は、焼付
けるチツプパターンにより適宜設定すべきもので
あり、実施例に限定されないことを付記する。 Note that in the above embodiment, duplicate baking is performed at four locations where a complete chip pattern can be formed, reducing the yield of chip collection. The drop can be eliminated.
In addition, it is generally desirable to set the position and number of overprinting to four locations distributed around the wafer as in the example, but it is also possible to increase or decrease the number of locations as appropriate and select the location at the center of the wafer. good. Furthermore, it should be noted that the number of times of overlapping printing, the direction of shifting, and the amount of shifting should be appropriately set depending on the chip pattern to be printed, and are not limited to the embodiments.
(g) 発明の効果
以上説明した如く本発明によれば、エツチング
の終了したことが目視で容易に確認できるため、
エツチング未了及びオーバエツチングによるパタ
ーン不良を著しく低減し得た効果が大きい。(g) Effects of the Invention As explained above, according to the present invention, the completion of etching can be easily confirmed visually.
The effect of significantly reducing pattern defects due to unfinished etching and overetching is significant.
第１図は所定工程を終了したウエーハの表面に
レジスト層を被着し複数個のチツプパターンを焼
付けした平面図、第２図は前記チツプパターンの
一部分を拡大して示す平面図、第３図は前記ウエ
ーハにおいて一部の既焼付けチツプパターンから
所定方向へ３μｍだけずらしたチツプパターンを
重複焼付けした平面図、第４図は前記重複焼付け
したチツプパターンの一部分を拡大して示す平面
図である。
なお図中において、１，１′はウエーハ、３，
３―１〜４，３―1′〜4′はチツプパターン、４，
４′はビツトパターンを示す。
FIG. 1 is a plan view showing a resist layer coated on the surface of a wafer that has undergone a predetermined process and a plurality of chip patterns are baked thereon; FIG. 2 is a plan view showing an enlarged portion of the chip patterns; FIG. 4 is a plan view in which a chip pattern shifted by 3 .mu.m in a predetermined direction from a part of the already-baked chip patterns is redundantly printed on the wafer, and FIG. In the figure, 1, 1' are wafers, 3,
3-1 to 4 , 3-1 ' to 4 ' are chip patterns, 4,
4' indicates a bit pattern.
Claims (1)
ツプアンドリピート手段による縮小投影法で複数
のチツプパターンを焼付け、該焼付けに際して一
部のチツプパターンはそのチツプ内のパターンの
ほとんどを消すべく適宜量だけずらして少なくと
も２重に焼付け、次いで該レジスト層を現像した
ことを特徴とするフオト・レジストパターンの形
成方法。1. A resist layer is deposited on the surface of the wafer, and a plurality of chip patterns are baked by a reduction projection method using step-and-repeat means. During the baking, some of the chip patterns are coated with an appropriate amount to erase most of the patterns within the chip. 1. A method for forming a photoresist pattern, which comprises baking at least twice in a staggered manner, and then developing the resist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57097947A JPS58215026A (en) | 1982-06-08 | 1982-06-08 | Formation of photo resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57097947A JPS58215026A (en) | 1982-06-08 | 1982-06-08 | Formation of photo resist pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58215026A JPS58215026A (en) | 1983-12-14 |
| JPS6253937B2 true JPS6253937B2 (en) | 1987-11-12 |
Family
ID=14205860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57097947A Granted JPS58215026A (en) | 1982-06-08 | 1982-06-08 | Formation of photo resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58215026A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50128469A (en) * | 1974-03-27 | 1975-10-09 | ||
| JPS5431282A (en) * | 1977-08-12 | 1979-03-08 | Mitsubishi Electric Corp | Pattern formation method |
-
1982
- 1982-06-08 JP JP57097947A patent/JPS58215026A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50128469A (en) * | 1974-03-27 | 1975-10-09 | ||
| JPS5431282A (en) * | 1977-08-12 | 1979-03-08 | Mitsubishi Electric Corp | Pattern formation method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58215026A (en) | 1983-12-14 |
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