JPS6250989B2 - - Google Patents
Info
- Publication number
- JPS6250989B2 JPS6250989B2 JP17101279A JP17101279A JPS6250989B2 JP S6250989 B2 JPS6250989 B2 JP S6250989B2 JP 17101279 A JP17101279 A JP 17101279A JP 17101279 A JP17101279 A JP 17101279A JP S6250989 B2 JPS6250989 B2 JP S6250989B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- ion
- ion implantation
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 10
- 238000009826 distribution Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- -1 boron ion Chemical class 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にイオン注入を含む半
導体装置の製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device including ion implantation.
半導体基体へ不純物を導入する手段としてイオ
ンを注入することは広く行われている。例えば、
MOS型FETのチヤネルしきい値を制御する方法
として、半導体の表面に局在して、正確に不純物
を導入できる方法としては他に類をみない有用性
が確認されている。この他ソース・ドレインの高
不純物層の形成、バイポーラトランジスタの製造
におけるベース、エミツタの形成にも有効に利用
されている。 Ion implantation is widely practiced as a means of introducing impurities into semiconductor substrates. for example,
As a method for controlling the channel threshold of MOS FETs, it has been confirmed that this method is uniquely useful as it allows for localized and accurate introduction of impurities into the surface of a semiconductor. In addition, it is effectively used to form highly impurity layers for sources and drains, and to form bases and emitters in the manufacture of bipolar transistors.
イオン注入工程は、一般に半導体表面が汚染さ
れることを避けるため、通常、第１図に示す様に
基体１の上にSiO2などの絶縁層２を付着し、こ
れを通して行うのが多い。３は例えば、ボロンイ
オンUB+であり、これが40KeVで加速されると、
500ÅのSiO2である２を通しては、１の中へ平均
的な深さ1000Åまで注入される。 In order to avoid contaminating the semiconductor surface, the ion implantation process is usually performed through an insulating layer 2 such as SiO 2 deposited on a substrate 1 as shown in FIG. 1. For example, 3 is boron ion UB+ , and when this is accelerated at 40KeV,
Through 2, 500 Å of SiO 2 is implanted into 1 to an average depth of 1000 Å.
第２図の４は基板へ注入されたイオンの分布を
示す。横軸は表面からの深さＸ、縦軸は不純物濃
度Ciを示す。MOSFETのチヤネルしきい値の制
御の場合は、２はゲート酸化膜であり、通常400
〜1500Åである場合が多い。注入工程を終了した
基体は、汚染を除くため洗浄されるが、この時２
の表面を20〜50Åエツチ除去去する必要がある。 4 in FIG. 2 shows the distribution of ions implanted into the substrate. The horizontal axis represents the depth X from the surface, and the vertical axis represents the impurity concentration Ci. In the case of MOSFET channel threshold control, 2 is the gate oxide film, usually 400
It is often ~1500 Å. After completing the implantation process, the substrate is cleaned to remove contamination.
It is necessary to etch away the surface by 20-50 Å.
高性能な集積回路を作るためには、MOSFET
のゲート絶縁膜は、前述の値より薄くする必要が
ある。例えば100Åとする場合は、前述の洗浄工
程における減少分を見込んでおかなければならな
いが、エツチングでは、均一なエツチが難しく、
さらに、うすいゲート絶縁膜が必要になるほどエ
ツチングの不均一性による膜厚のばらつき、従つ
てFET特性のばらつきは大きくなる。これを解
決する１つの方法は、うすいゲート絶縁膜の上に
ゲートとなるべき、多結晶SiやMo等の金属を付
着後、ゲート金属とゲート絶縁膜を通して基板ま
で達する様に注入エネルギーを選んでイオン注入
すればよいが、ゲート金属の厚さは、通常3000Å
以上であり、これを通してイオン注入するために
は、ボロンイオンの場合で100KeV以上のエネル
ギーが必要である。一般に注入エネルギーが大き
くなると、イオンの注入深さの分布も広がること
が知られており、この工程を経た素子は必ずしも
一般的な注入工程によるEFTの特性と同じでな
い。 MOSFETs are needed to create high-performance integrated circuits.
The gate insulating film must be thinner than the above value. For example, when setting the thickness to 100 Å, it is necessary to take into account the reduction in the cleaning process mentioned above, but with etching, uniform etching is difficult.
Furthermore, the thinner the gate insulating film is required, the greater the variation in film thickness due to non-uniform etching, and therefore the greater the variation in FET characteristics. One way to solve this problem is to deposit a metal such as polycrystalline Si or Mo to form the gate on a thin gate insulating film, and then select the implantation energy so that it reaches the substrate through the gate metal and gate insulating film. Ion implantation is sufficient, but the thickness of the gate metal is usually 3000Å.
This is the above, and in order to implant ions through this, an energy of 100 KeV or more is required for boron ions. It is generally known that as the implantation energy increases, the distribution of ion implantation depth also widens, and devices that undergo this process do not necessarily have the same characteristics as EFT produced by a general implantation process.
本発明は、この様な不都合をなくすべき方法で
あつて、今後、100Å程度のゲート絶縁膜が必要
とされ、基体表面に極く浅く不純物を局在させる
必要のある素子で、有効な手法になるものであ
る。 The present invention is a method to eliminate such inconveniences, and is an effective method for devices that will require gate insulating films of about 100 Å in thickness and localize impurities extremely shallowly on the substrate surface. It is what it is.
本発明の工程は、第３図ａ，ｂ，ｃに示されて
いる様に半導体基体１の上へ絶縁層２を生成し、
２の表面に、半導体または金属５を付着し（第３
図ａ）、５及び２を通して１の表面へイオン６を
注入し（第３図ｂ）、しかる後に半導体または金
属８を５の上へ付着し（第３図ｃ）、５及び８を
パターン形成することにより、半導体装置の配線
として用いるものである。なお、７はイオン注入
領域を示す。本発明によれば、イオン注入は、５
の上から行うので２が汚染されることなく、注入
後充分な洗浄を行うことが可能である。また、５
の厚さは、注入工程における汚染が２へ到達しな
い程度に充分薄くできるので、注入イオンエネル
ギーは、従来方法より、わずかに高くすればよ
く、結果として、第４図の９に示す様な鋭い分布
を得ることができる。また配線は５及び８が使用
されるから、その厚さは８によつて任意に決定で
き、配線抵抗も充分低くできる。 The process of the invention includes producing an insulating layer 2 on a semiconductor substrate 1 as shown in FIGS. 3a, b, c,
A semiconductor or metal 5 is attached to the surface of 2 (3rd
Figure a), implanting ions 6 into the surface of 1 through 5 and 2 (Figure 3b), then depositing a semiconductor or metal 8 on top of 5 (Figure 3c), patterning 5 and 8. By doing so, it can be used as wiring for semiconductor devices. Note that 7 indicates an ion implantation region. According to the invention, the ion implantation is performed by
Since the injection is carried out from above, it is possible to perform sufficient cleaning after injection without contaminating 2. Also, 5
Since the thickness of 2 can be made sufficiently thin so that contamination during the implantation process does not reach 2, the implanted ion energy only needs to be slightly higher than in the conventional method, resulting in a sharp ion beam as shown at 9 in Figure 4. distribution can be obtained. Further, since the wires 5 and 8 are used, the thickness can be arbitrarily determined by the wires 8, and the wire resistance can be made sufficiently low.
次に本発明の実施例としてMOS FETの製造工
程を第５図ａ乃至ｆを用いて説明する。３〜５
Ω・cm程度の抵抗率をもつＰ型のSi基体１０上
に、FETを作成すべき領域を除いてフイールド
SiO2１１を第５図ａのように約8000Å生成す
る。次にゲートSiO2１２を100Å生成し（第５図
ｂ）、続いて、多結晶Si１３を500Å付着する。次
に30KeVのエネルギーでボロンイオン１４
（11B+）を４×1012cm-2注入する（第５図ｃ）。こ
れにより、１３及び１２を通してボロンイオンは
基板１０の中へ1000Åの深さまで急峻な分布で注
入される。シリコンの場合イオン注入後でも安定
で、この段階で表面のライトエツチングをしても
よいが、これを実施しなくてもよい。次に、不純
物をドープした多結晶Si１５を3000Å付着し（第
５図ｄ）、１５及び１３をパターン形成し、１６
のゲート電極を形づくる。次に、ひ素（AS+）イ
オン１７を150KeVのエネルギーで４×1015cm-2
注入し、１８及び１９に示されているソース、ド
レイン領域及び１６へのドーピングを完成する
（第５図ｅ）。次に熱処理を経た後、PSGの被覆２
０をし各領域への接続穴をあけ、Al電極のソー
ス、ドレイン電極２１，２２を形成する（第５図
ｆ）。第５図の工程により製造したFETは100Å
の非常にうすいゲート絶縁膜をもつているにもか
かわらず、安定性に優れており、均一な高利得の
特性を示した。その理由はゲートSiO2の汚染が
全くなく、さらに注入イオンの分布が表面に局在
して理論値に近い形状をしているため素子の最適
設計に近い形に製造できたためである。以上の例
からわかるように本発明の実用的価値は大きいと
考えられる。 Next, the manufacturing process of a MOS FET as an embodiment of the present invention will be explained using FIGS. 5a to 5f. 3-5
A field is formed on a P-type Si substrate 10 with a resistivity of about Ω・cm except for the area where the FET is to be fabricated.
SiO 2 11 is formed to a thickness of about 8000 Å as shown in FIG. 5a. Next, a gate SiO 2 12 of 100 Å is formed (FIG. 5b), and then a polycrystalline Si 13 of 500 Å is deposited. Next, with an energy of 30 KeV, boron ion 14
Inject 4×10 12 cm -2 of ( 11 B + ) (Figure 5c). As a result, boron ions are implanted into the substrate 10 through 13 and 12 to a depth of 1000 Å with a steep distribution. In the case of silicon, it is stable even after ion implantation, and the surface may be lightly etched at this stage, but this is not necessary. Next, 3000 Å of polycrystalline Si 15 doped with impurities was deposited (Fig. 5d), patterns 15 and 13 were formed, and 16
form the gate electrode. Next, arsenic (AS + ) ions 17 were irradiated with 4×10 15 cm -2 at an energy of 150 KeV.
The implantation completes the source and drain regions shown at 18 and 19 and the doping of 16 (FIG. 5e). Next, after heat treatment, PSG coating 2
0 and make connection holes to each region to form source and drain electrodes 21 and 22 of the Al electrode (FIG. 5f). The FET manufactured by the process shown in Figure 5 is 100Å.
Despite having an extremely thin gate insulating film, it exhibited excellent stability and uniform high gain characteristics. The reason for this is that there is no contamination of the gate SiO 2 , and the distribution of implanted ions is localized on the surface and has a shape close to the theoretical value, making it possible to manufacture the device in a shape close to the optimal design. As can be seen from the above examples, the present invention is considered to have great practical value.
第１図は従来のイオン注入工程の断面図、第２
図は、そのイオン分布である。第３図ａ，ｂ，ｃ
は本発明の説明図であり、第４図はそのイオン分
布例である。第５図は、本発明の１実施例であつ
て、MOSFETの製造工程を示す各工程の断面図
である。
図中、１，１０は半導体基板、２，１２は酸化
膜、５，１３は第１の半導体または金属、７，１
８，１９はイオン注入領域、８，１５は第２の半
導体または金属、１１はフイールド酸化膜、１６
は多層ゲート電極、２０はPSG膜、２１と２２は
それぞれソース、ドレイン電極である。
Figure 1 is a cross-sectional view of the conventional ion implantation process;
The figure shows the ion distribution. Figure 3 a, b, c
is an explanatory diagram of the present invention, and FIG. 4 is an example of the ion distribution thereof. FIG. 5 is an embodiment of the present invention, and is a cross-sectional view of each step showing the manufacturing process of a MOSFET. In the figure, 1 and 10 are semiconductor substrates, 2 and 12 are oxide films, 5 and 13 are first semiconductors or metals, and 7 and 1
8 and 19 are ion implantation regions, 8 and 15 are second semiconductors or metals, 11 is a field oxide film, and 16
2 is a multilayer gate electrode, 20 is a PSG film, and 21 and 22 are source and drain electrodes, respectively.
Claims (1)
上に付着した第１の半導体または金属層を通し
て、該半導体基体へイオンを注入せしめ、しかる
後、同じまたは他の第２の半導体または金属層を
重ね、第１及び第２の半導体または金属層をパタ
ーン形成することを特徴とする半導体装置の製造
方法。1. Implanting ions into the semiconductor substrate through an insulating film deposited on the semiconductor substrate and a first semiconductor or metal layer deposited on the insulating film, and then implanting the same or another second semiconductor or metal layer. 1. A method of manufacturing a semiconductor device, comprising overlapping and patterning first and second semiconductor or metal layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17101279A JPS5694772A (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17101279A JPS5694772A (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5694772A JPS5694772A (en) | 1981-07-31 |
| JPS6250989B2 true JPS6250989B2 (en) | 1987-10-28 |
Family
ID=15915453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17101279A Granted JPS5694772A (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5694772A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173757A (en) * | 1987-12-28 | 1989-07-10 | Fujitsu Ltd | Manufacture of mis semiconductor device |
-
1979
- 1979-12-28 JP JP17101279A patent/JPS5694772A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5694772A (en) | 1981-07-31 |
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