JPH01173757A - Manufacture of mis semiconductor device - Google Patents
Manufacture of mis semiconductor deviceInfo
- Publication number
- JPH01173757A JPH01173757A JP33215687A JP33215687A JPH01173757A JP H01173757 A JPH01173757 A JP H01173757A JP 33215687 A JP33215687 A JP 33215687A JP 33215687 A JP33215687 A JP 33215687A JP H01173757 A JPH01173757 A JP H01173757A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- implanted
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 abstract description 23
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000006866 deterioration Effects 0.000 abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 8
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000428 dust Substances 0.000 abstract description 4
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
Ｍｉｓ型半導体装置における、闇値調整用及びソース−
ドレイン間パンチスルー防止用の不純物導入領域の形成
方法の改良に関し、
チャネル形成領域及びチャネル下部領域に不純物を４人
する際のゲート絶縁膜の耐圧劣化を防止し、且つ不純物
の導入されたチャネル形成領域を浅く形成してソース−
ドレイン間の耐圧劣化を防止することを目的とし、
ソース領域とドレイン領域との離間部に、不純物導入領
域を設けるに際して、半導体基体上にゲート絶縁膜を形
成し、該ゲート絶縁膜上にゲート電掘の材料となる導電
体層を形成し、該導電体層及びゲート絶縁膜を通して該
半導体基体内に不純物をイオン注入する工程を含んで構
成する。[Detailed description of the invention] [Summary] Dark value adjustment and source in Mis type semiconductor device
Regarding the improvement of the method of forming an impurity-introduced region for preventing punch-through between drains, this study aims to prevent deterioration in breakdown voltage of the gate insulating film when impurities are added to the channel formation region and the channel lower region, and to form a channel with impurities introduced. By forming a shallow region to
In order to prevent breakdown voltage deterioration between the drain and drain regions, a gate insulating film is formed on the semiconductor substrate and a gate voltage is applied on the gate insulating film when providing an impurity-introduced region in the space between the source region and the drain region. The method includes the steps of forming a conductive layer as a material for the trench, and implanting impurity ions into the semiconductor substrate through the conductive layer and the gate insulating film.
本発明はＭＩＳ型半導体装置における、闇値調整用及び
ソース−ドレイン間パンチスルー防止用の不純物導入領
域の形成方法の改良に関する。The present invention relates to an improvement in a method of forming an impurity-introduced region for dark value adjustment and prevention of source-drain punch-through in a MIS type semiconductor device.
ＬＳＩ等ＭＩＳ型半導体装置は高集積化、高速化の進行
のために、該Ｍｉｓ半導体装置に配設される電界効果ト
ランジスタ（ＦＥＴ）のヂャネル長は極度に縮小され、
これに伴ってソース−ドレイン間の距Ｍｌｆが著しく接
近してきている。As MIS type semiconductor devices such as LSIs become more highly integrated and faster, the channel length of field effect transistors (FETs) disposed in the MIS semiconductor devices is extremely reduced.
Along with this, the source-drain distance Mlf has become significantly smaller.
しかし高速性等の維持のために、その電源電圧は従来通
り高い侭で保持されるので、ソース若しくはドレイン領
域からの空乏層の拡がりによってソース〜ドレイン間が
短絡するという所謂ショートチャネル効果を生じて素子
性能が損なわれるという問題を生ずる。However, in order to maintain high speed, etc., the power supply voltage is kept high as before, so the so-called short channel effect occurs, in which the depletion layer spreads from the source or drain region, causing a short circuit between the source and drain. A problem arises in that device performance is impaired.
そこでショートチャネルＭＯ３ＦＥＴにおいてはチャネ
ル形成領域の下部領域が、不純物導入領域の形成によっ
て基体と同導電型の比較的高濃度に維持される。Therefore, in the short channel MO3FET, the lower region of the channel formation region is maintained at a relatively high concentration of the same conductivity type as the substrate by forming an impurity introduction region.
従ってまたチャネル領域には、更に反対導電型不純物を
導入してその闇値電圧の制御がなされることが多い。Therefore, the dark value voltage is often controlled by further introducing impurities of opposite conductivity type into the channel region.
従来、ｐチャネル型ＭＯＳ Ｆ ＥＴを形成する際には
、以下に第３図（ａｌ 〜（ｂ）及び第４図（ａ）〜（
Ｃ）に従って説明する２種類の方法が用いられていた。Conventionally, when forming a p-channel type MOS FET, the steps shown in FIGS.
Two methods were used as described in accordance with C).
第１の方法は第３図（ａｌに示すように、基板若しくは
ウェルからなるｎ−型のシリコン（Ｓｉ）基体１がフィ
ールド酸化膜２及びその下部のｎ型チャネルストッパ３
によって画定表出された素子形成領域４上にゲート酸化
膜５を形成した後、該ゲート酸化膜５を通して硼素（Ｂ
゛）または（ｔ＋Ｆｚ” ）を浅くイオン注入しく１０
６はＢゝｏｒ ＯＦ、’注入領域）、該注入不純物を、
第３図（ｂ）に示すように、ゲート電極７形成後、ゲー
ト電極７をマスクにしてを高濃度にイオン注入されたＢ
゛と同時に活性化し、ｐ゛型のソース領域８及びドレイ
ン領域９と共にゲート下部領域に浅いｎ−型チャネル領
域６を形成する方法である。The first method is as shown in FIG.
After forming a gate oxide film 5 on the element formation region 4 defined and exposed by , boron (B
゛) or (t+Fz”) should be shallowly implanted.
6 is B or OF, 'implanted region), and the implanted impurity is
As shown in FIG. 3(b), after the gate electrode 7 is formed, B ions are implanted at a high concentration using the gate electrode 7 as a mask.
In this method, a shallow n-type channel region 6 is formed in the gate lower region along with a p-type source region 8 and a drain region 9 by activating the gate electrode at the same time.
また第２の方法は第４図（ａ）に示すように、素子形成
領域４上に不純物イオンを透過する酸化膜１０を形成し
て上記同様にｐ型不純物のイオン注入を行い（１０６は
Ｂ” ｏｒ ［ｌＦ２＋注入領域）、次いで上記酸化ｖ
１０を除去した後に、例えば１０００〜１１００”ｃ程
度の温度で熱酸化を行い、第４図（ｂ）に示すように素
子形成領域４上にゲート酸化膜５を形成する。In the second method, as shown in FIG. 4(a), an oxide film 10 that transmits impurity ions is formed on the element formation region 4, and p-type impurity ions are implanted in the same manner as described above (106 is B ” or [lF2+ implanted region), then the above oxidation v
After removing the gate oxide film 10, thermal oxidation is performed at a temperature of, for example, 1000-1100''c to form a gate oxide film 5 on the element formation region 4, as shown in FIG. 4(b).
この熱酸化工程において注入されているＢ’ ｏｒ Ｂ
Ｆ２゛は活性化してｎ−型チャネル領域６が形成される
。そして第４図（Ｃ１に示すようにゲート電極７を形成
し、該ゲート電極７をマスクにしてＢ゛またはｎｐｚ″
を高濃度にイオン注入し、活性化熱処理を行ってｐ゛型
のソース領域８及びドレイン領域９を形成する方法であ
る。B' or B implanted in this thermal oxidation step
F2' is activated and an n-type channel region 6 is formed. Then, as shown in FIG. 4 (C1), a gate electrode 7 is formed, and using the gate electrode 7 as a mask,
In this method, a p-type source region 8 and drain region 9 are formed by ion-implanting at a high concentration and performing activation heat treatment.
しかし上記第１の方法においては、チャネル領域６への
不純物のイオン注入がゲート酸化膜５を通してなされる
ので、イオン注入時に雰囲気中から打ち込まれる塵によ
りゲート酸化膜５に欠陥を生じてゲート耐圧が劣化する
おそれがある。However, in the first method, since the impurity ions are implanted into the channel region 6 through the gate oxide film 5, defects are caused in the gate oxide film 5 due to dust injected from the atmosphere during ion implantation, and the gate breakdown voltage is reduced. There is a risk of deterioration.
また上記第２の方法によると、ゲート酸化膜５を形成す
る際の上記高温熱処理によって、基体の表面部に浅く注
入されていたチャネル形成用のＢ″ｏｒ ＣＦ、”が第
４図（ｂｌに示すように基体内に深く再分布しチャネル
領域下部のソース−ドレイン間領域のｐ型不純物濃度を
減少させ、そのためにソース若しくはドレイン領域から
の空乏層の拡がりが拡大してソース−ドレイン間耐圧が
低下するという問題を生ずる。In addition, according to the second method, the high-temperature heat treatment when forming the gate oxide film 5 causes the channel-forming B"or CF," which had been shallowly implanted into the surface of the substrate, to be removed as shown in FIG. As shown in the figure, the p-type impurity concentration is deeply redistributed within the substrate and decreases the p-type impurity concentration in the source-drain region below the channel region, which increases the spread of the depletion layer from the source or drain region and increases the source-drain breakdown voltage. This results in the problem of lowering the temperature.
そこで本発明は、チャネル形成領域及びチャネル下部領
域に不純物を導入する際のゲート絶縁膜の耐圧劣化を防
止し、且つ不純物の導入されたチャネル形成領域を浅く
形成してソース−ドレイン間の耐圧劣化を防止すること
を目的とする。Therefore, the present invention prevents the breakdown voltage deterioration of the gate insulating film when impurities are introduced into the channel formation region and the channel lower region, and forms the channel formation region into which the impurities are introduced shallowly to prevent the breakdown voltage deterioration between the source and drain. The purpose is to prevent
上記問題点は、ソース領域とドレイン領域との離間部に
、不純物導入領域を設けるに際して、半導体基体上にゲ
ート絶縁膜を形成し、該ゲート絶縁股上にゲート電極の
材料となる導電体層を形成し、該４電体層及びゲート絶
縁膜を通して該半導体基体内に不純物をイオン注入する
工程を有する本発明によるＭｉｓ型半導体装置の製造方
法によって解決される。The above problem is solved by forming a gate insulating film on the semiconductor substrate and forming a conductive layer, which will be the material of the gate electrode, on the gate insulating film when providing an impurity-introduced region in the space between the source region and the drain region. However, this problem is solved by the method for manufacturing a Mis-type semiconductor device according to the present invention, which includes a step of ion-implanting impurities into the semiconductor substrate through the four-conductor layer and the gate insulating film.
即ち本発明はチャネル形成領域及びチャネル下部領域へ
の不純物のイオン注入を、基体上にゲ−１・酸化膜を形
成し、更にその上にゲート電極材料の皮膜を形成した後
に該ゲート電極材料皮膜の上から行うことによって、ゲ
ート酸化膜に塵が打ち込まれるのを防止し、且つイオン
注入後にゲート酸化膜を形成するための高温処理が行わ
れないようにして浅くイオン注入されたチャネル形成の
ための基体と反対導電型不純物が深く拡散するのを防止
する。That is, the present invention performs ion implantation of impurities into the channel forming region and the channel lower region by forming a Ga-1 oxide film on the substrate, further forming a film of the gate electrode material thereon, and then forming the film of the gate electrode material. By performing the process from above, it is possible to prevent dust from being implanted into the gate oxide film, and to avoid high-temperature treatment for forming the gate oxide film after ion implantation, and to form a shallow ion-implanted channel. This prevents impurities of conductivity type opposite to the substrate from diffusing deeply.
これによってゲート酸化膜の欠陥に起因するゲート耐圧
の劣化、及びチャネル下部領域の基体不純物？農度の低
下によるソース−ドレイン間耐圧の劣化が防止される。Will this cause deterioration of the gate breakdown voltage due to defects in the gate oxide film and the presence of base impurities in the lower channel region? Deterioration of the source-drain breakdown voltage due to a decrease in agricultural yield is prevented.
以下本発明を、図を参照し実施例により具体的に説明す
る。Hereinafter, the present invention will be specifically explained by examples with reference to the drawings.
第１図（ａｌ〜（ｄｌは本発明の一実施例の工程断面図
、第２図ｆａｌ〜（ｂ）は本発明の他の実施例の工程断
面図である。FIGS. 1(al to dl) are process cross-sectional views of one embodiment of the present invention, and FIGS. 2 fal to (b) are process cross-sectional views of another embodiment of the present invention.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
第１図（ａ）参照
即ち従来と同様に例えばウェル等からなり１０１６ｅｌ
ｌ −’程度の不純物濃度を有するｎ−型のシリコン（
Ｓｉ）基体１がフィールド酸化膜２及びその下部のｎ型
チャネルストッパ３によって画定表出された素子形成領
域４を有する被加工基板を用い、先ず１０００〜１１０
０℃で行われる通常の熱酸化方法により素子形成領域４
上に厚さ２００〜３００人程度のゲート酸化ｖ５を形成
し、次いで通常の化学気相成長（ＣＶＤ）法により厚さ
２０００〜４０００人程度のポ’ＪＳｉ層１０７を形成
し、次いで該ポリＳｉ層１０７にガス拡散等により不純
物を高濃度に導入して高導電性を与える。Refer to FIG. 1(a). In other words, as in the conventional case, it consists of, for example, wells, etc.
n-type silicon (
First, using a substrate to be processed having an exposed element formation region 4 defined by a field oxide film 2 and an n-type channel stopper 3 below the field oxide film 2,
The element forming area 4 is formed by a normal thermal oxidation method carried out at 0°C.
A gate oxide layer 107 with a thickness of about 200 to 300 layers is formed thereon, and then a poly-Si layer 107 with a thickness of about 2000 to 4000 layers is formed by ordinary chemical vapor deposition (CVD). Impurities are introduced into the layer 107 at a high concentration by gas diffusion or the like to impart high conductivity.
第１図（′ｂ）参照
次いで１００〜１５０ ＫｅＶ程度の加速エネルギーで
上記ポリＳｉ層１０７及びデー１−酸化膜５を通してＳ
ｔ基体１面に、ｐ型不純物例えばＢ゛を１０”〜１０Ｉ
２程度のドーズ量でイオン注入し、Ｓｉ基体１の表面部
に深さ例えば１０００人程度Ｏ８゛低濃度注入領域１０
６を形成する。このイオン注入に際してゲート酸化膜５
は雰囲気中に直に曙されていないので、その表面に塵が
打ち込まれることがなく、該ゲート酸化膜５に欠陥は形
成されない。Referring to FIG. 1('b), S is then heated through the poly-Si layer 107 and the D1-oxide film 5 with an acceleration energy of about 100 to 150 KeV.
10" to 10I of p-type impurity such as B" is applied to one surface of the t-substrate.
Ions are implanted at a dose of about 2,000 ions to a depth of, for example, about 1,000 ions on the surface of the Si substrate 1.
form 6. During this ion implantation, the gate oxide film 5
Since the gate oxide film 5 is not directly exposed to the atmosphere, no dust is implanted into its surface, and no defects are formed in the gate oxide film 5.
第１図ｆｃ）参照
次いで通常通りのフォトリソグラフィにより上記ポリＳ
ｉ層１０７をパターニングしてポリＳｉゲート電極７を
形成し、次いで該ゲート電極７をマスクにし該シリコン
基体１面へ５０ＫｅＶ程度の加速エネルギーで８゛を１
０”ｃｍ−”程度の高ドーズ量でイオン注入する。１０
８及び１０９はＢ゛高？ｚ度注入領域を示す。Refer to FIG. 1 fc). Next, the above polyS is formed by photolithography as usual.
The i-layer 107 is patterned to form a poly-Si gate electrode 7, and then, using the gate electrode 7 as a mask, 8° is applied to the silicon substrate 1 surface at an acceleration energy of about 50 KeV.
Ion implantation is performed at a high dose of about 0"cm-". 10
8 and 109 are B high? The z-degree implantation area is shown.
第１図（ｄｌ参照
次いで８００〜９００℃程度の熱処理を行い、上記Ｂ′
裔濃度注入領域１０８及び１０９を活性化してｐ゛型ソ
ース領域８及びｐ゛型ドレイン領域９を形成すると同時
に、前記Ｂ゛低濃度注入領域１０６を活性化してｎ−型
チャネル領域６を形成する。Figure 1 (see dl) Next, heat treatment at about 800 to 900°C is performed, and the above B'
The progeny concentration implantation regions 108 and 109 are activated to form the p' type source region 8 and the p' type drain region 9, and at the same time, the B' low concentration implantation region 106 is activated to form the n-type channel region 6. .
この活性化処理は８００〜９００°Ｃ程度の比較的低温
で行われるのでＢ゛が拡散再分布することがない。Since this activation treatment is performed at a relatively low temperature of about 800 to 900°C, B' is not diffused and redistributed.
従ってＢ゛の注入深さに見合った１０００人程度Ｏ８い
ｒｌ−型チャネル領域６が形成される。また上記理由に
よりチャネル下部領域の基体濃度即ちｐ型不純物濃度は
低下することがないので、基体濃度に見合って所要のソ
ース−ドレイン間耐圧が確保される。Therefore, an O8 rl-type channel region 6 of about 1000 layers corresponding to the implantation depth of B' is formed. Further, for the above-mentioned reason, the base concentration, that is, the p-type impurity concentration in the lower channel region does not decrease, so that the required source-drain breakdown voltage is ensured commensurate with the base concentration.
ここで上記活性化処理は、図示しない後工程において、
該素子形成領域上に被着された絶縁膜に形成したコンタ
クト窓の側面をなだらかに形成するために行われる該絶
縁膜のリフロー処理に際しての熱処理で兼ねることもあ
る。Here, the above activation process is performed in a post process (not shown).
It may also serve as heat treatment during reflow treatment of the insulating film, which is performed to form a smooth side surface of the contact window formed in the insulating film deposited on the element forming region.
なお本発明の方法は、ソース・ドレイン領域の接合容量
を減少させて高速化に寄与せしめるために基体の不純物
濃度を特に低（し、チャネル下部領域のみに基体と同導
電型の高不純物濃度領域を設けてソース−ドレイン間耐
圧の劣化を防止する構造においても適用される。In addition, in the method of the present invention, the impurity concentration of the substrate is particularly low (and a high impurity concentration region of the same conductivity type as the substrate is formed only in the lower channel region) in order to reduce the junction capacitance of the source/drain region and contribute to higher speed. The present invention is also applied to a structure in which a source-drain breakdown voltage is prevented from deteriorating by providing the structure.
即ちこの場合は第２図（ａｌに示すように、前記実施例
同様ポリＳｉ層１０７上から該ポリＳｉ層１０７及びゲ
ート酸化膜５を通してｎ型不純物例えば燐（Ｐ’）を１
０１３ｃｍ−２程度のドーズ量でソース・ドレイン領域
に見合う例えば３０００人程度０深さにイオン注入して
ｎ型パンチスルー防止領域１１を形成し、次いで第２図
（ｂｌに示すように前記実施例同様Ｂ゛を１０１１〜１
０１２程度のドーズ量で浅くイオン注入してｎ−型チャ
ネル領域６を形成する。That is, in this case, as shown in FIG. 2 (al), an n-type impurity such as phosphorus (P') is injected from above the poly-Si layer 107 through the poly-Si layer 107 and the gate oxide film 5 as in the previous embodiment.
The n-type punch-through prevention region 11 is formed by ion implantation to a depth of about 3,000 ions corresponding to the source/drain region at a dose of about 0.013 cm-2, and then, as shown in FIG. Similarly B゛1011~1
The n-type channel region 6 is formed by shallow ion implantation at a dose of about 0.012.
ここで、Ｐ′″と８４とのイオン注入の順序は逆であっ
てもよい。Here, the order of ion implantation of P''' and 84 may be reversed.
なお本発明の方法は上記実施例に示すｐチャネル型に限
らすｎチャネル型ＭＩＳＦＥＴにも勿論通用される。Note that the method of the present invention is of course applicable not only to the p-channel type MISFET shown in the above embodiment but also to the n-channel type MISFET.
またゲート電極材料に、高融点金属或いは高融点金属の
シリサイドが用いられる際にも適用できる。It can also be applied when a high melting point metal or a silicide of a high melting point metal is used as the gate electrode material.
（発明の効果〕
以上説明のように本発明によれば、Ｍｉｓ型半導体装置
を製造する際に、ゲート絶縁膜に欠陥ができてゲート耐
圧の劣化を生じたり、また不純物がドープされるチャネ
ル領域が深く拡がってソース−ドレイン間耐圧の劣化を
生ずるのが防止される。(Effects of the Invention) As described above, according to the present invention, when manufacturing a Mis-type semiconductor device, defects may occur in the gate insulating film, resulting in deterioration of the gate breakdown voltage, and the channel region may be doped with impurities. is prevented from spreading deeply and causing deterioration of the source-drain breakdown voltage.
従って本発明は、特にショートチャネル構造のＭｉｓ半
導体装置の製造歩留り及び性能の向上に効果がある。Therefore, the present invention is particularly effective in improving the manufacturing yield and performance of Mis semiconductor devices having a short channel structure.
第１図（ａｌ〜（ｄｌは本発明の一実施例の工程断面図
、第２図ｆａ）〜（ｂ）は本発明の他の実施例の工程断
面図、
第３図（ａ）〜（ｂ）及び第４図（ａｌ〜（Ｃ）は従来
の異なる方法の工程断面図である。
図において
１はｎ−型Ｓｉ′）′Ｓ体、
２はフィールド酸化膜、
３はｎ型チャネルストッパ、
４は素子形成領域、
５はゲート酸化膜、
６はｎ−型チャネル領域、
７はポリＳｉゲート電極、
８はｐ゛型ソース領域、
９はｐ４型ドレイン領域、
１０はスルー酸化膜、
１１はｎ型パンチスルー防止？ｉＪＴ域、１０６はＢ゛
低沼度注入領域、
１０７はポリＳｉ層、
１０８．１０９はＢ゛高濃度注入領域
を示す。Figure 1 (al~(dl) is a process sectional view of one embodiment of the present invention, Figure 2 fa)~(b) is a process sectional view of another embodiment of the invention, Figure 3 (a)~( b) and FIGS. 4A to 4C are process cross-sectional views of different conventional methods. In the figures, 1 is an n-type Si')'S body, 2 is a field oxide film, and 3 is an n-type channel stopper. , 4 is an element formation region, 5 is a gate oxide film, 6 is an n-type channel region, 7 is a poly-Si gate electrode, 8 is a p-type source region, 9 is a p4-type drain region, 10 is a through oxide film, 11 106 is a Bₛ low concentration implantation region, 107 is a poly-Si layer, and 108 and 109 are Bₛ high concentration implantation regions.
Claims (1)
領域を設けるに際して、 半導体基体上にゲート絶縁膜を形成し、 該ゲート絶縁膜上にゲート電極の材料となる導電体層を
形成し、 該導電体層及びゲート絶縁膜を通して該半導体基体内に
不純物をイオン注入する工程を有することを特徴とする
ＭＩＳ型半導体装置の製造方法。[Scope of Claims] When providing an impurity-introduced region between a source region and a drain region, a gate insulating film is formed on a semiconductor substrate, and a conductive layer serving as a material for a gate electrode is formed on the gate insulating film. 1. A method for manufacturing an MIS type semiconductor device, comprising the steps of: forming a semiconductor substrate; and implanting impurity ions into the semiconductor substrate through the conductor layer and the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33215687A JPH01173757A (en) | 1987-12-28 | 1987-12-28 | Manufacture of mis semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33215687A JPH01173757A (en) | 1987-12-28 | 1987-12-28 | Manufacture of mis semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173757A true JPH01173757A (en) | 1989-07-10 |
Family
ID=18251777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33215687A Pending JPH01173757A (en) | 1987-12-28 | 1987-12-28 | Manufacture of mis semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173757A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694772A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS59155125A (en) * | 1983-02-24 | 1984-09-04 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-12-28 JP JP33215687A patent/JPH01173757A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694772A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS59155125A (en) * | 1983-02-24 | 1984-09-04 | Toshiba Corp | Manufacture of semiconductor device |
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