JPS6245058A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To stably form a gate length of 1mum or less capable of coping with high speed, by composing both of a process, on which a second conduction-type semiconductor is made to epitaxially grow selectively after a thin oxidizing film is formed on a side face, and a process, on which a high concentration layer is composed to form electrodes at the parts for drain and source regions. CONSTITUTION:A second conduction-type of a first region 103 of high concentration and a second conduction-type of a second region 102 of low concentration are selectively formed on a first conduction-type semiconductor substrate 101, with a first conduction type of a third region 104 formed inside the second region. After both oxidizing film and semiconductor layers are formed in succession all over the substrate, the semiconductor layer is selectively oxidized, and both oxidizing and semiconductor layers on the second region are selectively removed to form a groove 108. With the first conduction-type semiconductor made to epitaxially grow selectively in the groove after a thin oxidizing film is formed on the side face, both the oxidizing film and semiconductor layers in the third region are selectively removed to form a groove. Besides, with the second conduction-type semiconductor made to epitaxially grow selectively in the groove after a thin oxidizing film being formed on the side face, a high concentration layer is composed to form electrodes at the parts for the drain and source regions in each channel.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 不発明は半導体装置に関し、より詳しくは１ｌｌＡ　ｑ
ｌｋゲートトランジスタおよびその製造方法に関する０
〔従来の技術〕 絶縁ゲートトランジスタ、時に相袖型絶碌ゲートトラン
ジスタを用いた集積回路（以下、ＣＭＯ８ＩＣというン
は、低消費電力等の大きな特徴を有している。一般的な
０ＭＯ８ＩＣの構成を第３図に示す。[Detailed Description of the Invention] [Industrial Application Field] The invention relates to semiconductor devices, more specifically 1llA q
0 about lk gate transistor and its manufacturing method
[Prior art] Integrated circuits (hereinafter referred to as CMO8ICs) using insulated gate transistors, sometimes phase-sleeved insulated gate transistors, have major features such as low power consumption. It is shown in Figure 3.

すなわち、Ｎ型半尋体基板３０１内にＰワエ・・領域と
呼ばれるＰ型不純物拡敵領域３０２が形成され、このＰ
型不純物拡散領域３０２内にＮ型ＭＯ８）ランジスタの
ドレイン及びソース３０４が形成され、基板側にはＰ型
ＭＯ８トランジスタのドレイン及びソース３０３が形成
されている。両トランジスタのゲート３０５は多結晶シ
リコン又はアルミニウム等の金楓で形成される。ざらに
、絶縁酸化膜３０６は選択酸化技術等で形成され、合ソ
ース・ドレイン・ゲートには電極３０７が形成される。That is, a P-type impurity expansion region 302 called a Pwae region is formed in the N-type semicircular substrate 301;
The drain and source 304 of an N-type MO8 transistor are formed in the type impurity diffusion region 302, and the drain and source 303 of a P-type MO8 transistor are formed on the substrate side. The gates 305 of both transistors are formed of polycrystalline silicon or gold maple such as aluminum. Roughly speaking, an insulating oxide film 306 is formed by selective oxidation technology or the like, and electrodes 307 are formed at the source, drain, and gate.

ここで基板３０１としてＰ型のものを用いても、Ｎ型拡
散領域３０２を形成して同様にＣＭＯ８半導体装置を構
１戎できる。Here, even if a P-type substrate is used as the substrate 301, a CMO8 semiconductor device can be constructed in the same manner by forming an N-type diffusion region 302.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の構造では、ゲート電極３０５によるチャ
ンネル電流が基板に対して横力向に流れる為に１高速動
作に最も影響を及ぼすチャンネル長はゲート３０５を形
成する為の写真食刻技術で限定される。しかし、現ｆ、
安定して写ＡＸ刻技術で形成できるチャンネル長は１μ
ｍ程度であシ、今後の筒速化に対応する１μｍ以下のゲ
ート長を安定して形成することが不可能である。加えて
、従来の構造では、寄生バイポーラ・トランジスターに
よるラッチ・アップ現象が発生する欠点がある０ 〔問題点を解決するための手段〕 本発明の半導体装置の攬造方法は、第１導電型の半導体
基板に第２専篭型の尚譲度第１饋域と第２導電型の低護
度第２憤域とを選択的に形成し。In the conventional structure described above, since the channel current due to the gate electrode 305 flows in the direction of lateral force with respect to the substrate, the channel length that most affects high-speed operation is limited by the photolithography technique used to form the gate 305. Ru. However, the current f,
The channel length that can be stably formed using Sha-AX engraving technology is 1μ.
However, it is impossible to stably form a gate length of 1 μm or less, which corresponds to future increases in cylinder speed. In addition, the conventional structure has the disadvantage that a latch-up phenomenon occurs due to a parasitic bipolar transistor. A second conductivity type low protection first region and a second conductivity type low protection second region are selectively formed on the semiconductor substrate.

該第２領域の内側に第１導電型の第３領域を形成する工
程と、基板全面に酸化膜、半導体ノーを順に形成する工
程と、半導体層を選択的に酸化して酸化膜に変える工程
と、第２領域上の酸化膜層と半導体層を選択的に＊り去
いて溝を形成する工程と、該溝の側面に薄い酸化膜を形
成した後に、該溝に選択的に第１導電型の半導体をエピ
タキシャル成長する工程と、前記第３領域の酸化膜層と
半導体層を選択的に取り去いて溝を形成し、該溝の側面
に薄い酸化膜を形成した後に、該碑に迅択的に第２導電
型の半導体をエピタキシャル成長する工程ト、谷チャン
ネルのドレイン及びソース狽域となる部分に高纜度層を
設け、電極を形成する工程から構成されている。A step of forming a third region of the first conductivity type inside the second region, a step of sequentially forming an oxide film and a semiconductor layer on the entire surface of the substrate, and a step of selectively oxidizing the semiconductor layer to convert it into an oxide film. a step of selectively removing* the oxide film layer and the semiconductor layer on the second region to form a groove; and after forming a thin oxide film on the side surfaces of the groove, selectively removing a first conductive layer in the groove; A step of epitaxially growing a type of semiconductor, selectively removing the oxide film layer and the semiconductor layer in the third region to form a groove, and forming a thin oxide film on the side surfaces of the groove, followed by a step of epitaxially growing a semiconductor layer on the monument. The method generally consists of a step of epitaxially growing a semiconductor of the second conductivity type, and a step of providing a high-strength layer in the portions that will become the drain and source regions of the valley channel to form electrodes.

〔実施例〕〔Example〕

久に、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will now be described with reference to the drawings.

第１図（ａ）乃至ｔｊ）は不発明の一実施例によるＣＭ
（ＪＳ　　ＩＣを製造工程順に示した断面図である。ま
ず、　ＮｌＪｌ手導体基板１０１に低戚度Ｐ型領域１０
２を形成し１次いで高訣度Ｐ型領域１０３を低濃度Ｐ型
領域１０２以外の部分に、高痕度Ｎ型頂域１０４を低濃
度Ｐ型領域１０２内へ形成する。各拡散領域のそれぞれ
の濃度は、１０３，１０４の濃度が１０１９〜１０”Ｃ
ｌ１Ｌ　’、　ｌ　０２の濃度は１０１６ｃ！ＩＬ−３
程度、基板１０１の濃度はｌ　Ｏ’　４　ｒ３程度であ
）、熱拡散又はイオン注入技術を用いて形成する（第１
図ａ）。FIG. 1(a) to tj) are commercials according to an embodiment of the non-invention.
(This is a sectional view showing the JSIC in the order of manufacturing steps.
Then, a high density P type region 103 is formed in a portion other than the low concentration P type region 102, and a high density N type top region 104 is formed in the low concentration P type region 102. The concentration of each diffusion region is 103,104 from 1019 to 10"C.
The concentration of l1L', l02 is 1016c! IL-3
The concentration of the substrate 101 is about lO' 4 r3), and is formed using thermal diffusion or ion implantation technology (the first
Diagram a).

全面に、３０００〜４０００Ａ程夏の１ｉ化膜１０５を
気相成長法等を用いて形成し、その上部に多結晶シリコ
ン膜１０６を形成する。この多結晶シリコン膜１０６の
膜厚はゲート長を医定し、１μｍ以下の所定の膜厚に設
定する（第１図り）０この後に、選択的に多結晶シリコ
ン膜１０６をα化し゛Ｃ１酸化膜１０７を形成する（第
１図Ｃ）。A 1i film 105 with a thickness of about 3000 to 4000 A is formed on the entire surface using a vapor phase growth method, and a polycrystalline silicon film 106 is formed on top of the 1i film 105. The film thickness of this polycrystalline silicon film 106 is set to a predetermined film thickness of 1 μm or less by medically determining the gate length (first diagram). After this, the polycrystalline silicon film 106 is selectively alphanized and C1 oxidized. A film 107 is formed (FIG. 1C).

全面に薄い酸化膜（１００〜５００Ａ）を形成した後に
Ｎ型不純物をイオン注入して、多結晶シリコン膜１０６
に導入する（第１図ｄ）。After forming a thin oxide film (100 to 500 A) on the entire surface, N-type impurity ions are implanted to form a polycrystalline silicon film 106.
(Fig. 1d).

熱処理を行ない多結晶シリコン膜１０６中の不純物一度
を一定にした後に、先ず＾濃匿Ｐ型饋域ｌＯ：３上の一
＋Ｍ晶シリコン膜１０６及び高濃度ＮＷ領域１０４上の
酸化膜１０７を選択的にＲＩＥを用いて異７ｊ性工、テ
ングを行ない、溝１０８を形成する。全体を酸化し溝部
分の側面に露出している多結晶シリコン膜を酸化し、再
び異カ性エツチングを行なうことにより、側壁のみに５
０〜５００八程鍵の膜厚のゲート酸化膜１５０を形成す
る（第１図ｅ）。After heat treatment is performed to make the impurity level in the polycrystalline silicon film 106 constant, first, the 1+M crystal silicon film 106 on the concentrated P-type region lO:3 and the oxide film 107 on the high concentration NW region 104 are selected. Then, a groove 108 is formed using RIE. By oxidizing the entire surface, oxidizing the polycrystalline silicon film exposed on the side surfaces of the groove portion, and then performing heterocrystalline etching again, 55% is applied to only the side walls.
A gate oxide film 150 having a thickness of about 0 to 500 mm is formed (FIG. 1e).

溝領域１０８にＮ型低濃度シリコ７層１０９゜１１０を
選択エピタキシャル成長法により形成する。ｂｉ、長後
、ぼ化を行ないエピタキシャル成長したシリコン層１０
９，１１０上に酸化膜を形成する（第１図ｆ）ｏ次に、
高磯度Ｐ型饋域１０３上の酸化！Ｉ！４１０７及び爾伽
匿Ｎ型頚域１０４上の多結晶シリコン膜１０６を選択的
に几ＩＥを用いて異方性エツチングを行ない溝１１１を
形成する０１１１１０８の場合と同様の方法で側面に５
０〜５００Ａのゲートば化膜となるべき鹸化禮１６０を
形成するＣＭ１図ｇ）。Seven N-type low concentration silicon layers 109° and 110 are formed in the groove region 108 by selective epitaxial growth. bi, silicon layer 10 epitaxially grown after long and blurring
9, 110 (FIG. 1f) o Next,
Oxidation on high-level P-type feeding area 103! I! 4107 and the polycrystalline silicon film 106 on the hidden N-type neck region 104 are selectively anisotropically etched using IE to form grooves 111.
CM1 (g) showing the formation of a saponification film 160 that is to become a gate film of 0 to 500A.

久にｎ４偵域Ｉｌｌに選択的にＰ緘低一度シリコン／ｆ
ｉ１１１２．１１３ｔ−エビター？７ヤル収長し、数比
を行なうことによジシリコン層１１２，１１３の上に酸
化膜を形成する（第１図ｈ）。Selectively low silicon/f in n4 reconnaissance area for a long time
i1112.113t-evitar? An oxide film is formed on the di-silicon layers 112 and 113 by performing a numerical ratio (FIG. 1h).

イ万ン注入技術を用いてＰＷ低低濃度職域１１２上部と
Ｎ型低濃度領域１０９の上部にＰ型筒一度領域１１４，
１１５をそＪ’Ｌぞれ形成する。家た同様に、Ｐ聖像ｆ
ｈ、度幀域１１３の上部と１ｑ型低線度領域１１０の上
部ＫＮ型Ｉ！１６礫度偵城１１６゜１１７をそれぞれ形
成する（第１図１）。Using the ion implantation technique, a P-type tube region 114 is placed in the upper part of the PW low-concentration work area 112 and the upper part of the N-type low-concentration region 109.
115 are formed respectively. Similarly, the P holy image f
h, KN-type I! above the high-intensity area 113 and above the 1q-type low-intensity area 110! 16-grained castles 116° and 117 are formed respectively (Fig. 1 1).

最後に領域１１４，１１５，１１６，１１７及Ｄ；１１
５と１１６の間の多結晶シリコン膜１０６上のは化膜を
選択的に取り去き、金楓を極１１８゜１１９．１２０，
１２１，１２２を形成して素子が完成する（第１図ｊ）
。Finally, areas 114, 115, 116, 117 and D; 11
The oxide film on the polycrystalline silicon film 106 between 5 and 116 is selectively removed, and the gold maple is coated at 118°, 119.120°,
121 and 122 are formed to complete the device (Fig. 1j)
.

ここで、電極１１８がＰチャタネ４ＭＯ８）ランジスタ
リソース、１１９は同トランジスタのドレインまた、電
極１２１はＮチャンネルＭＯＳトランジスタのドレイン
、１２２は同トランジスタソースに、電極１２０は共通
のゲートに相当する。Here, the electrode 118 corresponds to the transistor source, 119 corresponds to the drain of the same transistor, the electrode 121 corresponds to the drain of the N-channel MOS transistor, 122 corresponds to the source of the same transistor, and the electrode 120 corresponds to the common gate.

第２図は素子の半面構造である。前述の説明からも明ら
かなように、１（ｊ６は共通ケート部、１０３はＰチャ
タネ４ＭＯ８のソース部、１０２はＰウェル、１０４は
ＮチャンネルＭ（Ｊ８のソース部、１５０はＰチャンネ
ルのゲート［化膜、１６０はＩＮチャンネルＭＯ８のゲ
ート酸化膜、１１８．１１９はそれぞれＰチャタネ４Ｍ
Ｏ８のソース及びドレイン・コンタクト部、１２０は共
通ゲートのコンタクト部、１２１，１２２はそれぞれＮ
チャンネルＭＯ８のドレイン及ソース・コンタクト部で
ある。以上は、Ｎ型基板てついて述べたが、Ｐ型基板に
ついても同僚に適用することができる◇ 〔発明の効果〕 以上説明したとおり、本発明によれば、高度な写真策刻
茂術を用いろことなく、ゲート唄城の多結晶７リコン膜
の膜厚を制御することにより容易て、高速化に対応した
１μｍ以下のゲート長を実現ｃｉｆ能であり、カロえて
谷トランジスターのドレインがそれぞれフェルと半導体
基板から離れている為に、寄生トランジスター効果が押
えらｎ、ラッチ・アップ現象が発生しにくい縦１ｉｃｙ
ｒｏＳ牛導体装置を提供できる。FIG. 2 shows a half-plane structure of the device. As is clear from the above description, 1 (j6 is the common gate part, 103 is the source part of P channel MO8, 102 is the P well, 104 is the N channel M (source part of J8, 150 is the gate of P channel) 160 is the gate oxide film of IN channel MO8, 118 and 119 are P chatane 4M, respectively.
Source and drain contacts of O8, 120 is a common gate contact, 121 and 122 are N
This is the drain and source contact portion of the channel MO8. The above has been described for N-type substrates, but it can also be applied to P-type substrates ◇ [Effects of the Invention] As explained above, according to the present invention, advanced photo engraving techniques can be used. By controlling the thickness of the polycrystalline 7-licon film in the gate, it is easy to achieve a gate length of 1 μm or less, which is compatible with high-speed operation. Because it is far from the semiconductor substrate, the parasitic transistor effect is suppressed, and the latch-up phenomenon is less likely to occur.
We can provide roS conductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜ｌｊ）は不発明の一実施例を説明するた
めに工程順に示した＠面図、第２図は本発明の実り例に
おける平面構造図、第３図は従来の牛轡体装置の製造方
法を説明するための断■図である。Figures 1 (a) to lj) are @ side views shown in the order of steps to explain an embodiment of the invention, Figure 2 is a plan view of the structure of a fruitful example of the present invention, and Figure 3 is a conventional cow. FIG. 3 is a cross-sectional view for explaining a method of manufacturing the housing device.

Claims (2)

【特許請求の範囲】[Claims] （１）ソースおよびドレイン領域の一方となる一導電型
の第１領域と、該第１領域上に選択的に形成された逆導
電型の柱状半導体領域と、該柱状半導体領域の上部に形
成されたソースおよびドレイン領域の他方となる前記一
導電型の第２領域と、前記柱状半導体領域の側面に形成
されたゲート絶縁膜と、この絶縁膜上に形成されたゲー
ト電極とを有することを特徴とする半導体装置。(1) A first region of one conductivity type that becomes one of the source and drain regions, a columnar semiconductor region of the opposite conductivity type selectively formed on the first region, and a columnar semiconductor region formed on the top of the columnar semiconductor region. the second region of one conductivity type, which is the other of the source and drain regions; a gate insulating film formed on a side surface of the columnar semiconductor region; and a gate electrode formed on the insulating film. semiconductor device. （２）ソースおよびドレインの一方となる一導電型の第
１領域上に絶縁膜を介して半導体層を形成する工程と、
前記半導体層を選択的に取り去いて溝を形成する工程と
、該溝の側面にゲート絶縁膜を形成し、該溝内に逆導電
型の半導体を選択エピタキシャル成長する工程と、この
エピタキシャル層の表面部分にソースおよびドレインの
他方となる前記一導電型の第２領域を形成する工程とを
有することを特徴とする半導体の製造方法。(2) forming a semiconductor layer on a first region of one conductivity type, which becomes one of a source and a drain, with an insulating film interposed therebetween;
a step of selectively removing the semiconductor layer to form a groove; a step of forming a gate insulating film on the side surface of the groove; and selectively epitaxially growing a semiconductor of the opposite conductivity type in the groove; and a step of forming a groove on the surface of the epitaxial layer. A method of manufacturing a semiconductor, comprising the step of forming a second region of one conductivity type, which becomes the other of a source and a drain, in a portion thereof.