JPS6239830B2 - - Google Patents
Info
- Publication number
- JPS6239830B2 JPS6239830B2 JP55117595A JP11759580A JPS6239830B2 JP S6239830 B2 JPS6239830 B2 JP S6239830B2 JP 55117595 A JP55117595 A JP 55117595A JP 11759580 A JP11759580 A JP 11759580A JP S6239830 B2 JPS6239830 B2 JP S6239830B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- emitter
- base
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、高速度モノリシツク・ダーリント
ン・トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high speed monolithic Darlington transistors.
モノリシツク・ダーリントン・トランジスタ
（以下MDTと略記する）は、一般に第１図に示す
様に第１のトランジスタTr1のコレクタと第２の
トランジスタTr2のコレクタおよび第１のトラン
ジスタTr1のエミツタと第２のトランジスタTr2
のベースがそれぞれ共通接続され、また第１のト
ランジスタTr1のベースと第２のトランジスタ
Tr2のベースとの間に抵抗R1が接続され、第２の
トランジスタTr2のベース・エミツタ間に抵抗R2
が接続され、さらに第２トランジスタTr2のエミ
ツタ・コレクタ間にダイオードD1が接続される
とともに、ベース電極Ｂ、エミツタ電極Ｅ、コレ
クタ電極Ｃを具備する回路が単一の半導体基板へ
１体的に作り込まれた構成となつている。 A monolithic Darlington transistor (hereinafter abbreviated as MDT) generally includes a collector of a first transistor Tr 1 , a collector of a second transistor Tr 2, an emitter of the first transistor Tr 1 , and a transistor as shown in FIG. 2 transistors Tr 2
The bases of the first transistor Tr1 and the second transistor Tr1 are connected in common.
A resistor R 1 is connected between the base of Tr 2 , and a resistor R 2 is connected between the base and emitter of the second transistor Tr 2 .
A diode D1 is connected between the emitter and collector of the second transistor Tr2 , and a circuit including a base electrode B, an emitter electrode E, and a collector electrode C is integrated onto a single semiconductor substrate. It has a built-in structure.
この様なMDTを製造するには、従来一般には
第３図に示す様に、まずトランジスタTr1および
Tr2のコレクタ領域１を基体として、その上にベ
ース領域２を形成し続いてトランジスタTr1のエ
ミツタ領域３とトランジスタTr2のエミツタ領域
４とを形成する。このエミツタ領域形成時にトラ
ンジスタTr1のエミツタ下に抵抗R1に相当する領
域５が同時に形成される。トランジスタTr2のエ
ミツタ領域４の形成時にエミツタとなる領域の一
部をベース領域のままで残す事によつてエミツタ
下に抵抗R2に相当する領域６が同時に形成さ
れ、かつダイオードD1７も形成される。 To manufacture such an MDT, conventionally, as shown in Figure 3, first the transistors Tr1 and
Using collector region 1 of Tr 2 as a base, base region 2 is formed thereon, and then emitter region 3 of transistor Tr 1 and emitter region 4 of transistor Tr 2 are formed. At the time of forming this emitter region, a region 5 corresponding to the resistor R1 is simultaneously formed under the emitter of the transistor Tr1 . When forming the emitter region 4 of the transistor Tr 2 , by leaving a part of the region that will become the emitter as the base region, a region 6 corresponding to the resistor R 2 is simultaneously formed under the emitter, and the diode D 1 7 is also formed. It is formed.
ベース電極Ｂに相当するアルミ電極８、トラン
ジスタTr1のエミツタとトランジスタTr2のベー
スとを接続する内部アルミ電極９、およびエミツ
タ電極Ｅに相当するアルミ電極１０は、周知の写
真蝕刻法を用いて形成され、コレクタ電極Ｃすな
わち１１はウエハー裏面に形成される。１２は絶
縁膜である。 An aluminum electrode 8 corresponding to the base electrode B, an internal aluminum electrode 9 connecting the emitter of the transistor Tr 1 and the base of the transistor Tr 2 , and an aluminum electrode 10 corresponding to the emitter electrode E were formed using a well-known photolithography method. A collector electrode C or 11 is formed on the back surface of the wafer. 12 is an insulating film.
この様にしてつくられた従来のMDTでは、ス
イツチング動作でONからOFFへの切り替え時に
ベース・エミツタ間が逆バイアスされるとTr1の
ベース・エミツタ間には電流が流れないため、
Tr2のベース領域に蓄積されたキヤリアは、Ｒ１
を通じて徐々にMDTのベースへ流出するだけで
あり、Ｒ１が大きいときにはキヤリアはすみやか
に外部へ流出できない。その結果スイツチング速
度が遅くなる欠点がある。 In the conventional MDT made in this way, when the base and emitter are reverse biased when switching from ON to OFF during switching operation, no current flows between the base and emitter of Tr 1 .
The carrier accumulated in the base area of Tr 2 is R1
If R1 is large, the carrier cannot flow out to the outside quickly. As a result, there is a drawback that the switching speed becomes slow.
これを改良するために、第３図で示すようにダ
イオードＤ２をTr1のエミツタ・ベース間に挿入
する方法が知られている。しかしこのダイオード
D2は他の回路要素のように単一の半導体基体内
へ一体的に作り込むことができないため外部接続
によつて回路中へ挿入する必要があり、量産性、
信頼性の面で必ずしも十分とはいえない。 In order to improve this, a method is known in which a diode D2 is inserted between the emitter and base of Tr 1 , as shown in FIG. But this diode
Unlike other circuit elements, D2 cannot be integrated into a single semiconductor substrate, so it must be inserted into the circuit through external connections, which reduces mass productivity and
It is not necessarily sufficient in terms of reliability.
本発明は、上記の不都合を除いたダイオード内
蔵型のモノリシツク・ダーリントン・トランジス
タを提供するものである。 The present invention provides a monolithic Darlington transistor with a built-in diode that eliminates the above disadvantages.
以下本発明を図面により詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第４図、第５図は本発明にかかるモノリシツ
ク・ダーリントン・トランジスタの一実施例を示
すもので、第４図はMDTの断面図、第５図ａお
よびｂは第１のトランジスタTr1のエミツタ・ベ
ース間に内蔵されたダイオードの平面図および断
面図である。 4 and 5 show an embodiment of the monolithic Darlington transistor according to the present invention, FIG. 4 is a cross-sectional view of the MDT, and FIGS. 5a and 5b show the emitter of the first transistor Tr1. - A plan view and a cross-sectional view of a diode built in between the bases.
第４図において、１はトランジスタTr1および
Tr2のコレクタ領域となるべく基体、２はトラン
ジスタTr1およびTr2のベース領域、３はトラン
ジスタTr1のエミツタ領域、４はトランジスタ
Tr2のエミツタ領域、５は抵抗R1を形成する抵抗
領域、６は抵抗R2を形成する抵抗領域、７はダ
イオードD1領域、８はベース電極、９′はトラン
ジスタTr1のエミツタ領域とダイオードD2のアノ
ードを結び、かつトランジスタTr1のエミツタ領
域とトランジスタTr2のベース領域を結ぶ内部配
線、１０はエミツタ電極、１１はコレクタ電極、
１２は絶縁膜、１３はダイオードD2のカソード
領域、１４はダイオードD2のアノード領域であ
る。 In FIG. 4, 1 is the transistor Tr 1 and
The base is preferably the collector region of Tr 2 , 2 is the base region of transistors Tr 1 and Tr 2 , 3 is the emitter region of transistor Tr 1 , and 4 is the transistor
The emitter region of Tr 2 , 5 the resistor region forming the resistor R 1 , 6 the resistor region forming the resistor R 2 , 7 the diode D 1 region, 8 the base electrode, and 9' the emitter region of the transistor Tr 1 . internal wiring that connects the anode of the diode D 2 and also connects the emitter region of the transistor Tr 1 and the base region of the transistor Tr 2 ; 10 is an emitter electrode; 11 is a collector electrode;
12 is an insulating film, 13 is a cathode region of diode D2 , and 14 is an anode region of diode D2 .
また第５図に示す様に、ベース電極８はダイオ
ードD2のカソード領域１３とトランジスタTr1の
ベース領域２を表面接合部全域で短絡している。
またダイオードD1のアノード領域１４とトラン
ジスタTr1のエミツタ領域３を結ぶ内部配線９は
ズース電極８の上部を通る。したがつて図示する
ように絶縁膜１２を介して多層線構造とするかま
たは内部配線９をワイヤボンドとするいずれかの
構成となる。 Further, as shown in FIG. 5, the base electrode 8 short-circuits the cathode region 13 of the diode D 2 and the base region 2 of the transistor Tr 1 over the entire surface junction.
Further, an internal wiring 9 connecting the anode region 14 of the diode D 1 and the emitter region 3 of the transistor Tr 1 passes over the Zuss electrode 8 . Therefore, as shown in the figure, either a multilayer wire structure is formed with the insulating film 12 interposed therebetween, or the internal wiring 9 is wire bonded.
この様に電極８が領域２および３と表面接合部
全域で短絡することにより、領域１４，１３，２
の３領域で形成されるPNPトランジスタ動作およ
び領域１４，１３，２，１の４領域で形成される
PNPNサイリスタ動作の双方が阻止されるところ
となり、領域１３，１４の間に形成されるPN接
合のみが良好なダイオード特性を有する事にな
る。 In this way, the electrode 8 is short-circuited with the regions 2 and 3 across the surface joints, so that the regions 14, 13, 2
The PNP transistor operation is formed by three regions, and the four regions are regions 14, 13, 2, and 1.
Both PNPN thyristor operations will be blocked, and only the PN junction formed between regions 13 and 14 will have good diode characteristics.
この様にして形成されたMDT内のダイオード
D2の特性を第６図に示し、第７図にスイツチン
グ特性を示した。 Diode in MDT formed in this way
The characteristics of D2 are shown in FIG. 6, and the switching characteristics are shown in FIG.
第７図に示すように本発明MDTは逆方向エミ
ツタ・ベース電流（−ＩB）に比例してスイツチ
ング速度が早くなつており、この結果高速度
MDTが可能である。 As shown in Fig. 7, the MDT of the present invention has a switching speed that increases in proportion to the reverse emitter-base current (-I B ), resulting in high speed switching.
MDT is possible.
以上、述べたように本発明によれば従来の
MDTの製造工程にダイオードD2領域形成工程を
加えるでだでけで第７図に示す様に外部接続によ
りダイオードを付加したMDTと同一の効果が奏
され、スイツチング速度および信頼性の面で非常
に優れた高速度モノリシツク・ダーリントン・ト
ランジスタを得ることがきる。本発明の実施例図
において導電型のすべて逆の導電型すなわちＮ型
→Ｐ型、Ｐ型→Ｎ型のようにすることは全く等価
であり、本発明に含まれるものである。 As described above, according to the present invention, the conventional
By simply adding the diode D two region forming process to the MDT manufacturing process, as shown in Figure 7, the same effect as an MDT with externally connected diodes can be achieved, resulting in extremely high switching speed and reliability. A high speed monolithic Darlington transistor with excellent performance can be obtained. In the embodiment diagrams of the present invention, it is completely equivalent to change the conductivity types to reverse conductivity types, such as N type → P type, P type → N type, and is included in the present invention.
第１図は従来のモノリシツク・ダーリントン・
トランジスタの等価回路図、第２図は従来のモノ
リシツク・ダーリントン・トランジスタの断面
図、第３図はスイツチング速度を早めるためにダ
イオードを挿入したダーリントン・トランジスタ
の等価回路図、第４図は本発明の一実施例にかか
るモノリシツク・ダーリントン・トランジスタの
断面図、第５図ａ，ｂは本発明にかかる同トラン
ジスタのダイオード部の平面図および断面図、第
６図は本発明のダイオード特性図、第７図は従来
と本発明のスイツチング速度の特性比較図であ
る。
１……コレクタ領域となる半導体基体、２……
ベース領域、１３……ダイオードのカソード領
域、１４……ダイオードのアノード領域。
Figure 1 shows the conventional monolithic Darlington
Equivalent circuit diagrams of transistors. Figure 2 is a cross-sectional view of a conventional monolithic Darlington transistor, Figure 3 is an equivalent circuit diagram of a Darlington transistor with a diode inserted to increase switching speed, and Figure 4 is a cross-sectional diagram of a conventional monolithic Darlington transistor. A cross-sectional view of a monolithic Darlington transistor according to an embodiment, FIGS. The figure is a comparison diagram of the switching speed characteristics of the conventional and the present invention. 1... Semiconductor base serving as a collector region, 2...
Base region, 13... cathode region of the diode, 14... anode region of the diode.
Claims (1)
において、前段トランジスタのベース領域中にエ
ミツタ領域と分離させてこれと同一導電型の領域
が作り込まれ、さらに同領域中に前記ベース領域
と同一導電型の領域が作り込まれるとともに前記
ベース領域と同一導電型の領域と前段トランジス
タのエミツク領域とを短絡し、さらに前記エミツ
タ領域と同一導電型の領域と前段トランジスタの
ベース領域との間に形成されるPN接合の表面接
合部全域を短絡して、前段トランジスタのエミツ
タ・ベース間に介在するダイオードを形成した事
を特徴としたモノリシツク・ダーリントン・トラ
ンジスタ。1. In a monolithic Darlington transistor, a region of the same conductivity type as the emitter region is formed in the base region of the previous transistor, separated from the emitter region, and a region of the same conductivity type as the base region is created in the same region. A surface junction of a PN junction is formed between the region having the same conductivity type as the emitter region and the base region of the preceding transistor. A monolithic Darlington transistor characterized by short-circuiting the entire region to form a diode interposed between the emitter and base of the preceding transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55117595A JPS5740970A (en) | 1980-08-25 | 1980-08-25 | Monolithic darlington transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55117595A JPS5740970A (en) | 1980-08-25 | 1980-08-25 | Monolithic darlington transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5740970A JPS5740970A (en) | 1982-03-06 |
| JPS6239830B2 true JPS6239830B2 (en) | 1987-08-25 |
Family
ID=14715694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55117595A Granted JPS5740970A (en) | 1980-08-25 | 1980-08-25 | Monolithic darlington transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5740970A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5987157U (en) * | 1982-12-01 | 1984-06-13 | 株式会社三社電機製作所 | darlington transistor |
| JPS59110166A (en) * | 1982-12-15 | 1984-06-26 | Sansha Electric Mfg Co Ltd | Darlington transistor |
-
1980
- 1980-08-25 JP JP55117595A patent/JPS5740970A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5740970A (en) | 1982-03-06 |
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