JPS6235693A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPS6235693A
JPS6235693A JP17504785A JP17504785A JPS6235693A JP S6235693 A JPS6235693 A JP S6235693A JP 17504785 A JP17504785 A JP 17504785A JP 17504785 A JP17504785 A JP 17504785A JP S6235693 A JPS6235693 A JP S6235693A
Authority
JP
Japan
Prior art keywords
circuit board
conductive
substrate
conductive material
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17504785A
Other languages
Japanese (ja)
Inventor
末広 照朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP17504785A priority Critical patent/JPS6235693A/en
Publication of JPS6235693A publication Critical patent/JPS6235693A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は新規な構成の回路基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit board with a novel configuration.

〔従来の技術〕[Conventional technology]

現在、プリント基板等の回路基板は主にエツチング法や
アディティブ法を用いて製作されるが、導電パターンの
線幅は、普通、エツチング法で20(lum程度1アデ
ィティブ法で100〜150μmのものが得られる。然
しなから、近年における実装技術の細密化や装置の小型
化に伴い回路基板の小型化が要求され、ディスクリート
IC等では上記線幅は100μmを超えて細くされるこ
とが要求されている。ところで、この要求に応じるため
、従来より特に上記アディティブ法を利用して種々の試
みがなされているが、このアディティブ法においては基
板材料の一つとしてセラミックスが多く用いられる。こ
の場合、例えば、セラミック回路基板は薄いシート状の
セラミック板上に導線部分を印刷して焼成することによ
り作られる。
Currently, circuit boards such as printed circuit boards are mainly manufactured using the etching method or the additive method, but the line width of the conductive pattern is usually about 20 μm using the etching method and 100 to 150 μm using the additive method. However, in recent years, with the miniaturization of packaging technology and miniaturization of devices, there has been a demand for smaller circuit boards, and for discrete ICs, etc., the line width is required to be thinner than 100 μm. By the way, in order to meet this demand, various attempts have been made in the past, especially using the above-mentioned additive method, but in this additive method, ceramics are often used as one of the substrate materials.In this case, for example, , Ceramic circuit boards are made by printing conductive wires on a thin sheet-like ceramic plate and firing it.

即ち、微粉化された導体粉をバインダーと共に印刷し、
電気抵抗を下げるために金属粉が焼結せしめられる。又
導電部分をメッキにより作成する方法もある。即ち、例
えば、セラミック板に適当な活性化を施すことによりメ
ッキを析出させて導電パターンを作成する。この場合、
基板の全面にメッキを析出させて後導電部分を残してエ
ツチングする方法と、導電部分にのみメッキを析出させ
る方法とがある。
That is, by printing pulverized conductor powder together with a binder,
Metal powder is sintered to reduce electrical resistance. There is also a method of creating the conductive part by plating. That is, for example, a conductive pattern is created by appropriately activating a ceramic plate to deposit plating. in this case,
There is a method in which plating is deposited on the entire surface of the substrate and then etched leaving the conductive portions, and a method in which plating is deposited only on the conductive portions.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで上記前者の作成方法によるプリント基板は導電
部分即ち回路部分の線幅は印刷精度によって決定される
ため、得られる線幅の限界値は100μm程度であり、
又上記後者の何れの作成方法によるプリント基板も印刷
工程を経るため同程度の線幅のものしか得られず、而も
後者の場合は基板との接着力が弱く実用上問題があった
By the way, the line width of the conductive portion, that is, the circuit portion of the printed circuit board manufactured by the above-mentioned former manufacturing method is determined by the printing accuracy, so the limit value of the line width that can be obtained is about 100 μm.
Furthermore, since the printed circuit boards manufactured by either of the latter methods described above go through a printing process, only line widths of approximately the same degree can be obtained, and in the latter case, the adhesion to the substrate is weak, which poses a practical problem.

本発明は、かかる問題点に鑑み、100μm以下の極め
て細い線幅の導電部分が均−且つ高精度で得られるよう
になした回路基板を提供することを目的とする。
SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a circuit board in which conductive portions having an extremely narrow line width of 100 μm or less can be obtained uniformly and with high precision.

〔問題点を解決するための手段及び作用〕本発明による
回路基板においては、導電パターンが電気絶縁性のシー
ト状基板材料の表面に溝として形成されていて、この溝
内に導電材料が充填されている。基板材料としてはセラ
ミックシートやプラスチックシートが用いられ、導電゛
材料としては銅、ニッケル等の金属が用いられる。
[Means and effects for solving the problem] In the circuit board according to the present invention, the conductive pattern is formed as a groove on the surface of the electrically insulating sheet-like substrate material, and the groove is filled with a conductive material. ing. A ceramic sheet or a plastic sheet is used as the substrate material, and a metal such as copper or nickel is used as the conductive material.

〔実施例〕〔Example〕

以下、基板材料としてセラミックを使用した場合を例に
挙げて本発明を具体的に説明する。第1図において、1
は回路パターンに対応する所定深さの溝1aを形成した
セラミック基板、2は溝la内に充填された銅、ニッケ
ル等の導電材料であって、溝1aは第2図に明示された
如く実質上基板1の表面に向って広がる台形をなしてい
ることが必要である。即ち、溝1aの対向側面は平面で
あっても球面又は楕円面の一部であってもよいが、その
側面頂角θ、は90°以上、基板表面と溝側面とのなす
角即ち切点角θ2は90゛以下であることが必要である
Hereinafter, the present invention will be specifically explained using an example in which ceramic is used as the substrate material. In Figure 1, 1
2 is a ceramic substrate in which a groove 1a of a predetermined depth corresponding to a circuit pattern is formed; 2 is a conductive material such as copper or nickel filled in the groove 1a; It is necessary that it has a trapezoidal shape that spreads toward the surface of the upper substrate 1. That is, the opposing side surfaces of the groove 1a may be flat or part of a spherical or ellipsoidal surface, but the apex angle θ of the side surface is 90° or more, the angle between the substrate surface and the groove side surface, that is, the cutting point. It is necessary that the angle θ2 is 90° or less.

次にセラミック基板1の製作方法について説明する。Next, a method for manufacturing the ceramic substrate 1 will be explained.

通常、セラミックは切込み加工が難しく、切削により溝
1aを形成するのは困難であるので、原料段階即ち所謂
グリーンシートの段階で溝加工を行う、この溝加工は、
プラスチックフィルムキャリア上に載置されたグリーン
シートに、回路パターンに相当する部分を凸にその他の
部分を凹となしたスタンパ−を圧着することにより行わ
れる。
Normally, it is difficult to cut ceramics, and it is difficult to form the grooves 1a by cutting. Therefore, the groove processing is performed at the raw material stage, that is, the so-called green sheet stage.
This is done by pressing a stamper, which has a convex part corresponding to the circuit pattern and a concave part in other parts, onto a green sheet placed on a plastic film carrier.

スタンパ−としては、ロール状のものと平板状のものが
あり、金属製、プラスチック製、ゴム製等多種類の材質
のものが使用され得る。これらのスタンパ−は、通常の
印刷用凸版の製作方法を応用して作成されるが、パター
ンが高密度で高精度を要求される場合は、高精度紫外線
露光焼付けにより得られた凸版を電鋳によりニッケル等
の高硬度金属に転写することにより作成される。又かか
るスタンパ−はレーザー感応型レジストによっても得る
ことができるが、レーザー光を使用する場合は、溝断面
の台形を自由に選ぶことができるばかりか、回路網作成
用プログラムデータを直接レーザー駆動用データとして
使用できると云う利点がある6以上はグリーンシートを
使用して回路基板を製作する方法について説明したが、
この回路基板はセラミック原料とバインダーとの混練物
を使用して製作することもできる。この場合は、上記混
線物を、前記スタンパ−を組込んだ金型に流し込むか或
いは該金型を利用して射出成形又は圧縮成形するかした
後、これらを焼成することによって得られる。
Stampers include roll-shaped stampers and flat-plate stampers, and stampers made of various materials such as metal, plastic, and rubber can be used. These stampers are created by applying the production method of ordinary letterpress printing plates, but if the pattern requires high density and high precision, a letterpress plate obtained by high-precision ultraviolet exposure baking can be electroformed. It is created by transferring it onto a high hardness metal such as nickel. Such a stamper can also be obtained using a laser-sensitive resist, but when using a laser beam, not only can the trapezoidal cross section of the groove be freely selected, but also the program data for creating the circuit network can be directly used to drive the laser. Above 6 explained how to manufacture circuit boards using green sheets, which have the advantage of being able to be used as data.
This circuit board can also be manufactured using a mixture of ceramic raw materials and a binder. In this case, the mixed material is poured into a mold incorporating the stamper, or injection molded or compression molded using the mold, and then fired.

次に導電材料2の溝la内への充填方法について説明す
る。
Next, a method of filling the groove la with the conductive material 2 will be described.

一般に導電材料2としては銅、ニッケル等の金属が用い
られるが、これらの金属は、上記の如くして得られたセ
ラミック基板1の表面を例えば塩化スズ及び塩化パラジ
ウム等を用いて活性化させた後、無電解メッキ法により
表面全体若しくは必要箇所へ部分的に析出させることに
より、溝la内へ充填される。この際、金属層の厚みを
充分なものにする必要がある場合は、電解メッキ法を併
用すれば良い、このほか、導電材料2をala内へ充填
するには、蒸着法、スパッター法等の気相法を用いても
よいし、金属ペースト、アマルガム等を直接充填する方
法を用いてもよいが、気相法を利用する場合には電解メ
ッキ法を組合せて金属層の充分な厚さを確保するように
することもできる。又金属ペーストやアマルガム等を使
用する場合、硬化、 ?fI融等の工程を加えても線幅
精度に影響を及ぼすことはない。
Metals such as copper and nickel are generally used as the conductive material 2, and these metals can be used by activating the surface of the ceramic substrate 1 obtained as described above using, for example, tin chloride or palladium chloride. Thereafter, by electroless plating, it is deposited over the entire surface or partially at necessary locations, thereby filling the grooves la. At this time, if it is necessary to make the metal layer sufficiently thick, electrolytic plating may be used in combination.In addition, vapor deposition, sputtering, etc. may be used to fill the ala with the conductive material 2. A vapor phase method may be used, or a method of directly filling metal paste, amalgam, etc. may be used, but when using a vapor phase method, it is necessary to combine it with an electrolytic plating method to obtain a sufficient thickness of the metal layer. It is also possible to secure it. Also, when using metal paste or amalgam, etc., hardening or ? Even if processes such as fI melting are added, line width accuracy is not affected.

かくして得られた導電材料付きセラミック板は、溝部に
対応する部分以外の表面部分に付着している導電材料を
除去することにより完成する。導電材料の除去は、研削
1機械研摩、エツチング51を解研摩等の適宜手段によ
り行われる。
The thus obtained ceramic plate with conductive material is completed by removing the conductive material adhering to the surface portions other than the portions corresponding to the grooves. The conductive material is removed by appropriate means such as mechanical polishing (grinding 1) and depolishing (etching 51).

以上実施例では、基板材料としてセラミックを用いた場
合について説明したが、本発明はこれに限定されるもの
ではなく、このほか射出成形可能な耐熱性可塑性及び熱
硬化性高分子材料、射出成形又は圧縮成形によるフォー
ミング可能な無機材料から選択される適宜の材料が使用
され得る。
In the above embodiments, the case where ceramic is used as the substrate material has been explained, but the present invention is not limited to this. Any suitable material selected from inorganic materials that can be formed by compression molding may be used.

尚、実験によれば、30μmの線幅で且つ30μmの厚
さをもつ導電パターンを極めて高い再現性を以って得る
ことができた。
According to experiments, it was possible to obtain a conductive pattern with a line width of 30 μm and a thickness of 30 μm with extremely high reproducibility.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、導電部分の線幅及び線間隔を極めて小
さく且つ均質に製作することができ、従って窩密度配線
可能で而も窩精度の配線回路網を実現し得る回路基板を
提供することができる。又本発明によれば、基板の内部
に導電部分がめり込んでいる構造をなしているため、基
板と導電部分との結合力が強く如何なる使用条件の下で
もR型部分が基板から剥離するようなことはなくて長期
間の使用に耐え得るばかりか、基板表面と導電部分の表
面とが同一平面をなしているため、実装部品を確実且つ
精度よく装着することができると云う利点がある。更に
本発明によれば、印刷、焼付け、焼成、溶融、エンチン
グ等の寸法を不安定にする要素をもつ工程を経ることな
く比較的少ない工程で仕上げることができるため、小型
化が容易で而も低コストで製作し得ると云う利点がある
According to the present invention, it is possible to provide a circuit board in which the line width and line spacing of conductive parts can be made extremely small and uniform, and therefore, it is possible to realize a wiring network with hole density wiring and hole precision. I can do it. Further, according to the present invention, since the conductive portion is recessed into the inside of the substrate, the bonding force between the substrate and the conductive portion is strong and the R-shaped portion will not peel off from the substrate under any usage conditions. Not only can it withstand long-term use, but also the board surface and the surface of the conductive part are on the same plane, so there is an advantage that the mounted components can be mounted reliably and accurately. Furthermore, according to the present invention, it is possible to finish with a relatively small number of steps without going through processes that have elements that make the dimensions unstable, such as printing, baking, firing, melting, and etching, so miniaturization is easy. It has the advantage that it can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る回路基板の一実施例を示す断面図
、第2図は第1図の部分拡大図である。 1・・・・基板材料、1a0.・・溝、2・・・・導電
材料。
FIG. 1 is a sectional view showing an embodiment of a circuit board according to the present invention, and FIG. 2 is a partially enlarged view of FIG. 1. 1...Substrate material, 1a0. ... Groove, 2... Conductive material.

Claims (3)

【特許請求の範囲】[Claims] (1)電気絶縁性の基板材料に回路パターンに対応する
溝を形成し、該溝内に導電性材料を充填して成る回路基
板。
(1) A circuit board formed by forming a groove corresponding to a circuit pattern in an electrically insulating substrate material and filling the groove with a conductive material.
(2)基板材料としてセラミックスが、又導電性材料と
して金属が用いられている、特許請求の範囲(1)に記
載の回路基板。
(2) The circuit board according to claim (1), wherein ceramic is used as the substrate material and metal is used as the conductive material.
(3)基板材料としてプラスチックスが、又導電性材料
として金属が用いられている、特許請求の範囲(1)に
記載の回路基板。
(3) The circuit board according to claim (1), wherein plastic is used as the substrate material and metal is used as the conductive material.
JP17504785A 1985-08-09 1985-08-09 Circuit board Pending JPS6235693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17504785A JPS6235693A (en) 1985-08-09 1985-08-09 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17504785A JPS6235693A (en) 1985-08-09 1985-08-09 Circuit board

Publications (1)

Publication Number Publication Date
JPS6235693A true JPS6235693A (en) 1987-02-16

Family

ID=15989296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17504785A Pending JPS6235693A (en) 1985-08-09 1985-08-09 Circuit board

Country Status (1)

Country Link
JP (1) JPS6235693A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104187A (en) * 1989-08-28 1991-05-01 Internatl Business Mach Corp <Ibm> Pattern writing on substrate
JPH06140742A (en) * 1992-10-29 1994-05-20 Canon Inc Printed-circuit board and manufacture thereof
JPH1168288A (en) * 1997-08-21 1999-03-09 Matsushita Electric Ind Co Ltd Circuit board and production thereof
JP2002204043A (en) * 2000-10-31 2002-07-19 Kyocera Corp Circuit board and its manufacturing method
JP2005005721A (en) * 2003-06-12 2005-01-06 Samsung Electronics Co Ltd Wiring board for semiconductor package, its producing process and semiconductor package utilizing it
JP2006066637A (en) * 2004-08-26 2006-03-09 Murata Mfg Co Ltd Manufacturing method of ceramic multilayer substrate and pressing die used therefor
JP2010052419A (en) * 2008-08-29 2010-03-11 Samsung Electro-Mechanics Co Ltd Methods for manufacturing ceramic green sheet and multilayer ceramic circuit board using the same
JP2012028735A (en) * 2010-06-24 2012-02-09 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2013038415A (en) * 2011-08-05 2013-02-21 Samsung Electro-Mechanics Co Ltd Thin film electrode ceramic substrate and method for producing the same
WO2014141492A1 (en) 2013-03-11 2014-09-18 日本碍子株式会社 Circuit substrate
JP2015050259A (en) * 2013-08-30 2015-03-16 京セラ株式会社 Semiconductor element mounting substrate and semiconductor device comprising the same
CN105916309A (en) * 2016-06-30 2016-08-31 广德宝达精密电路有限公司 Method for levelling conductive pattern and substrate in PCB
JP2020177950A (en) * 2019-04-15 2020-10-29 河村産業株式会社 Transparent conductive circuit board, manufacturing method thereof, usage method, and optical sensor

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55127094A (en) * 1979-03-26 1980-10-01 Suwa Seikosha Kk Circuit board
JPS55141786A (en) * 1979-04-20 1980-11-05 Hitachi Ltd Method of forming infinitesimal pattern
JPS56120191A (en) * 1980-02-27 1981-09-21 Tamura Electric Works Ltd Pattern device structure and method of mounting same
JPS5785289A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Method of producing ceramic printed board
JPS57106098A (en) * 1980-11-03 1982-07-01 Amp Inc Circuit board with casting circuit and method of producing same
JPS5868998A (en) * 1981-10-20 1983-04-25 後藤 啓 Method of forming printed wire
JPS60115290A (en) * 1983-11-28 1985-06-21 富士ゼロックス株式会社 Patterning method
JPS60128694A (en) * 1983-12-16 1985-07-09 株式会社日立製作所 Conductor powder melting circuit board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55127094A (en) * 1979-03-26 1980-10-01 Suwa Seikosha Kk Circuit board
JPS55141786A (en) * 1979-04-20 1980-11-05 Hitachi Ltd Method of forming infinitesimal pattern
JPS56120191A (en) * 1980-02-27 1981-09-21 Tamura Electric Works Ltd Pattern device structure and method of mounting same
JPS57106098A (en) * 1980-11-03 1982-07-01 Amp Inc Circuit board with casting circuit and method of producing same
JPS5785289A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Method of producing ceramic printed board
JPS5868998A (en) * 1981-10-20 1983-04-25 後藤 啓 Method of forming printed wire
JPS60115290A (en) * 1983-11-28 1985-06-21 富士ゼロックス株式会社 Patterning method
JPS60128694A (en) * 1983-12-16 1985-07-09 株式会社日立製作所 Conductor powder melting circuit board

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104187A (en) * 1989-08-28 1991-05-01 Internatl Business Mach Corp <Ibm> Pattern writing on substrate
JPH06140742A (en) * 1992-10-29 1994-05-20 Canon Inc Printed-circuit board and manufacture thereof
JPH1168288A (en) * 1997-08-21 1999-03-09 Matsushita Electric Ind Co Ltd Circuit board and production thereof
JP4605939B2 (en) * 2000-10-31 2011-01-05 京セラ株式会社 Wiring board manufacturing method
JP2002204043A (en) * 2000-10-31 2002-07-19 Kyocera Corp Circuit board and its manufacturing method
US8110918B2 (en) 2003-06-12 2012-02-07 Samsung Electronics Co., Ltd. Flexible substrate for a semiconductor package, method of manufacturing the same, and semiconductor package including flexible substrate
JP2005005721A (en) * 2003-06-12 2005-01-06 Samsung Electronics Co Ltd Wiring board for semiconductor package, its producing process and semiconductor package utilizing it
US8796158B2 (en) 2003-06-12 2014-08-05 Samsung Electronics Co., Ltd. Methods for forming circuit pattern forming region in an insulating substrate
JP2006066637A (en) * 2004-08-26 2006-03-09 Murata Mfg Co Ltd Manufacturing method of ceramic multilayer substrate and pressing die used therefor
JP2010052419A (en) * 2008-08-29 2010-03-11 Samsung Electro-Mechanics Co Ltd Methods for manufacturing ceramic green sheet and multilayer ceramic circuit board using the same
JP2012028735A (en) * 2010-06-24 2012-02-09 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2013038415A (en) * 2011-08-05 2013-02-21 Samsung Electro-Mechanics Co Ltd Thin film electrode ceramic substrate and method for producing the same
WO2014141492A1 (en) 2013-03-11 2014-09-18 日本碍子株式会社 Circuit substrate
JP2015050259A (en) * 2013-08-30 2015-03-16 京セラ株式会社 Semiconductor element mounting substrate and semiconductor device comprising the same
CN105916309A (en) * 2016-06-30 2016-08-31 广德宝达精密电路有限公司 Method for levelling conductive pattern and substrate in PCB
JP2020177950A (en) * 2019-04-15 2020-10-29 河村産業株式会社 Transparent conductive circuit board, manufacturing method thereof, usage method, and optical sensor

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