JPS6234828U - - Google Patents
Info
- Publication number
- JPS6234828U JPS6234828U JP12688685U JP12688685U JPS6234828U JP S6234828 U JPS6234828 U JP S6234828U JP 12688685 U JP12688685 U JP 12688685U JP 12688685 U JP12688685 U JP 12688685U JP S6234828 U JPS6234828 U JP S6234828U
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- collector
- transistor
- base
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案のスイツチ回路の第１実施例を
示す回路図、第２図は同第２実施例を示す回路図
、第３図は本考案の応用例を説明するためのテー
プレコーダのコントローラを示す回路図、第４図
はこの種従来のスイツチ回路を示す図である。
１……入力端子、２……電源端子、３……制御
端子、４……出力端子、５……テープレコーダの
コントローラ、６……端子、Ｌ……負荷、Ｑ１〜
Ｑ５……トランジスタ、Ｒ１〜Ｒ９……抵抗、Ｓ
１〜Ｓ５……スイツチ。
Fig. 1 is a circuit diagram showing a first embodiment of the switch circuit of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the same, and Fig. 3 is a circuit diagram of a tape recorder for explaining an application example of the present invention. FIG. 4 is a circuit diagram showing the controller, and is a diagram showing a conventional switch circuit of this type. 1...Input terminal, 2...Power terminal, 3...Control terminal, 4...Output terminal, 5...Tape recorder controller, 6...Terminal, L...Load, Q1~
Q5...Transistor, R1-R9...Resistor, S
1 to S5...Switch.
Claims (1)
に接続した１つのトランジスタ構成または極性の
異なるトランジスタのコレクタおよびエミツタ同
志が接続された構成の第１のスイツチング素子と
、コレクタとエミツタ間が第１のスイツチング素
子のベースあるいは、第１スイツチング素子の第
１のベースと電源端子間にエミツタ抵抗を介して
接続された第２のトランジスタと、コレクタとエ
ミツタ間が抵抗値がそれぞれ等しいコレクタ抵抗
およびエミツタ抵抗を介して電源端子と接地間に
、コレクタが第２のトランジスタのベースに接続
し、ベースがスイツチ回路の制御端子とする第３
のトランジスタと、ベースが第３のトランジスタ
のエミツタに、エミツタが第２のトランジスタの
エミツタ抵抗と抵抗値が等しい抵抗を介してアー
スに、コレクタが第１のスイツチング素子のエミ
ツタあるいは第１のスイツチング素子の第２のベ
ースに接続された第４のトランジスタとを備えた
ことを特徴とするスイツチ回路。 A first switching element has a configuration in which one transistor has its collector and emitter connected between input and output terminals, or a configuration in which the collectors and emitters of transistors with different polarities are connected together, and a first switching element has a configuration in which the collector and emitter are connected between the collector and emitter. or a second transistor connected via an emitter resistor between the base of the first switching element or the first base of the first switching element and the power supply terminal, and a collector resistor and an emitter resistor having equal resistance values between the collector and emitter, respectively. A third transistor is connected between the power supply terminal and ground, the collector of which is connected to the base of the second transistor, and the base of which is the control terminal of the switch circuit.
, the base is connected to the emitter of the third transistor, the emitter is connected to ground via a resistor whose resistance value is equal to the emitter resistance of the second transistor, and the collector is connected to the emitter of the first switching element or the first switching element. a fourth transistor connected to a second base of the switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12688685U JPS6234828U (en) | 1985-08-20 | 1985-08-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12688685U JPS6234828U (en) | 1985-08-20 | 1985-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6234828U true JPS6234828U (en) | 1987-02-28 |
Family
ID=31021114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12688685U Pending JPS6234828U (en) | 1985-08-20 | 1985-08-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6234828U (en) |
-
1985
- 1985-08-20 JP JP12688685U patent/JPS6234828U/ja active Pending
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