JPS6233442A - Formation of wiring - Google Patents

Abstract

PURPOSE:To simplify the process for providing wiring and to improve the yield of products, by performing a process of depositing a metal film for the first wiring, a process of forming a part of the first wiring, a process of forming the second wiring and a process of etching the metal film for the first wiring. CONSTITUTION:An SiO2 film 21 as an insulation film is adhered on a semiconductor substrate 11. A wiring metal 31 composed of Ti, Pt and Au layers superposed one after another is deposited on the film 21. Then, a mask is formed with a photoresist film 41. After the wiring metal 31 is worked by means of the ion milling process, the photoresist film 41 is removed, and a part of the wiring layer having a smaller thickness is formed. Some part (311-313) of the wiring metal 31 are allowed to remain for providing a power supply path for the plating operation. A plating mask 71 is formed with a photoresist film and Au is adhered with the wiring metal used as a power supply path. The plating mask 71 is removed and an Au plated film 81 is formed as a wiring having a larger thickness. Subsequently, the plating power supply path formed of the wiring metal 31 is removed by the ion milling process with photoresist film used as a mask. Thus, the wiring is completed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線の形成方法に関し、特に電解めっき法を用
いた半導体装置の配線の形成方法に関する・ 〔従来の技術〕 半導体装置の配線の形成方法の中で、電解めっき法を用
いた形成方法は配線厚さを容易に厚くできるため、低抵
抗配線、大電流用配線等の形成に広く用いられている。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for forming wiring, and in particular to a method for forming wiring in a semiconductor device using an electrolytic plating method. [Prior Art] Forming wiring in a semiconductor device Among these methods, a method using electrolytic plating can easily increase the thickness of the wiring, and is therefore widely used for forming low-resistance wiring, high-current wiring, and the like.

ただ電解めっき法では微細配線の形成は容易ではないの
で、微細配線を含む半導体装置では特に電流容量が大き
い箇所にのみ比較的粗なパターンの選択電解めっきによ
り形成された配線を設置し、微細なパターンの配線は別
途形成する方法が用いられている。このような配線の形
成方法としては従来より第３図に示される方法が多く用
いられている。この方法によれば、まず、第３図（、ｚ
）において゛、半導体基板１２上に絶縁膜２２を被着し
、更にその上に配線用金属膜として例えばＴｉ、　Ｐｔ
、　Ａｕ　ｔ−順次積層した金属膜３２ｔ−被着し、配
線加工用マスク４２を形成する。次にイオンミリング法
によりエツチングを行い、配線加工用マスク４２を除去
して電極形成部の金属膜３２のパターンを形成する（第
３図（ｂ））。この表面に対しめつき用給電金属膜除去
時の保護のための絶縁膜５２を形成しく第３図（Ｃ））
、Ｔ　ｉ　ｒ　Ａｕよりなる積層金属膜をめっき用給電
金属膜６２として全面に被着しく第３図（ｄ））、続い
てめっき用マスク７２を形成し、電解めっき法によりん
膜８２を選択的に形成する（第３図（ｅ）　）　、更に
めっき用マスク７２を除去しく第３図（ｆ）　）　、　
Ａｕ膜８２　、８３をマスクとしてめっき用給電金属膜
６２をイオンミリング法により除去して第３図（ｇ）に
示す配線を完成するものである。However, it is not easy to form fine wiring using electrolytic plating, so in semiconductor devices that include fine wiring, wiring formed by selective electrolytic plating with a relatively rough pattern is installed only in areas where the current capacity is particularly large. A method is used in which pattern wiring is formed separately. Conventionally, the method shown in FIG. 3 has been widely used as a method for forming such wiring. According to this method, first, Figure 3 (, z
), an insulating film 22 is deposited on the semiconductor substrate 12, and a wiring metal film such as Ti or Pt is further applied thereon.
, Au t - sequentially laminated metal films 32 t - are deposited to form a mask 42 for wiring processing. Next, etching is performed by ion milling, the wiring processing mask 42 is removed, and a pattern of the metal film 32 of the electrode forming portion is formed (FIG. 3(b)). An insulating film 52 is formed on this surface for protection when removing the power supply metal film for plating (Fig. 3(C)).
, a laminated metal film made of Ti r Au is deposited on the entire surface as a power supply metal film 62 for plating (FIG. 3(d)), then a plating mask 72 is formed, and a metal film 82 is selected by electrolytic plating. (FIG. 3(e)), and further remove the plating mask 72 (FIG. 3(f)).
Using the Au films 82 and 83 as a mask, the power supply metal film 62 for plating is removed by ion milling to complete the wiring shown in FIG. 3(g).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながらこのような方法によるときには、めっき給
電用金属膜を被着する工程が必要となシ、配線の形成工
程が複雑化し、更にめっき給電用金属膜を被着するため
の被着装置が必要になるという重大な欠点がある。また
先に配線３２が下地に形成されているため、これらによ
って生じる段差によってめっき用給電金属膜が段切れを
起こすことがしばしばあり、しかも段切れを生じないよ
うにめっき用給電金属膜を例えばバイアススパッタ蒸着
法等により被着して段部の被着膜厚を充分に厚くすると
、後工程のめつき用給電膜の除去の際に段部に金属膜が
エツチングされずに残り、配線間短絡を起こすという問
題があった。However, when using such a method, a process of depositing a metal film for plating power supply is required, the wiring formation process becomes complicated, and a deposition device is required to deposit the metal film for plating power supply. It has a serious drawback. In addition, since the wiring 32 is first formed on the base, the power supply metal film for plating often causes step breakage due to the step difference caused by these.Moreover, in order to prevent step breaks, the power supply metal film for plating is biased, for example. If the thickness of the deposited film on the steps is made sufficiently thick by sputter deposition, etc., when the power supply film for plating is removed in the subsequent process, the metal film will remain on the steps without being etched, resulting in short circuits between wiring. There was a problem of causing

本発明の目的は、上記従来の欠点を除去した配線の形成
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming wiring that eliminates the above-mentioned conventional drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は同一層上の配線として厚さが薄い第１の配線と
厚さが厚い第２の配線とを混載する半導体装置の配線の
形成方法において、第１の配線用の金ｔ４膜を被着する
工程と、少なくともめっき給電路を残して該配線用の金
属膜をエツチング加工して第１の配線の一部を形成する
工程と、該配線用の金属膜をめっき給電路に用いて第１
の配線用金属の一部に選択めっきを行い、第２の配線を
形成する工程と、第１の配線用の金属膜をエツチング加
工して第１および第２の配線を完成させる工程とを行う
ことを特徴とする配線の形成方法である。The present invention provides a method for forming wiring for a semiconductor device in which a first wiring with a thin thickness and a second wiring with a thick thickness are mixedly mounted on the same layer, in which a gold T4 film for the first wiring is coated. a step of etching the metal film for the wiring leaving at least the plating power supply path to form a part of the first wiring; and a step of etching the metal film for the wiring while leaving at least the plating power supply path; 1
A step of performing selective plating on a part of the wiring metal to form a second wiring, and a step of etching the metal film for the first wiring to complete the first and second wirings. This is a wiring forming method characterized by the following.

〔実施例〕〔Example〕

以下に本発明の実施例について図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図（α）〜（ｅ）は本発明の一実施例を説明するた
めに工程順に示した平面図、第２図（α）〜（ωは第１
図（α）〜（ｅ）の各工程に対する第１図（α）に示し
たＡ−Ａ部の断面図である。FIGS. 1(α) to (e) are plan views shown in the order of steps to explain one embodiment of the present invention, and FIGS. 2(α) to (ω are the first
It is a sectional view of the AA section shown in FIG. 1 (α) for each process of FIGS. (α) to (e).

まず、第２図（α）において、半導体基板１１上に絶縁
膜としてＳｌＯ□ｔ＆２１を被着し、その上に０．１１
ｓｎの厚さのＴ１．０．１μｍの厚さのＰζ０．４μｍ
厚さの麺を順次積層してなる厚さ０．６μ情の配線用金
属３１をスパッタ法により被着した後、第１図（α）の
ようにホトレジスト膜４１によりマスクを形成する。First, in FIG. 2 (α), SlO□t&21 is deposited as an insulating film on the semiconductor substrate 11, and 0.11
sn thickness T1.0.1μm thickness Pζ0.4μm
After a wiring metal 31 having a thickness of 0.6 μm, which is formed by sequentially laminating layers of different thicknesses, is deposited by sputtering, a mask is formed with a photoresist film 41 as shown in FIG. 1(α).

次に第２図（ｂ）に示すようにイオンミリング法により
配線金ｉ＠３１ヲ加工した後、ホトレジスト＠４１を除
去し、厚さが薄い方の配線の一部を形成する。Next, as shown in FIG. 2(b), after processing the wiring gold i@31 by ion milling, the photoresist @41 is removed to form a part of the thinner wiring.

このとき、めっき用給電路として配線用金属３１の一部
（３１１，３１２，３１３）を残置する（第１図（ｂ）
　）　。At this time, a part of the wiring metal 31 (311, 312, 313) is left as a power supply path for plating (Fig. 1(b)
).

第２図（Ｃ）において、厚さ３μｍのホトレジスト膜を
用いてめっき用マスク７１を形成する（第１図（ｃ））
。In FIG. 2(C), a plating mask 71 is formed using a photoresist film with a thickness of 3 μm (FIG. 1(c)).
.

第２図（ｄ）において、配線用金属を給電路として用い
て電解めっき法によ５ｉを２μｍの厚さ被着し、めっき
用マスク７１ヲ除去して厚さが厚い方の配線としてんめ
つき膜８１を形成する（第１図（ｄ）　）　、厚さが厚
い方の配線は配線用金属３１を下層に、めっき膜８１を
上層にして形成されており、厚さは２．６μｍとなる。In FIG. 2(d), 5i is deposited to a thickness of 2 μm by electrolytic plating using the wiring metal as a power supply path, and the plating mask 71 is removed to form the thicker wiring. The thicker wiring is formed with the wiring metal 31 as the lower layer and the plating film 81 as the upper layer, and has a thickness of 2.6 μm. Become.

続いて第１図（ｅ）に示すように配線用金属３１を用い
て形成されためつき用給電路を、ホトレジストａｔマス
クとしてイオンミリング法により除去し、配線を完成す
る。Subsequently, as shown in FIG. 1(e), the power supply path for tampering formed using the wiring metal 31 is removed by ion milling using a photoresist at mask to complete the wiring.

〔発明の効果〕 以上の説明より明らかなように本発明によれば配線用金
属膜をめっき給電路として利用するために、めっき給電
用金属膜を被着する工程は不要となるために配線の形成
工程が簡単となり、製品歩留りを著しく向上できる。ま
ためっき給電用金属膜を被着する装置も不要となる。し
かも配線用金属膜の下には構造物はないのでめっき給電
路の段切れの問題も皆無となり、めっき給電路の除去に
も何ら困難を伴わないので、その効果は大きい。[Effects of the Invention] As is clear from the above description, according to the present invention, since the metal film for wiring is used as a plating power supply path, the step of depositing the metal film for plating power supply is unnecessary, so that the wiring can be improved. The forming process is simplified and the product yield can be significantly improved. Further, a device for depositing a metal film for plating power supply is also unnecessary. Moreover, since there is no structure under the wiring metal film, there is no problem of breakage of the plating power supply path, and there is no difficulty in removing the plating power supply path, so the effect is great.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（α）〜（ｅ）は本発明の一実施例を工程順に示
した平面図、第２図（α）〜（Ｊｉ）は第１図のＡ−Ａ
断面図を工程順に示した断面図、第３図（α）〜（２）
は従来の配線の形成方法の一例を工程順に示した断面図
である。 １１．１２・・・半導体基板、２１　、２２・・・絶縁
膜、３１　、３２・・・配線用金に膜、４１．４２・・
・ホトレジスト膜、５２・・・絶縁膜、６２・・・めっ
き用給電金ＩＡ膜、７１．７２・・・めっき用マスク、
８１　、８２・・・蔀めつき膜特許出願人　　日本電気
株式会社 、−ｍ− 代理人　弁理士　　　内　　　原　　　　（′竺、′：
２＜ａ＞ （Ｃ） 第１図 （ｄ） （θ） 箒１図 第３図Figures 1 (α) to (e) are plan views showing an embodiment of the present invention in the order of steps, and Figures 2 (α) to (Ji) are A-A in Figure 1.
Cross-sectional views showing cross-sectional views in order of process, Figure 3 (α) to (2)
1A and 1B are cross-sectional views showing an example of a conventional wiring forming method in the order of steps. 11.12... Semiconductor substrate, 21, 22... Insulating film, 31, 32... Gold film for wiring, 41.42...
・Photoresist film, 52... Insulating film, 62... Power supply gold IA film for plating, 71.72... Mask for plating,
81, 82...Applicant for the patented film patent: NEC Corporation, -m- Agent: Patent attorney Uchihara ('竺、':
2<a> (C) Figure 1 (d) (θ) Broom 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] （１）同一層上の配線として厚さが薄い第１の配線と厚
さが厚い第２の配線とを混載する半導体装置の配線の形
成方法において、第１の配線用の金属膜を被着する工程
と、少なくともめつき給電路を残して該配線用の金属膜
をエッチング加工して第１の配線の一部を形成する工程
と、該配線用の金属膜をめつき給電路に用いて第１の配
線用金属の一部に選択めつきを行ない、第２の配線を形
成する工程と、第１の配線用の金属膜をエッチング加工
し、第１および第２の配線を完成させる工程とを行うこ
とを特徴とする配線の形成方法。(1) In a method for forming wiring for a semiconductor device in which a thin first wiring and a thick second wiring are mounted together on the same layer, a metal film for the first wiring is coated. a step of forming a part of the first wiring by etching the metal film for the wiring leaving at least the plated power supply path; and a step of using the metal film for the wiring as the plated power supply path. A step of selectively plating a part of the first wiring metal to form a second wiring; and a step of etching the first wiring metal film to complete the first and second wiring. A method for forming wiring, characterized by performing the following steps.