JPS6232653A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS6232653A JPS6232653A JP17216085A JP17216085A JPS6232653A JP S6232653 A JPS6232653 A JP S6232653A JP 17216085 A JP17216085 A JP 17216085A JP 17216085 A JP17216085 A JP 17216085A JP S6232653 A JPS6232653 A JP S6232653A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- gate electrode
- silicon film
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 239000002245 particle Substances 0.000 claims abstract description 5
- 150000003377 silicon compounds Chemical class 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 16
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 229910021332 silicide Inorganic materials 0.000 abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000002425 crystallisation Methods 0.000 abstract description 9
- 230000008025 crystallization Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010453 quartz Substances 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- -1 monobdenum Chemical compound 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は例えばアクティブマトリクス型平面ディスプ
レイパネルの各画素の切替えに用いられる薄膜トランジ
スタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a method of manufacturing a thin film transistor used for switching each pixel of an active matrix flat display panel, for example.
「従来の技術」
近年アクティブマトリクス型の平面ディスプレイパネル
の実現を目的として、半導体薄膜として多結晶シリコン
膜を用い、高速なスイッチング特性をもつ薄膜トランジ
スタの開発が進められている。第２図に多結晶シリコン
膜を用いた従来の薄膜トランジスタの断面構造を示す。"Prior Art" In recent years, with the aim of realizing active matrix type flat display panels, development of thin film transistors using polycrystalline silicon films as semiconductor thin films and having high-speed switching characteristics has been progressing. FIG. 2 shows a cross-sectional structure of a conventional thin film transistor using a polycrystalline silicon film.
（例えば。(for example.
Ｌａｋａｔｏｓ 、 ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ
ｔｈｅ ＳＩｐ 、 ＶＯＩ、 ２４（１９８３） １
８７．）この薄膜トランジスタの構造では、半導体薄膜
に多結晶シリコン膜を用いている。この多結晶シリコン
膜の移動度向上のためには、高温でシリコン膜を形成す
るか、あるいは高温でシリコン膜を加熱して結晶粒径を
増大する必要があった。Lakatos, proceedings of
the SIp, VOI, 24 (1983) 1
87. ) In this thin film transistor structure, a polycrystalline silicon film is used as the semiconductor thin film. In order to improve the mobility of this polycrystalline silicon film, it is necessary to form the silicon film at a high temperature or to increase the crystal grain size by heating the silicon film at a high temperature.
以下、この第２図に示す薄膜トランジスタの製遣方法を
説明する。まず絶縁基板１１上に多結晶シＩＪ−７ン膜
１２あるいはアモルファスシリコン膜１２を形成し、必
要に応じて電気炉加熱、レーザアニール等の方法により
シリコン膜１２の結晶化を行う。次に多結晶シリコン膜
１２上にゲート絶縁膜１３を形成した後、ゲート絶縁膜
１３上（ニゲート電極１４を形成する。その後、ゲート
電極１４をマスクとしてイオン注入法によりリン、ボロ
ン、ヒ素等の不純物を打ち込み、電気炉加熱、ランプ加
熱等の方法により不純物の活性化を行い、多結晶シリコ
ン膜１２にソース領域１５およびドレイン領域１６を形
成する。次に全体の上に層間絶縁膜１７を堆積した後、
ソース領域１５、ドレイン領域１６」二の層間絶縁膜１
７にそれぞれコンタノドホールを開口し、これら開口を
通じてソース領域１５、ドレイン領域１６とそれぞれ接
触したソース電極１８、ドレイン電極１９を形成して薄
膜トランジスタを完成する。Hereinafter, a method for manufacturing the thin film transistor shown in FIG. 2 will be explained. First, a polycrystalline IJ-7 film 12 or an amorphous silicon film 12 is formed on an insulating substrate 11, and if necessary, the silicon film 12 is crystallized by heating in an electric furnace, laser annealing, or the like. Next, after forming a gate insulating film 13 on the polycrystalline silicon film 12, a gate electrode 14 is formed on the gate insulating film 13. Then, using the gate electrode 14 as a mask, ion implantation is performed to inject phosphorus, boron, arsenic, etc. Impurities are implanted and activated by a method such as electric furnace heating or lamp heating to form a source region 15 and a drain region 16 in the polycrystalline silicon film 12. Next, an interlayer insulating film 17 is deposited on the entire surface. After that,
Source region 15, drain region 16'' second interlayer insulating film 1
A contact hole is opened in each of 7, and a source electrode 18 and a drain electrode 19 are formed in contact with the source region 15 and drain region 16, respectively, through these openings, thereby completing a thin film transistor.
「発明が解決しようとする問題点」
このような従来の薄膜トランジスタの製造方法では次の
ような欠点があった。"Problems to be Solved by the Invention" Such conventional methods for manufacturing thin film transistors have the following drawbacks.
（ａ） 絶縁基板１１として安価なガラスの使用が望
まれるが、そのガラス基板が耐えるように製造工程を低
温化せねばならず、次のような問題が生じる。まずイオ
ン注入法により導入した不純物の活性化が低温熱処理で
は不十分であるため、ソース領域１５、ドレイン領域１
６のシート抵抗が高くなる。例えば活性化の温度をガラ
スの変形温度以下である６００°Ｃにした場合、ソース
領域１５、ドレイン領域１６のシート抵抗は１０００
ＶＤにもなる。この結果、ソース電極１８、ドレイン電
極１９とソース領域１５゜１・上゛レイン領域１６との
各接触抵抗が高くなり、薄膜トランジスタの高駆動化が
図れない。また低温熱処理では多結晶シリコン膜１２の
結晶化が不十分であり、キャリアの移動度が小さくなる
ため、高駆動な薄膜トランジスタが形成できない。(a) Although it is desirable to use inexpensive glass as the insulating substrate 11, the manufacturing process must be carried out at a low temperature so that the glass substrate can withstand it, which causes the following problems. First, since low-temperature heat treatment is insufficient to activate impurities introduced by ion implantation, source region 15 and drain region 1
The sheet resistance of No. 6 becomes high. For example, when the activation temperature is set to 600°C, which is below the deformation temperature of glass, the sheet resistance of the source region 15 and drain region 16 is 1000°C.
Also available on VD. As a result, the contact resistance between the source electrode 18, the drain electrode 19, and the source region 15.1 and upper drain region 16 increases, making it impossible to achieve high drive of the thin film transistor. Further, in low-temperature heat treatment, crystallization of the polycrystalline silicon film 12 is insufficient and carrier mobility is reduced, making it impossible to form a highly driven thin film transistor.
（ｂ） 大面積基板の使用が望まれるが、イオン注入
法を用いる場合は、−基板当りの処理時間が長く生産性
が悪い。(b) Although it is desirable to use a large-area substrate, when using the ion implantation method, the processing time per substrate is long and productivity is poor.
この発明の目的は従来のイオン注入法によるソース領域
、ドレイン領域の形成工程と、シリコン膜の結晶化に必
要であった高温熱処理工程とを除去し、低温熱処理でも
ソース領域、ドレイン領域の低抵抗化とシリコン膜の結
晶粒径の増大とが図れ、かつ大面積基板上でも形成が可
能な薄膜トランジスタの製造方法を提供することにある
。The purpose of this invention is to eliminate the process of forming source and drain regions using the conventional ion implantation method and the high-temperature heat treatment process necessary for crystallizing silicon films, and to reduce the resistance of the source and drain regions even with low-temperature heat treatment. It is an object of the present invention to provide a method for manufacturing a thin film transistor, which is capable of increasing the crystal grain size of a silicon film and can be formed even on a large-area substrate.
「問題点を解決するための手段」
この発明によればゲート電極をマスクとしてゲート絶縁
膜を除去し、その除去により露出したシリコン膜表面上
に金属膜を堆積し、その金属膜および前記ゲート電極に
光、電磁波、荷電粒子の何れか一つを照射して加熱する
ことにより、前記露出したシリコン膜表面と前記金属膜
との界面にソース電極、ドレイン電極として使用する金
后・シリコン化合物（シリサイド）を形成し、かつ前記
ゲート電極直下のシリコン膜を熱処理し、結晶化する。"Means for Solving the Problem" According to the present invention, the gate insulating film is removed using the gate electrode as a mask, a metal film is deposited on the surface of the silicon film exposed by the removal, and the metal film and the gate electrode are removed. By irradiating the surface with light, electromagnetic waves, or charged particles and heating it, a gold-silicon compound (silicide) to be used as a source electrode and a drain electrode is formed at the interface between the exposed silicon film surface and the metal film. ) is formed, and the silicon film directly under the gate electrode is heat-treated and crystallized.
従来の技術とはソース・ドレインがシリサイドで形成さ
れること、およびシリコン膜の結晶化がゲート電極から
の伝導熱によって行われることが異なる。The difference from the conventional technology is that the source and drain are formed of silicide, and that the silicon film is crystallized by conductive heat from the gate electrode.
「実施例」
第１図にこの発明による薄膜トランジスタの製造方法の
一実施例を示す。まず第１図Ａに示すように、例えば石
英基板２１上に多結晶シリコン膜２２、あるいはアモル
ファスシリコン膜２２をＣＶＤ法、グロー放電分解法、
蒸着法等で形成した後、そのシリコン膜２２上にシリコ
ン酸化膜、シリコン窒化膜等のゲート絶縁膜３３を形成
する。"Embodiment" FIG. 1 shows an embodiment of the method for manufacturing a thin film transistor according to the present invention. First, as shown in FIG. 1A, for example, a polycrystalline silicon film 22 or an amorphous silicon film 22 is deposited on a quartz substrate 21 using a CVD method, a glow discharge decomposition method, or the like.
After forming by vapor deposition or the like, a gate insulating film 33 such as a silicon oxide film or a silicon nitride film is formed on the silicon film 22.
次に第１図Ｂに示すように光吸収係数が比較的大きいシ
リコン、モ１ノプデン、タングステン、あるいはチタン
等を例えば厚さ４ｏｏｏｉ程度に堆積してゲート電極２
４を例えば４ｏｏｏｉ程度の厚さで形成する。その後、
必要に応じてこのゲート電極２４とソース領域、ドレイ
ン領域との短絡を防止するために、° −酸化シリコ
ン、窒化シリコン恐どの絶縁膜２５をゲート電極２４の
側壁に、膜厚１００オグストロント程度に形成する。Next, as shown in FIG. 1B, silicon, monobdenum, tungsten, titanium, or the like having a relatively large light absorption coefficient is deposited to a thickness of, for example, about 4 oooi, and the gate electrode 2 is deposited.
4 is formed to have a thickness of about 4oooi, for example. after that,
If necessary, in order to prevent short circuits between the gate electrode 24 and the source and drain regions, an insulating film 25 such as silicon oxide or silicon nitride is formed on the side walls of the gate electrode 24 to a thickness of approximately 100 Å. Form.
次に第１図Ｃに示すように絶縁膜２５をゲート電極２４
の側壁部だけ残して反応性イオンエツチング等により除
去する。その後、金属膜２６としてシリコンと反応しシ
リサイド（化合物）の形成が可能で、かつシリコン膜よ
り光吸収係数の大きいチタン、モリブデン、あるいはタ
ングステン等を１０００人程度以上に堆積する。Next, as shown in FIG.
It is removed by reactive ion etching or the like, leaving only the side wall portion. Thereafter, titanium, molybdenum, tungsten, or the like, which can react with silicon to form a silicide (compound) and has a larger light absorption coefficient than the silicon film, is deposited as the metal film 26 in an amount of about 1000 or more.
このようにして形成した試料へ第１図りに示すよう（二
例えば１８ＫＷのハロゲンランプ光２７゜２８を数１０
秒程度照射する。試料の上方から入射した光２７はゲー
ト電極２４および金属膜２６にほとんど吸収される。一
方、試料の下方から入射した光２８は石英基板２１を透
過して一部シリコン膜２２に吸収され、残りは金属膜２
６およびゲート電極２４に吸収される。光の吸収量はゲ
ート電極２４および金属膜２６で最も多く、次にシリコ
ン膜２２であり、石英基板２１では無視できるほど少な
い。この結果、試料の温度はゲート電極２４および金属
膜２６で最も高く、次にシリコン膜２２が高くなる。こ
のためゲート電極２４および金属膜２６からシリコン膜
２２へ熱伝導が生じ、シリコン膜２２はシリコン膜２２
の光吸収による発熱に加え、侵導熱の寄与により、さら
に高温に加熱され、例えば１０００°ｃＢ上Ｃ二なる。As shown in the first diagram, the sample formed in this way is
Irradiate for about seconds. Most of the light 27 incident from above the sample is absorbed by the gate electrode 24 and the metal film 26. On the other hand, light 28 incident from below the sample passes through the quartz substrate 21 and is partially absorbed by the silicon film 22, and the rest is absorbed by the metal film 22.
6 and the gate electrode 24. The amount of light absorbed is greatest in the gate electrode 24 and the metal film 26, followed by the silicon film 22, and is negligibly small in the quartz substrate 21. As a result, the temperature of the sample is highest at the gate electrode 24 and the metal film 26, followed by the silicon film 22. Therefore, heat conduction occurs from the gate electrode 24 and the metal film 26 to the silicon film 22, and the silicon film 22
In addition to the heat generated by the absorption of light, the material is heated to an even higher temperature due to the contribution of invasive heat, for example, to 1000°C or higher.
この結果、例えば第３２回応用物理学関係連合講演会講
演予稿集の１２２−Ｃ−９に述べられているようにゲー
ト電極２４直下においてシリコン膜２′２：の結晶化が
生じ、結晶化シリコン膜２９となる。また同時に金属膜
２６とシリコン膜２２との反応によりシリコン化合物（
シリサイド）がゲート絶縁膜２３の両側に形成されてソ
ース領域３１、ドレイン領域３２が得られる。As a result, for example, as described in 122-C-9 of the 32nd Applied Physics Conference Proceedings, the silicon film 2'2: crystallizes directly under the gate electrode 24, and the crystallized silicon This becomes a film 29. At the same time, a silicon compound (
Silicide) is formed on both sides of the gate insulating film 23 to obtain a source region 31 and a drain region 32.
次に未反応金属膜２６を゛エツチングなどにより除去し
た後、第１図Ｅに示すように層間絶縁膜３３を堆積する
。最後に層間絶縁膜３３にコンタクトホールな開口しそ
れぞれその開口をｉｍじてソース領域３１およびドレイ
ン領域３２と接触したソース電極３４およびドレイン電
極３５を形成して薄膜トランジスタを完成する。Next, after removing the unreacted metal film 26 by etching or the like, an interlayer insulating film 33 is deposited as shown in FIG. 1E. Finally, a contact hole is opened in the interlayer insulating film 33, and a source electrode 34 and a drain electrode 35 are formed in contact with the source region 31 and drain region 32 through the opening, respectively, thereby completing a thin film transistor.
以上説明したこの発明の薄膜トランジスタの製造方法に
よれば、ソース領域３１、ドレイン領域３２がシリサイ
ドで形成され、従来のイオン注入法によるソース領域、
ドレイン領域と比較し電気抵抗が１／１００〜１／１０
００になる。また多結晶シリコン膜２９の結晶粒径はゲ
ート電極２４からの１云導熱の寄与により２〜３倍増大
する。According to the method for manufacturing a thin film transistor of the present invention described above, the source region 31 and the drain region 32 are formed of silicide, and the source region and the drain region 32 are formed of silicide using the conventional ion implantation method.
Electrical resistance is 1/100 to 1/10 compared to the drain region
It becomes 00. Further, the crystal grain size of the polycrystalline silicon film 29 increases by 2 to 3 times due to the contribution of 1 yen of heat conduction from the gate electrode 24.
以上説明した実施例ではシリサイド化とシリコン膜２２
の結晶化を・・ロゲンランプ光照射により行ったが、こ
れに限ることはなくレーザ光照射によってもまったく同
様に実施できる。また電磁波照射による高周波加熱法に
よっても同様に実施でき、この場合には金属膜２６およ
びゲート電極２４が電磁波を吸収し、渦電流の発生によ
り発熱する点が光照射による方法と異なる。例えば周波
数４００ ＫＨｚをもつ高周波加熱装置を用いると、金
属膜２６における電磁波の表皮深さが数靜にも及ぶため
、ゲート電極２４および金属膜２６は膜厚方向に一様に
加熱され、光照射の場合と同様にシリコン膜２２はゲー
ト電極２４、金属膜２６からの伝導熱によって加熱され
、結晶化が生じ、またシリサイド化も光照射の場合と同
様に行える。荷電粒子の照射によっても光照射、電磁波
照射の場合とまったく同様に実施できる。例えば荷電粒
子として電子ビームを用いて行うことができ、加速電圧
１０ＫＶ、ビーム電流数ｍＡの条件でシリコン膜２２の
結晶化およびシリサイド化を生じさせることができる。In the embodiment described above, silicidation and silicon film 22
Although the crystallization was carried out by irradiation with rogen lamp light, the crystallization is not limited to this and can be carried out in exactly the same manner by irradiation with laser light. A high-frequency heating method using electromagnetic wave irradiation can also be used. In this case, the metal film 26 and the gate electrode 24 absorb the electromagnetic waves and generate heat due to the generation of eddy current, which is different from the method using light irradiation. For example, when a high-frequency heating device with a frequency of 400 KHz is used, the skin depth of the electromagnetic waves in the metal film 26 reaches several degrees, so the gate electrode 24 and the metal film 26 are heated uniformly in the film thickness direction, and the light irradiation The silicon film 22 is heated by conductive heat from the gate electrode 24 and the metal film 26 to cause crystallization, and silicidation can also be performed in the same manner as in the case of light irradiation. Irradiation with charged particles can be carried out in exactly the same way as light irradiation and electromagnetic wave irradiation. For example, an electron beam can be used as the charged particle, and the silicon film 22 can be crystallized and silicided under the conditions of an acceleration voltage of 10 KV and a beam current of several mA.
以上説明した実施例では、石英基板を用いて説明したが
、ガラス基板を用いても同様に実施できる。この場合に
はガラス基板が石英基板に比べて低融点物質であるため
、シリコン膜２２の結晶化およびシリサイド化の際にガ
ラス基板を過度に加熱する前に、シリサイド化とシリコ
ン膜の結晶化を終了する必要があり、そのためには加熱
時間を短かくするためキャノンランプ光、レーザ光など
を用いることができる。Although the embodiments described above are explained using a quartz substrate, the same can be implemented using a glass substrate. In this case, since the glass substrate has a lower melting point than the quartz substrate, silicidation and crystallization of the silicon film should be performed before excessively heating the glass substrate during crystallization and silicidation of the silicon film 22. For this purpose, cannon lamp light, laser light, etc. can be used to shorten the heating time.
また上記実施例ではゲート電極とソース領域３１、ドレ
イン領域３２との短絡を防止するためにゲート電極に絶
縁物から成る側壁２５を形成したが、これに限ることは
なく、側壁２５を形成しなくてもゲート絶縁膜２３の存
在によりソース領域３１、ドレイン領域３２とゲート電
極２４とは互に分離される。Further, in the above embodiment, the sidewall 25 made of an insulator is formed on the gate electrode in order to prevent a short circuit between the gate electrode and the source region 31 and drain region 32. However, the present invention is not limited to this, and the sidewall 25 may not be formed. However, due to the presence of the gate insulating film 23, the source region 31, drain region 32, and gate electrode 24 are separated from each other.
「発明の効果」
以上説明したようにこの発明の方法によれば、ソース領
域、ドレイン領域がシリサイドで形成されるため電気抵
抗を低く抑えることができる。このためソース電極、ド
レイン電極とのコンタクト抵抗を小さくすることができ
、薄膜トランジスタの高駆動化が図れる。また大面漬基
板にも適用でき、イオン注入法に比ベスループット（生
産性）を上げることができる。さらにシリコン膜の結晶
化はゲート電極からの１云導熱により行われるため。"Effects of the Invention" As explained above, according to the method of the present invention, the source region and the drain region are formed of silicide, so that the electrical resistance can be kept low. Therefore, the contact resistance with the source electrode and the drain electrode can be reduced, and the thin film transistor can be highly driven. It can also be applied to large substrates, and can increase throughput (productivity) compared to ion implantation. Furthermore, crystallization of the silicon film is performed by heat conduction from the gate electrode.
透明基板の加熱を抑えて、ゲート電極直下のアクティブ
領域に結晶粒径の大きな結晶化したシリコン膜を形成で
きる。この結果、チャネル領域の移動度が向上し、薄膜
トランジスタの高駆動化が図れる利点がある。A crystallized silicon film with large grain size can be formed in the active region directly under the gate electrode while suppressing heating of the transparent substrate. As a result, there is an advantage that the mobility of the channel region is improved and the thin film transistor can be highly driven.
第１図はこの発明の薄膜トランジスタの製；貴注の一実
施例の各・工程を示す断面図、第２図は従来の薄膜トラ
ンジスタの製造方法により得られた薄膜トランジスタを
示す断面図である。
２１：絶縁基板、２２：多結晶シリコン４λ、２３：ゲ
ート絶縁膜、２４：ゲート電極、２５：絶縁膜、２６：
金属膜、２７：試料の上方から入射するハロゲンランプ
光、２８：試料の下方から入射するハロゲンランプ光、
２９：結晶化頭載、３１：シリサイドで形成したソース
領域、３２：シリサイドで形成したドレイン＠域、３３
：層間絶嶽膜、３４：ソース電極、３５ニドレイン電極
。
特許出願人 日本′宸信電話株式会社代 理 人
草 野 卓オ １ 図
士 １ 図
オ ２ 図FIG. 1 is a cross-sectional view showing each step of manufacturing a thin film transistor of the present invention; FIG. 2 is a cross-sectional view showing a thin film transistor obtained by a conventional thin film transistor manufacturing method. 21: Insulating substrate, 22: Polycrystalline silicon 4λ, 23: Gate insulating film, 24: Gate electrode, 25: Insulating film, 26:
metal film, 27: halogen lamp light incident from above the sample, 28: halogen lamp light incident from below the sample,
29: Crystallization head, 31: Source region formed of silicide, 32: Drain @ region formed of silicide, 33
: Interlayer film, 34: Source electrode, 35 Ni-drain electrode. Patent applicant: Nihon Shinshin Denwa Co., Ltd. Representative: Takuo Kusano 1 Illustration artist 1 Illustration 2 Illustration
Claims (1)
コン膜上面に順次形成されたゲート絶縁膜およびゲート
電極とを具備する薄膜トランジスタの製造方法において
、 前記ゲート電極をマスクとして前記ゲート絶縁膜を除去
する工程と、 その除去により露出した前記シリコン膜表面上に金属膜
を堆積する工程と、 その堆積された金属膜および前記ゲート電極に、光、電
磁波、荷電粒子のうちの何れか一つを照射して加熱する
ことにより、前記露出したシリコン膜表面と前記金属膜
との界面にソース電極、ドレイン電極として使用する金
属シリコン化合物を形成し、かつ前記ゲート電極直下の
シリコン膜を熱処理し結晶化する工程とを含むことを特
徴とする薄膜トランジスタの製造方法。(1) A method for manufacturing a thin film transistor comprising a silicon film deposited on an insulating substrate, and a gate insulating film and a gate electrode sequentially formed on the upper surface of the silicon film, wherein the gate insulating film is formed using the gate electrode as a mask. a step of depositing a metal film on the surface of the silicon film exposed by the removal; and a step of applying one of light, electromagnetic waves, and charged particles to the deposited metal film and the gate electrode. By irradiating and heating, a metal silicon compound to be used as a source electrode and a drain electrode is formed at the interface between the exposed silicon film surface and the metal film, and the silicon film directly under the gate electrode is heat-treated and crystallized. A method for manufacturing a thin film transistor, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17216085A JPS6232653A (en) | 1985-08-05 | 1985-08-05 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17216085A JPS6232653A (en) | 1985-08-05 | 1985-08-05 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232653A true JPS6232653A (en) | 1987-02-12 |
Family
ID=15936683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17216085A Pending JPS6232653A (en) | 1985-08-05 | 1985-08-05 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232653A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341028A (en) * | 1990-10-09 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of manufacturing thereof |
| EP0645802A2 (en) * | 1993-09-20 | 1995-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2009141144A (en) * | 2007-12-06 | 2009-06-25 | Sharp Corp | Semiconductor memory device, and methods of manufacturing and driving the same |
| CN104716193A (en) * | 2013-12-11 | 2015-06-17 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and preparation method and application thereof |
-
1985
- 1985-08-05 JP JP17216085A patent/JPS6232653A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444282A (en) * | 1990-10-09 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of manufacturing thereof |
| US5341028A (en) * | 1990-10-09 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of manufacturing thereof |
| US7109108B2 (en) | 1992-10-09 | 2006-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having metal silicide |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7602020B2 (en) | 1992-10-09 | 2009-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7723788B2 (en) | 1992-10-09 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US8017506B2 (en) | 1992-10-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| EP0645802A3 (en) * | 1993-09-20 | 1998-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6867431B2 (en) | 1993-09-20 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| EP0645802A2 (en) * | 1993-09-20 | 1995-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2009141144A (en) * | 2007-12-06 | 2009-06-25 | Sharp Corp | Semiconductor memory device, and methods of manufacturing and driving the same |
| CN104716193A (en) * | 2013-12-11 | 2015-06-17 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and preparation method and application thereof |
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