JPS6231190A - Electronic circuit board and manufacture thereof - Google Patents
Electronic circuit board and manufacture thereofInfo
- Publication number
- JPS6231190A JPS6231190A JP17045885A JP17045885A JPS6231190A JP S6231190 A JPS6231190 A JP S6231190A JP 17045885 A JP17045885 A JP 17045885A JP 17045885 A JP17045885 A JP 17045885A JP S6231190 A JPS6231190 A JP S6231190A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paint
- paint layer
- circuit board
- layer
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、絶縁基板の面上に抵抗体、コンデンサ、コイ
ル、直接半田付は不可能な配線等の電子素子と半田付は
可能な電極又は配線を印刷法により形成する電子回路基
板およびその製造方法に関するものＣある。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides electronic elements such as resistors, capacitors, coils, and wiring that cannot be directly soldered on the surface of an insulating substrate and electrodes that can be soldered. Alternatively, there is C related to an electronic circuit board in which wiring is formed by a printing method and a method for manufacturing the same.
［従来の技術］
従来、エツチング、めっき等の印刷法により配線パター
ンを形成し、スクリーン印刷法等により抵抗体、コンデ
ンサ等を形成して、絶縁基板上にハイブリッド回路や印
刷抵抗回路等を形成した電子回路基板が知られている。[Conventional technology] Conventionally, wiring patterns were formed by printing methods such as etching and plating, and resistors, capacitors, etc. were formed by screen printing methods, and hybrid circuits, printed resistance circuits, etc. were formed on insulating substrates. Electronic circuit boards are known.
例えば従来がら知られている、抵抗体を絶縁基板上に印
刷法によって形成Ｊる電子回路基板では、第４図に示す
ように、ＲｕＯ２等からなる抵抗塗料を用いてセラミッ
ク絶縁基板１０上に所定のパターンの抵抗塗料層を形成
した後に、絶縁基板１１とともに抵抗塗料層を約８５０
℃の調度で焼成して抵抗体１２を形成し、次いで酸化ル
テニウム、銀パラジウム等の貴金属を含有する導電塗料
を用いて電極のパターンを形成した侵約９００℃の温度
で焼成して半田（＝１け可能な電極部１３を形成してい
る。For example, in a conventionally known electronic circuit board in which a resistor is formed on an insulating substrate by a printing method, as shown in FIG. After forming a resistive paint layer with a pattern of
The resistor 12 is formed by firing at a temperature of 900°C, and then an electrode pattern is formed using a conductive paint containing noble metals such as ruthenium oxide and silver palladium. One electrode portion 13 is formed.
また第５図に示す電子回路基板のように、絶縁基板の一
方の面上に半田付は可能な銅箔１４からなる配線パター
ンをエツチングにより形成した後に、絶縁基板１０の他
方の面上に抵抗体１２を焼成し、絶縁基板を貫通して設
けたスルーホールの内壁に銀塗料等の導電塗料を塗布し
て抵抗体１２と配線パターンとを電気的に接続するもの
もある。Further, as in the electronic circuit board shown in FIG. 5, after a wiring pattern made of copper foil 14 that can be soldered is formed on one surface of the insulating substrate by etching, a resistor is formed on the other surface of the insulating substrate 10. In some cases, the resistor 12 and the wiring pattern are electrically connected by firing the resistor 12 and applying conductive paint such as silver paint to the inner wall of a through hole provided through the insulating substrate.
［発明が解決しようとする問題点］
しかしながら、例えば第４図に示す従来の電子回路基板
では、電子素子としての抵抗体１２の半田付は時の熱に
よる抵抗値の変化を少なくして安定した電気的特性を得
るために抵抗体１２を高い温度で焼成しており、また電
極部１３も半田量ゎれを防止するためにかなり高い温度
で焼成していた。したがって、この電子回路基板では、
高温で焼成するために高温炉の設備を必要とするばかり
か、加熱に要するエネルギが多くなるため、電子回路基
板の価格が高くなるのを避けられないという問題があっ
た。また電極部１３の焼成温度を高くしすぎると、電極
部の焼成時の熱で抵抗体１２の電気的特性が変化する虞
れがあった。[Problems to be Solved by the Invention] However, for example, in the conventional electronic circuit board shown in FIG. The resistor 12 was fired at a high temperature in order to obtain electrical characteristics, and the electrode portion 13 was also fired at a considerably high temperature to prevent the amount of solder from sagging. Therefore, in this electronic circuit board,
There is a problem in that not only is a high-temperature furnace equipment required for firing at a high temperature, but also a large amount of energy is required for heating, which inevitably increases the price of the electronic circuit board. Furthermore, if the firing temperature of the electrode portion 13 is set too high, there is a risk that the electrical characteristics of the resistor 12 may change due to the heat generated during firing of the electrode portion.
更に第５図に示す電子回路基板のように、絶縁基板１１
の一方の面に銅箔１４を形成する場合には、構造が複雑
になって回路の高密度化が図かれない欠点があった。ま
たこの回路基板では銅箔の酸化を防止する必要があるた
め、後に形成される抵抗体１２の焼成温度を半田付は温
度より低い温度にせざるを得ず、低い温度で焼成された
抵抗体１２の抵抗値が半田付は時の熱で変化し易くなり
、精密回路定数を要する用途には使えないという問題が
あった。Furthermore, like the electronic circuit board shown in FIG.
When the copper foil 14 is formed on one side of the circuit, the structure becomes complicated and there is a drawback that high circuit density cannot be achieved. In addition, in this circuit board, it is necessary to prevent oxidation of the copper foil, so the firing temperature of the resistor 12, which will be formed later, must be lower than the soldering temperature. When soldered, the resistance value tends to change due to heat during soldering, making it unsuitable for applications requiring precise circuit constants.
［問題点を解決するための手段］ 本発明をその実施例を示す第１図を参照して説明する。[Means for solving problems] The present invention will be explained with reference to FIG. 1 showing an embodiment thereof.
本出願の第１の発明は、絶縁基板１と、絶縁基板の上に
焼成により形成された半田付は不可能な電子素子（抵抗
体２）と、電子素子の少なくとも一部に接続されるよう
にして絶縁基板１の上に所定のパターンで形成され上面
に無電解めっきの核となるめっき核物質３ｂを備えた導
電塗料層３と、導電塗料層３の上に形成された無電解め
つき層３Ｃとから構成されることを特徴とする電子回路
基板である。The first invention of the present application includes an insulating substrate 1, an electronic element (resistor 2) which cannot be soldered and which is formed by firing on the insulating substrate, and a resistor 2 to be connected to at least a part of the electronic element. A conductive paint layer 3 is formed in a predetermined pattern on an insulating substrate 1 and has a plating core material 3b on its upper surface that serves as a nucleus for electroless plating, and an electroless plating layer 3 is formed on the conductive paint layer 3. This is an electronic circuit board characterized by comprising a layer 3C.
また本出願の第２の発明は、絶縁基板１の上に半田付は
不可能な電子素子（抵抗体２）を焼成により形成する工
程と、電子素子の少なくとも一部を被覆するようにして
絶縁基板１の上に熱硬化性の導電塗料を所定のパターン
で塗布して導電塗料層３ａを形成する工程と、導電塗料
ａ３ａの上に無電解めっきの核となるめっき核物質３ｂ
をふりまく工程と、導電塗料層３ａを焼成する工程と、
焼成した導電塗料層３ａの上に無電解めつきＭ３Ｃを形
成する工程とから成り、電子素子を焼成する温度を半田
付は温度より高い温度とし、導電塗料層３ａを焼成する
温度を半田付は温度より低い温度にしたことを特徴とす
る電子回路基板の製造方法である。Further, the second invention of the present application includes a step of forming an electronic element (resistor 2) that cannot be soldered on the insulating substrate 1 by firing, and a step of forming the electronic element (resistor 2) on the insulating substrate 1 by baking, and insulating the electronic element by covering at least a part of the electronic element. A step of applying a thermosetting conductive paint in a predetermined pattern on the substrate 1 to form a conductive paint layer 3a, and a step of forming a plating core material 3b which becomes the core of electroless plating on the conductive paint a3a.
a step of sprinkling the conductive paint layer 3a, a step of baking the conductive paint layer 3a,
It consists of a process of forming electroless plating M3C on the fired conductive paint layer 3a, the temperature at which the electronic element is fired is set higher than the soldering temperature, and the temperature at which the conductive paint layer 3a is fired is set at a higher temperature than the soldering temperature. This is a method of manufacturing an electronic circuit board, characterized in that the temperature is lower than the above temperature.
［発明の作用］
第１の発明では、導電塗料層３ａを介して無電解めっき
層３Ｃを形成して半田付は可能な電極又は配線等を構成
できるので、回路の高密変化を図ることができる上、半
田付は時の熱伝達率を小さくして、半田の熱による電子
素子の電気的特性の変化を小さくすることができる。[Function of the invention] In the first invention, the electroless plating layer 3C can be formed through the conductive paint layer 3a to form solderable electrodes or wiring, so it is possible to increase the density of the circuit. Additionally, soldering can reduce the heat transfer coefficient and reduce changes in the electrical characteristics of electronic devices due to the heat of the solder.
第２の発明によれば、電子素子を焼成する温度を半田付
は温度より高い温度とし、導電塗料層３ａを焼成する温
度を半田付は温度より低い温度にしたので、導電塗料層
３ａの焼成時の熱により電子素子の電気的特性が変化す
ることを防止することができる。According to the second invention, the temperature at which the electronic element is fired is higher than the soldering temperature, and the temperature at which the conductive paint layer 3a is fired is lower than the soldering temperature. It is possible to prevent the electrical characteristics of the electronic device from changing due to the heat generated during heating.
［実施例］
第１図は、本発明により製造した電子回路基板の一実施
例を示しており、同図において符号１で示す部材はセラ
ミック１．エポキシ系、ビスマレイミド−トリアジン（
ＢＴレジン）系等の材料からなる絶縁基板であり、絶縁
基板１の一方の面（表面）上には、電子素子としての抵
抗体２が印刷法により所定のパターンで形成されており
、抵抗体２の両側には所定のパターンの電極部３．３が
形成されている。電極部３は、抵抗体２の端部と一部が
接続されるように絶縁基板１の上に形成された導電塗料
層３ａと該導電塗料層３ａの上面上に固着された無電解
めっきの核となる銅粉末等のめつき核物質３ｂと、一部
が抵抗体２の上に結合するようにして無電解めっきによ
り形成された無電解めっき層３Ｃとから構成されている
。[Example] FIG. 1 shows an example of an electronic circuit board manufactured according to the present invention, in which the member indicated by the reference numeral 1 is made of ceramic 1. Epoxy-based, bismaleimide-triazine (
This is an insulating substrate made of a material such as BT resin), and on one side (front surface) of the insulating substrate 1, a resistor 2 as an electronic element is formed in a predetermined pattern by a printing method. Electrode portions 3.3 of a predetermined pattern are formed on both sides of 2. The electrode part 3 includes a conductive paint layer 3a formed on the insulating substrate 1 so as to be partially connected to the end of the resistor 2, and an electroless plating film fixed on the upper surface of the conductive paint layer 3a. It is composed of a plating core material 3b such as copper powder serving as a core, and an electroless plating layer 3C formed by electroless plating so as to be partially bonded onto the resistor 2.
上記実施例において、絶縁基板１は抵抗体２の焼成温度
に耐え得る耐熱性を有していればよく、上記の材質に限
定されるものではない。In the above embodiments, the insulating substrate 1 only needs to have heat resistance that can withstand the firing temperature of the resistor 2, and is not limited to the above-mentioned materials.
抵抗体２は、ポリイミド、シリコン、ＢＴレジン等の熱
硬化性樹脂をバインダとしたカーボンを含有する抵抗塗
料を用いて絶縁基板１上に所定のパターンを印刷し、半
田付は温度（約２４０℃）より高い温度で該パターンを
絶縁基板１に焼付けて形成される。抵抗体２を半田付は
温度より高い温度で焼成するのは、半田付は時に電極部
３から伝わる半田の熱によって、抵抗体２の抵抗値が変
化するのを防止するためである。The resistor 2 is made by printing a predetermined pattern on the insulating substrate 1 using a carbon-containing resistance paint with a thermosetting resin such as polyimide, silicone, or BT resin as a binder, and soldering is carried out at a temperature of about 240°C. ) is formed by baking the pattern onto the insulating substrate 1 at a higher temperature. The reason why the resistor 2 is fired at a higher temperature than the soldering temperature is to prevent the resistance value of the resistor 2 from changing due to solder heat transmitted from the electrode portion 3 during soldering.
導電塗料層３ａは、半田付は時の熱に耐え得る有機系ま
たは無機系の熱硬化性導電塗料を用いて形成されており
、熱硬化性導電塗料としては、例えば、エポキシ、フェ
ノール、メラミン、アクリル、ガラスフリット（有機系
）等をバインダとして、銀、金、酸化ルテニウム、パラ
ジウム、銅。The conductive paint layer 3a is formed using an organic or inorganic thermosetting conductive paint that can withstand the heat of soldering. Examples of the thermosetting conductive paint include epoxy, phenol, melamine, Silver, gold, ruthenium oxide, palladium, copper using acrylic, glass frit (organic type), etc. as a binder.
カーボン等を導電体として含有するものがある。Some contain carbon or the like as a conductor.
特に、導電体としてカーボンを含有する導電塗料を用い
れば、電子回路基板の価格を大幅に下げることができる
。上記実施例では、バインダとしてエポキシを用い、導
電体としてカーボンを用いた熱硬化性導電塗料により、
導電塗料層３ａを形成している。In particular, if a conductive paint containing carbon as a conductor is used, the price of electronic circuit boards can be significantly reduced. In the above example, a thermosetting conductive paint using epoxy as a binder and carbon as a conductor was used to
A conductive paint layer 3a is formed.
上記本発明により製造した上記電子回路基板の製造工程
は次の通りである。まず、抵抗塗料を用いてスクリーン
印刷法等により基板１の表面上に所定のパターンの抵抗
塗料層を形成し、該抵抗塗料層を基板１とともに約２６
０℃の温度で焼成して抵抗体２を形成する。次に、絶縁
基板１の表面上に所定のパターンで導電塗料を塗布して
導電塗料層３ａを形成する。尚該実施例では、抵抗体２
と導電塗料層３ａとの接続境界部に隙間が形成されてめ
っき液がこの隙間から侵入するのを防止するため、境界
部を導電塗料層３ａの塗料と同じ塗料で被覆して境界被
覆部を形成している。境界被覆部の形成を導電塗料層の
被覆と同時に行ってもよいのは勿論である。上記実施例
では境界被覆部も導電塗料層３ａの一部を構成している
。The manufacturing process of the electronic circuit board manufactured according to the present invention is as follows. First, a resistive paint layer with a predetermined pattern is formed on the surface of the substrate 1 using a resistive paint by a screen printing method or the like, and the resistive paint layer is coated with the substrate 1 at a thickness of approximately 2.5 mm.
The resistor 2 is formed by firing at a temperature of 0°C. Next, a conductive paint layer 3a is formed by coating the surface of the insulating substrate 1 with a conductive paint in a predetermined pattern. In this embodiment, the resistor 2
In order to prevent a gap from forming at the connection boundary between the conductive paint layer 3a and the plating solution from entering through this gap, the boundary area is coated with the same paint as the conductive paint layer 3a to form a boundary coating. is forming. Of course, the formation of the boundary coating may be carried out simultaneously with the application of the conductive paint layer. In the above embodiment, the boundary coating also constitutes a part of the conductive paint layer 3a.
導電塗料層３ａを形成した後、３４電塗料が粘着性を有
している間に無電解めっきの核となる銅粉末、銀粉末、
ニッケル粉末等からなるめっき核物質３ｂを導電塗料層
３ａの上面上にふりまく。尚抵抗体２上に銅粉末等が付
着しないようにするためには、抵抗体２の露出している
部分の領域を、スクリーンインク、液状レジスト、ドラ
イフィル。After forming the conductive paint layer 3a, while the 34-electrode paint has adhesive properties, copper powder, silver powder, which becomes the core of electroless plating,
A plating core material 3b made of nickel powder or the like is sprinkled on the upper surface of the conductive paint layer 3a. In order to prevent copper powder etc. from adhering to the resistor 2, the exposed areas of the resistor 2 should be coated with screen ink, liquid resist, or dry fill.
フオトレジス等の適宜のレジストで被覆しておけばよい
。ただし銅粉末等を散布した後に、適宜の方法で該銅粉
末等を取除けば、このようなレジストは必ずしも必要な
い。めつぎ核物質３ｂを導電塗料層３ａに付着させた後
、導電塗料層３ａを抵抗体２の焼成温度（２６０℃）お
よび半田付は温度（２４０℃）よりも低く且つめっき核
物質３ｂとしての銅粉末等が酸化しない温度（１５０℃
）で焼成する。このようにして抵抗体２の焼成温度より
も低い温度で導電塗料層３ａを焼成すれば、抵抗体２の
抵抗値が導電塗料層３ａの焼成温度によって変化するの
を防止することができる。It may be coated with a suitable resist such as photoresist. However, if the copper powder, etc. is removed by an appropriate method after being spread, such a resist is not necessarily necessary. After adhering the mating core material 3b to the conductive paint layer 3a, the conductive paint layer 3a is heated at a temperature lower than that of the resistor 2 at a firing temperature (260°C) and a soldering temperature (240°C) and as a plating core material 3b. The temperature at which copper powder, etc. does not oxidize (150℃
). By firing the conductive paint layer 3a at a temperature lower than the firing temperature of the resistor 2 in this manner, it is possible to prevent the resistance value of the resistor 2 from changing depending on the firing temperature of the conductive paint layer 3a.
導電塗料層３Ｃを焼成した後、無電解めっき層３Ｃを、
公知のアディティブ法により形成する。After baking the conductive paint layer 3C, the electroless plating layer 3C is
It is formed by a known additive method.
めっきの析出金属としては、銅、ニッケル等の半田に強
い金属を用いれば、半田食われに強い無電解めっき層を
形成できる。尚抵抗体２の露出部を覆うレジストとして
めつきレジス１−を用いれば、抵抗体２の露出部がめつ
き液によって化学変化を受けるのを防止できる。尚めつ
き液の化学変化が抵抗値に与える影響は、熱による抵抗
値の変化と比べて小さいので、めっきレジストは必ずし
も必要ない。If a metal that is resistant to solder, such as copper or nickel, is used as the deposited metal for plating, an electroless plating layer that is resistant to solder corrosion can be formed. If the plating resist 1- is used as a resist to cover the exposed portion of the resistor 2, the exposed portion of the resistor 2 can be prevented from being chemically changed by the plating solution. It should be noted that a plating resist is not necessarily required since the chemical change in the plating solution has a smaller effect on the resistance value than the change in resistance value due to heat.
上記実施例によれば、半田が付けられる部分をめっき核
物質３ｂが固着された導電塗料層３Ｃを介して無電解め
っきで形成するので、導電塗料層３Ｃを低い温度で焼成
しても半田食われがない。According to the above embodiment, since the part to be soldered is formed by electroless plating through the conductive paint layer 3C to which the plating core material 3b is fixed, there is no solder corrosion even if the conductive paint layer 3C is baked at a low temperature. There is no me.
言いかえれば、半田が付けられる部分を無電解めっきで
形成するので、導電塗料層３ａの焼成温度を半田付は温
度よりも低くすることができ、また導電塗料層３ａの焼
成温度を低くできれば、抵抗体２の焼成温度も併せて低
くすることができる。In other words, since the part to be soldered is formed by electroless plating, the firing temperature of the conductive paint layer 3a can be lower than that for soldering, and if the firing temperature of the conductive paint layer 3a can be lowered, The firing temperature of the resistor 2 can also be lowered.
したがって、製造工程における加熱温度を全体的に低く
することができるので、加熱に必要なエネルギ聞を少な
くすることができ、製造価格を大幅に下げることができ
る。Therefore, since the heating temperature in the manufacturing process can be lowered overall, the energy required for heating can be reduced, and the manufacturing cost can be significantly lowered.
また、上記実施例によれば、導電塗料層３ａを介して無
電解めっき層３Ｇを形成するので、電子素子としての抵
抗体２と無電解めっき層３ｃとの間に導電路を形成でき
る上、半田付は時の熱伝達率を小さくして、半田の熱に
よる抵抗体２の抵抗値の変化を小さくすることができる
。Further, according to the above embodiment, since the electroless plating layer 3G is formed via the conductive paint layer 3a, a conductive path can be formed between the resistor 2 as an electronic element and the electroless plating layer 3c, and Soldering can reduce the heat transfer coefficient and reduce changes in the resistance value of the resistor 2 due to the heat of the solder.
尚上記実施例において、電極部３だけでなく配線パター
ンを、電極部３の構成と同様にＳ電塗料層と電解めっき
層とからなる構成で形成しても良いのは勿論である。こ
の様にすれば、電極部３と配線パターンの形成を同時に
行うことができる上、配線の高密度化を図れる利点があ
る。In the above embodiment, it is of course possible to form not only the electrode section 3 but also the wiring pattern with a structure consisting of an S electrolytic paint layer and an electrolytic plating layer, similar to the structure of the electrode section 3. In this way, the electrode portion 3 and the wiring pattern can be formed at the same time, and there is an advantage that the density of the wiring can be increased.
上記第１図の実施例では、特に抵抗体２に何の保護層も
設番プでいないが、第２図に示すように、抵抗体２の大
部分を絶縁性を有する絶縁保護Ｈ４によって被覆しても
よい。この保護層４は、公知のめつきレジストでよく、
抵抗体２の外周面のうち導Ｎ塗料層３ａと接続される部
分と絶縁基板１に接続される部分とを除いたすべての面
を覆うように、抵抗体２を形成した後に抵抗体２の上に
公知の方法で配置する。尚保護層４を設けた場合にも、
めっき液の侵入を防止するため、導電塗料を塗布する際
に導電塗料層３ａと保護層４の境界部を、上記第１図の
実施例と同様に、導電塗料層３ａを構成する導電塗料に
よって被覆する。保護層４の大きさは、抵抗体２と導電
塗料層３ａとの電気的接続を十分に行える大きさであれ
ばよく、保護層４の幅を抵抗体２の幅と一致させるよう
にして、導電塗料層３ａを抵抗体２の端面にのみ接続す
るようにしてもよい。 −
上記実施例では、抵抗体２を絶縁基板１上に直接形成し
ているが、第３図に示づ゛ように、アンダーコートを含
むベース層５を介して抵抗体２を絶縁基板１上に形成し
てもよいのは勿論である。このベース層５の形成は、絶
縁基板１上に抵抗塗料を塗布して、抵抗体２を形成する
前に行う。ベース層がアンダーコートである場合には、
基板１の全面にベース層５が施されることになる。この
ようなベース層５を設ければ、絶縁基板１が含有する湿
度の影響を防止できるほか、抵抗体２を形成する面をよ
り平坦にして抵抗値のバラツキを小さくすることができ
る。In the embodiment shown in FIG. 1, no protective layer is particularly provided on the resistor 2, but as shown in FIG. You may. This protective layer 4 may be a known plating resist,
After forming the resistor 2, the resistor 2 is coated so as to cover the entire outer peripheral surface of the resistor 2 except for the part connected to the N-conducting paint layer 3a and the part connected to the insulating substrate 1. placed on top in a known manner. Furthermore, even when the protective layer 4 is provided,
In order to prevent the plating solution from entering, when applying the conductive paint, the boundary between the conductive paint layer 3a and the protective layer 4 is covered with the conductive paint constituting the conductive paint layer 3a, similar to the embodiment shown in FIG. Cover. The size of the protective layer 4 may be a size sufficient to allow electrical connection between the resistor 2 and the conductive paint layer 3a, and the width of the protective layer 4 is made to match the width of the resistor 2. The conductive paint layer 3a may be connected only to the end face of the resistor 2. - In the above embodiment, the resistor 2 is formed directly on the insulating substrate 1, but as shown in FIG. Of course, it may be formed as follows. The base layer 5 is formed before the resistive paint is applied onto the insulating substrate 1 and the resistor 2 is formed. If the base layer is an undercoat,
A base layer 5 will be applied to the entire surface of the substrate 1. By providing such a base layer 5, not only can the influence of humidity contained in the insulating substrate 1 be prevented, but also the surface on which the resistor 2 is formed can be made flatter to reduce variations in resistance value.
上記実施例では、半田付は不可能な電子素子として抵抗
体を例にあげて説明したが、本発明は抵抗体を印刷法に
より形成する電子回路基板に限定されるものではなく、
印刷法により形成されるコンデサ、コイル等の電子素子
を含む電子回路基板にも適用できるのは勿論である。ま
た、電子素子の形状および電極部３の形状は任意である
。In the above embodiment, a resistor was used as an example of an electronic element that cannot be soldered, but the present invention is not limited to an electronic circuit board in which a resistor is formed by a printing method.
Of course, the present invention can also be applied to electronic circuit boards including electronic elements such as capacitors and coils formed by printing methods. Further, the shape of the electronic element and the shape of the electrode section 3 are arbitrary.
「発明の効果」
以上のように、本出願の第１の発明によれば、導電塗料
層を介して無電解めっき層を形成して半田付は可能な電
極又は配線等を構成するので、回路の高密度化を図るこ
とができる上、半田付は時の熱伝達率を小さくして、半
田の熱による電子素子の電気的特性の変化を小さくする
ことができる利点がある。"Effects of the Invention" As described above, according to the first invention of the present application, an electroless plating layer is formed through a conductive paint layer to form electrodes or wiring that can be soldered. In addition to being able to achieve higher density, soldering has the advantage of lowering the heat transfer coefficient and reducing changes in the electrical characteristics of electronic elements due to the heat of the solder.
また第２の発明によれば、電子素子を焼成する温度を半
田付は温度より高１／〜温度とし、導電塗料層を焼成す
る温度を半田付は温度より低い温度にしたので、導電塗
料層の焼成時の熱により電子素子の電気的特性が変化す
ることを防止することができる利点がある。According to the second invention, the temperature at which the electronic element is fired is 1/~ higher than the temperature for soldering, and the temperature at which the conductive paint layer is fired is lower than the temperature for soldering. This has the advantage that the electrical characteristics of the electronic device can be prevented from changing due to heat during firing.
第１図は本発明の電子回路基板の一実施例の構成を示す
断面図、第２図は保護層を有する本発明に係る電子回路
基板の構成を示す断面図、第３図はベース層を介して抵
抗体を絶縁基板上に形成した状態を示す断面図、第４図
および第５図は、それぞれ従来の電子回路基板の構成を
示す断面図である。
１・・・絶縁基板、２・・・抵抗体、３・・・電極部、
３ａ・・・導電塗料層、３ｂ・・・めっき核物質、３Ｃ
・・・無電解めっき層、４・・・保護層、５・・・ベー
ス層。FIG. 1 is a cross-sectional view showing the structure of an electronic circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of an electronic circuit board according to the present invention having a protective layer, and FIG. 4 and 5 are cross-sectional views showing the structure of a conventional electronic circuit board, respectively. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Resistor, 3... Electrode part,
3a... Conductive paint layer, 3b... Plating core material, 3C
... Electroless plating layer, 4... Protective layer, 5... Base layer.
Claims (9)
にされた半田付け不可能な電子素子と、前記電子素子の
少なくとも一部に接続されるようにして前記絶縁基板の
上に所定のパターンで形成され上面に無電解めっきの核
となるめつき核物質を備えた導電塗料層と、前記導電塗
料層の上に形成された無電解めつき層とからなる電子回
路基板。(1) An insulating substrate, a non-solderable electronic element formed on the insulating substrate by firing, and a predetermined electronic element on the insulating substrate so as to be connected to at least a part of the electronic element. An electronic circuit board comprising a conductive paint layer formed in a pattern and having a plating core substance on the upper surface that serves as a nucleus for electroless plating, and an electroless plating layer formed on the conductive paint layer.
たは直接半田付けすることができない材料から形成され
た配線またはこれらの組合せであることを特徴とする特
許請求の範囲第１項に記載の電子回路基板。(2) The electronic element according to claim 1, wherein the electronic element is a resistor, a capacitor, a coil, a wiring formed from a material that cannot be directly soldered, or a combination thereof. circuit board.
されている部分および前記導電塗料層に接続されている
部分を除くすべての面は無電解めっき液によつて侵され
ることのない絶縁性保護層により被覆されていることを
特徴とする特許請求の範囲第１項に記載の電子回路基板
。(3) All surfaces of the outer circumferential surface of the electronic element, excluding the portion connected to the insulating substrate and the portion connected to the conductive paint layer, are insulated so that they will not be corroded by electroless plating solution. 2. The electronic circuit board according to claim 1, wherein the electronic circuit board is coated with a protective layer.
部は前記導電塗料と同じ塗料によって被覆されているこ
とを特徴とする特許請求の範囲第３項に記載の電子回路
基板。(4) The electronic circuit board according to claim 3, wherein a connection boundary between the conductive paint layer and the insulating protective layer is coated with the same paint as the conductive paint.
設けられていることを特徴とする特許請求の範囲第４項
に記載の電子回路基板。(5) The electronic circuit board according to claim 4, wherein the electronic element is provided on the insulating substrate via a base layer.
により形成する工程と、前記電子素子の少なくとも一部
を被覆するようにして前記絶縁基板の上に熱硬化性の導
電塗料を所定のパターンで塗布して導電塗料層を形成す
る工程と、前記導電塗料層の上に無電解めっきの核とな
るめつき核物質をふりまく工程と、前記導電塗料層を焼
成する工程と、焼成した前記導電塗料層の上に無電解め
つき層を形成する工程とから成り、 前記電子素子を焼成する温度は半田付け温度より高く、
前記導電塗料層を焼成する温度は半田付け温度より低い
温度であることを特徴とする電子回路基板の製造方法。(6) forming a non-solderable electronic element on an insulating substrate by firing; and applying a thermosetting conductive paint on the insulating substrate so as to cover at least a portion of the electronic element; a step of coating the conductive paint layer in a pattern to form a conductive paint layer, a step of sprinkling a plating core material that will become the nucleus of electroless plating on the conductive paint layer, a step of firing the conductive paint layer, and a step of baking the conductive paint layer. forming an electroless plating layer on the conductive paint layer, the temperature at which the electronic element is fired is higher than the soldering temperature;
A method for manufacturing an electronic circuit board, characterized in that the temperature at which the conductive paint layer is fired is lower than the soldering temperature.
系または無機系の熱硬化性樹脂に導電体を分散した導電
塗料であることを特徴とする特許請求の範囲第６項に記
載の電子回路基板の製造方法。(7) The conductive paint layer is a conductive paint in which a conductor is dispersed in an organic or inorganic thermosetting resin that can withstand heat during soldering. A method for manufacturing an electronic circuit board.
特許請求の範囲第７項に記載の電子回路基板の製造方法
。(8) The method for manufacturing an electronic circuit board according to claim 7, wherein the conductor is carbon.
質を酸化させない温度であることを特徴とする特許請求
の範囲第６項に記載の電子回路基板の製造方法。(9) The method for manufacturing an electronic circuit board according to claim 6, wherein the temperature at which the conductive paint layer is fired is a temperature that does not oxidize the plating core material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17045885A JPS6231190A (en) | 1985-08-01 | 1985-08-01 | Electronic circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17045885A JPS6231190A (en) | 1985-08-01 | 1985-08-01 | Electronic circuit board and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6231190A true JPS6231190A (en) | 1987-02-10 |
| JPH0584679B2 JPH0584679B2 (en) | 1993-12-02 |
Family
ID=15905310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17045885A Granted JPS6231190A (en) | 1985-08-01 | 1985-08-01 | Electronic circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6231190A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253710A (en) * | 2006-05-08 | 2006-09-21 | Matsushita Electric Works Ltd | Printed wiring board and method for manufacturing the same |
| WO2017141984A1 (en) * | 2016-02-17 | 2017-08-24 | ナミックス株式会社 | Conductive paste |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0977173A (en) * | 1995-09-13 | 1997-03-25 | Mitsumoto:Kk | Magnetic tape cassette storage case |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059764A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
| JPS6059765A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
-
1985
- 1985-08-01 JP JP17045885A patent/JPS6231190A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059764A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
| JPS6059765A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253710A (en) * | 2006-05-08 | 2006-09-21 | Matsushita Electric Works Ltd | Printed wiring board and method for manufacturing the same |
| WO2017141984A1 (en) * | 2016-02-17 | 2017-08-24 | ナミックス株式会社 | Conductive paste |
| JPWO2017141984A1 (en) * | 2016-02-17 | 2018-12-13 | ナミックス株式会社 | Conductive paste |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0584679B2 (en) | 1993-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4556422B2 (en) | Electronic component and manufacturing method thereof | |
| JPS61194794A (en) | Manufacture of hybrid integrated circuit board | |
| JPS6231190A (en) | Electronic circuit board and manufacture thereof | |
| WO1997030461A1 (en) | Resistor network in ball grid array package | |
| JPH0595071U (en) | Thick film circuit board | |
| JP2839262B2 (en) | Chip resistor and manufacturing method thereof | |
| JP2699980B2 (en) | Wiring board with a film element inside | |
| JPH10233485A (en) | Composite chip component | |
| JPH11345734A (en) | Laminated ceramic capacitor | |
| JPH1098244A (en) | Thick-film circuit board and its manufacture | |
| JP2537893B2 (en) | Electronic circuit board manufacturing method | |
| JPH02260592A (en) | Circuit board | |
| JP2562797Y2 (en) | Wiring board | |
| JPH0210548B2 (en) | ||
| JP2975491B2 (en) | Chip resistor | |
| JPH0410754B2 (en) | ||
| JP2000068105A (en) | Resistor and method of producing the same | |
| JPH0380358B2 (en) | ||
| JP2000156304A (en) | Jumper resistor | |
| JPS60175495A (en) | Multilayer board | |
| JPS63186492A (en) | Manufacture of circuit board | |
| JPS63244801A (en) | Printed wiring board | |
| JPS62287695A (en) | Manufacture of metal core copper-cladded enamelled board | |
| JPH11330693A (en) | Thick film multilayer ceramic board, its manufacture, and mounting structure of electronic component thereon | |
| JPH02260593A (en) | Manufacture of circuit board |