JPS62297889A - Active matrix substrate - Google Patents
Active matrix substrateInfo
- Publication number
- JPS62297889A JPS62297889A JP61142210A JP14221086A JPS62297889A JP S62297889 A JPS62297889 A JP S62297889A JP 61142210 A JP61142210 A JP 61142210A JP 14221086 A JP14221086 A JP 14221086A JP S62297889 A JPS62297889 A JP S62297889A
- Authority
- JP
- Japan
- Prior art keywords
- write
- write element
- source
- region
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 24
- 239000011159 matrix material Substances 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims description 38
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 230000007704 transition Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体基板上に多数の駆動電極と各駆動電極に
信号を書き込み、または消去する為の走査回路及び制御
回路を集積化したアクティブマトリクス基板に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a large number of drive electrodes on a semiconductor substrate, and a scanning circuit and control for writing or erasing signals to each drive electrode. The present invention relates to an active matrix substrate with integrated circuits.
本発明はアクティブマトリクス基板において、書込み素
子の集積化される領域と他の素子群の集積化される領域
を少なくとも２つ以上の領域に分離し、また書込み素子
は３または４素子からなり、第１書込み素子の接続され
る第１書込み接地線と第３書込み素子の接続される第２
書込み接地線を設けた事により、アクティブマトリクス
基板の書込み特性を改善し、表示品質低下の原因となる
信号電流のばらつきを低減するものである。In an active matrix substrate, the present invention separates a region where write elements are integrated and a region where other element groups are integrated into at least two regions, and furthermore, the write elements consist of three or four elements, and the write elements are composed of three or four elements. A first write ground line to which one write element is connected and a second write ground line to which a third write element is connected.
By providing the write ground line, the write characteristics of the active matrix substrate are improved and variations in signal current that cause deterioration in display quality are reduced.
従来例を第５図に示す。従来は同一基板上に、複数の垂
直スイッチ２、複数の駆動電極１、複数の水平スイッチ
５、水平走査回路２０、垂直走査回路２１、制御素子６
．７が集積化され、信号は制御回路（書込み素子、消去
素子）により制御され、水平スイッチ５、垂直スイッチ
２により選択され駆動電極１に伝達される。A conventional example is shown in FIG. Conventionally, a plurality of vertical switches 2, a plurality of drive electrodes 1, a plurality of horizontal switches 5, a horizontal scanning circuit 20, a vertical scanning circuit 21, and a control element 6 are arranged on the same substrate.
．． 7 are integrated, and signals are controlled by a control circuit (writing element, erasing element), selected by horizontal switch 5 and vertical switch 2, and transmitted to drive electrode 1.
第５図に従来例を示すが、書込み素子７をドレイン電流
の飽和領域で使用する場合、すなわち書込み素子７を定
電流源として動作さセる時理想的にはドレイン電流は書
込み素子７のドレイン電圧によらず一定でなければなら
ないが、実際にはチャンネル下の空乏層が拡がりドレイ
ン電流はドレイン電圧の増加にともない増加する。ドレ
イン電流の増加は信号電流のばらつきにつながり表示品
質低下の原因となる。書込み素子７のみに着目すれば、
チャネル下の基板の不純物濃度を高める事によりこの傾
向は低減される。しかし他の素子群たとえば水平走査回
路の能力は基板の不純物濃度を高める事により低下する
。また、書込み素子７をドレイン電流の定電流領域で動
作させる場合、すなわち定電流源として使用する時、基
板上の各書込み素子は全て同一電流値で書込み動作がな
されなければならない。A conventional example is shown in FIG. 5. When the write element 7 is used in the drain current saturation region, that is, when the write element 7 is operated as a constant current source, ideally the drain current is Although it must be constant regardless of the voltage, in reality the depletion layer under the channel expands and the drain current increases as the drain voltage increases. An increase in drain current leads to variations in signal current and causes deterioration in display quality. If we focus only on the write element 7,
This tendency is reduced by increasing the impurity concentration of the substrate under the channel. However, the performance of other elements such as horizontal scanning circuits is reduced by increasing the impurity concentration of the substrate. Further, when the write element 7 is operated in a constant current region of drain current, that is, when used as a constant current source, each write element on the substrate must perform a write operation with the same current value.
原理的には各素子のサイズを同一にする事により同一電
流値で書込みが出来るはずであるが、実際には各書込み
素子の接続される書込み接地線が共通で、ある有限な抵
抗値をもつ為、書込み電流値は電流の取り出し側から遠
くなるに従い小さい値となる。この現象は次の様に説明
される。In principle, it should be possible to write with the same current value by making each element the same size, but in reality, the write ground wire to which each write element is connected is common and has a certain finite resistance value. Therefore, the write current value becomes smaller as the distance from the current extraction side increases. This phenomenon is explained as follows.
ある書込み素子により書込み電流を取り出した時書込み
接地線の抵抗により書込み接地線に電圧降下を生じ、書
込み素子のソース電位が上昇し、書込み素子のゲートル
ソース間電圧が減少する。When a write current is taken out by a certain write element, a voltage drop occurs in the write ground line due to the resistance of the write ground line, the source potential of the write element increases, and the gate-to-source voltage of the write element decreases.
これにより書込み素子のドレイン電流が減少し、また、
書込み電流の取り出し側から遠ければ遠い程電圧降下が
増加し電流値は減少する０本発明の目的は上記信号電流
のばらつきを低減し、表示品質の向上を計り動作特性の
良好なアクティブマトリクス基板を提供することにある
。This reduces the drain current of the write element and also
The further away from the write current extraction side, the more the voltage drop increases and the current value decreases.The purpose of the present invention is to reduce the above-mentioned variation in signal current, improve display quality, and provide an active matrix substrate with good operating characteristics. It is about providing.
本発明のアクティブマトリクス基板は、ａ）書込み素子
の集積化される領域と上記各素子群を少なくとも２つ以
上の領域に集積化し、上記書込み素子と各素子群の素子
特性を変える手段として、基板と異なる不純物層を設け
、該不純物層領域の中に各素子群を集積化し各素子群の
素子特性をそれぞれに変えられるよう構成する、ｂ）異
なる不純物層領域に集積化される素子の特性を変える手
段として、基板主表面に設ける上記具なる不純物層領域
の不純物濃度を基板の不純物濃度より高め、かつそれぞ
れの領域ごとに不純物濃度を異ならしめ、必要な素子特
性に従い各素子群を異なる不純物濃度の領域に集積化す
る、Ｃ）上記書込み素子の集積化される不純物層領域の
不純物濃度を他の素子群の集積化される不純物層領域の
不純物濃度よりも高（ならしめた、ｄ）書込み素子は第
１、第２、第３、第４書込み素子の４素子から成り、第
１書込み素子のソースは第１書込み接地線に接続され、
第１書込み素子のドレインは第２書込み素子のソースに
接続され、第３書込み素子のソースは第２書込み接地線
に接続され、第３書込み素子のドレインは第４書込み素
子のソースに接続され、第２書込み素子と第４書込み素
子のドレインは水平スイッチのソースに接続され、第１
、第２、第３、第４書込み素子のゲートは書込みゲート
制御線に接続される、ｅ）第１書込み素子と第３書込み
素子はドレイン電流の飽和領域かまたは非飽和領域の飽
和領域との遷移領域近傍を動作点としてならしめ、ｆ）
第２書込み素子と第４書込み素子はドレイン電流の飽和
領域を動作点としてならしめる。The active matrix substrate of the present invention includes a) a substrate as a means for integrating a region in which a write element is integrated and each of the above-mentioned element groups into at least two or more regions, and changing the element characteristics of the above-mentioned write element and each of the above-mentioned element groups; (b) providing different impurity layers in the impurity layer region, integrating each element group in the impurity layer region and changing the element characteristics of each element group; b) controlling the characteristics of the elements integrated in the different impurity layer regions; As a means of changing the impurity concentration, the impurity concentration of the impurity layer region provided on the main surface of the substrate is made higher than the impurity concentration of the substrate, and the impurity concentration is made different for each region, so that each element group is given a different impurity concentration according to the required element characteristics. d) Writing, where the impurity concentration of the impurity layer region where the write element is integrated is made higher than the impurity concentration of the impurity layer region where the other element groups are integrated. The element consists of four elements, first, second, third, and fourth write elements, the source of the first write element is connected to the first write ground line,
The drain of the first write element is connected to the source of the second write element, the source of the third write element is connected to the second write ground line, the drain of the third write element is connected to the source of the fourth write element, The drains of the second write element and the fourth write element are connected to the source of the horizontal switch;
, the gates of the second, third, and fourth write elements are connected to a write gate control line; e) the first write element and the third write element are connected to the saturated region of the drain current or the saturated region of the non-saturated region; Normalize the vicinity of the transition region as the operating point, f)
The second write element and the fourth write element normalize the drain current saturation region as an operating point.
（２、特許請求の範囲第１項記載の第２書込み素子と第
４書込み素子は、１個の第５書込み素子がらなり、第５
書込み素子のソースは第１書込み素子と第３書込み素子
のドレインに接続され、第５書込み素子のドレインは水
平スイッチのソースに接続され、第５書込み素子はドレ
イン電流の飽和領域を動作点としてならしめるような構
成としたことを！！＊徴とする。(2. The second write element and the fourth write element recited in claim 1 consist of one fifth write element, and the fifth write element
The source of the write element is connected to the drains of the first write element and the third write element, the drain of the fifth write element is connected to the source of the horizontal switch, and the fifth write element has a drain current saturation region as an operating point. The structure was designed to make it more appealing! ! *As a sign.
本発明の作用を述べれば、第３図に示すように不純物濃
度Ａの不純物層上の素子のｖｏ １．特性と不純物濃
度Ｂの不純物層上の素子の■。−■Ｄ枠性を比較すれば
、ドレイン電流Ｉ１１のばらつきΔ■。は以下の様にな
り不純物濃度Ａの不純物層上の素子はドレイン電流りの
ドレイン電圧■。に対する依存性が少なくなり、信号電
流のばらつきの原因となる書込み素子のドレイン電流の
ばらつきが低減される。To describe the operation of the present invention, as shown in FIG. 3, the vo 1. ■Characteristics and device on impurity layer with impurity concentration B. -■ Comparing the D-frame properties, the variation in drain current I11 is Δ■. is as follows, and the element on the impurity layer with the impurity concentration A has a drain voltage (■) of the drain current. This reduces the dependence on the drain current of the write element, which causes variations in the signal current.
Ｉｓ＾重 ・
ＩＤＢＩ不純物濃度Ａ〉不純物Ｂのどき
Δ １０＾ く Δ ＩＤＩ
また、負荷の変動により第２と第４書込み素子のドレイ
ン電圧が上昇すると、第２、第４書込み素子は飽和領域
で動作するが、ドレイン電流、流はわずかに増加する。Is^heavy ・
IDBI impurity concentration A> impurity B Δ 10^ × Δ IDI Furthermore, when the drain voltages of the second and fourth write elements increase due to load fluctuations, the second and fourth write elements operate in the saturation region; Drain current, current increases slightly.
このとき第１と第３書込み素子のドレイン電圧も上昇す
るが、第１と第３岱込み素子のドレイン電圧の上昇は第
２、第４書込み素子のゲートとソース間の電圧を減少さ
せ、第２と第４書込み素子のドレイン電流を減少させる
働きをする。この作用を利用し第１、第３、第２、第４
書込み素子の動作点を適当に設定する事により非常に安
定したドレイン電流の飽和特性を得る事ができ、従来の
１０倍以上もレギュレーション特性の良い定電流源を得
ることができる。また、第１図に示す様に、垂直信号線
４が１本に対し書込み素子を７０〜７３の様に４素子を
１組として構成し、書込み素子７０と書込み素子７２の
ソースをそれぞれ異なる書込み接地線８．８１に接続し
、書込み動作を書込み素子７０と７２を通して行なう。At this time, the drain voltages of the first and third write elements also increase, but the increase in the drain voltages of the first and third write elements decreases the voltage between the gate and source of the second and fourth write elements, and It serves to reduce the drain currents of the second and fourth write elements. Using this effect, the first, third, second, and fourth
By appropriately setting the operating point of the write element, very stable saturation characteristics of the drain current can be obtained, and a constant current source with regulation characteristics more than 10 times better than conventional sources can be obtained. Further, as shown in FIG. 1, the write elements 70 to 73 are configured as a set of four elements for one vertical signal line 4, and the sources of the write element 70 and the write element 72 are set to different write elements. It is connected to ground line 8.81 and a write operation is performed through write elements 70 and 72.
このとき書込み素子７０に流れる書込み電流は書込み接
地′ａ８により取り出され、書込み素子７２に流れる電
流は書込み接地線８１により取り出され、書込み接地線
には書込み電流と書込み接地線の抵抗に比例した電圧降
下を生じる。この電圧降下は各書込み素子の基板上の位
置により異なるが、書込み接地線８と書込み接地線８１
に流れる書込み電流を互いに反対方向から取り出し合成
する事により、書込み接地線の位置による電圧降下値の
差は補償される事となる。すなわち各書込み素子の書込
み電流値の位置による依存性が補償され、信号電流のば
らつきが低減される。At this time, the write current flowing in the write element 70 is taken out by the write ground 'a8, the current flowing in the write element 72 is taken out by the write ground line 81, and the write current and the voltage proportional to the resistance of the write ground line are applied to the write ground line. cause a drop. Although this voltage drop differs depending on the position of each write element on the substrate, the write ground line 8 and the write ground line 81
By extracting and combining the write currents flowing from opposite directions, the difference in voltage drop value depending on the position of the write ground line can be compensated for. In other words, the positional dependence of the write current value of each write element is compensated for, and variations in signal current are reduced.
第１〜４図に本発明の一実施例を示す。 An embodiment of the present invention is shown in FIGS. 1-4.
駆動電極ｌ、垂直スイッチ２、水平スイッチ５、消去素
子６、書込み素子７０．７１、書込み素子７２．７３は
アレイ状に複数個配置され、書込み信号は駆動電極ｌか
ら、垂直走査回路２１により選択される垂直スイッチ２
を通り垂直信号線４に伝達される。さらに水平走査回路
２０により選択される水平スイッチ５を通った信号は、
書込み素子７０．７１と７２．７３を通り、それぞれ書
込み接地線８と８１に伝達される。書込み接地線８と８
１に伝達した書込み信号を互いに反対方向から取り出し
合成すれば、各書込み素子の位置によるｔ流値の依存性
が少ない一定の書込み信号が得られ、書込み素子の集積
化される領域７００の不純物濃度を他の素子群の集積化
される領域１００の不純物濃度より高めることにより、
書込み素子７１．７３のドレイン電圧の変動に対し安定
な書込み信号が得られる。A plurality of drive electrodes 1, vertical switches 2, horizontal switches 5, erase elements 6, write elements 70, 71, and 72, 73 are arranged in an array, and a write signal is selected from the drive electrodes 1 by the vertical scanning circuit 21. vertical switch 2
and is transmitted to the vertical signal line 4. Further, the signal passed through the horizontal switch 5 selected by the horizontal scanning circuit 20 is
It passes through write elements 70.71 and 72.73 and is transmitted to write ground lines 8 and 81, respectively. Write ground wire 8 and 8
If the write signals transmitted to 1 are extracted from opposite directions and combined, a constant write signal whose t current value is less dependent on the position of each write element can be obtained, and the impurity concentration of the region 700 where write elements are integrated can be obtained. By making the impurity concentration higher than that of the region 100 where other element groups are integrated,
A stable write signal can be obtained against fluctuations in the drain voltage of the write elements 71 and 73.
本発明によれば、書込み素子の集積化される不純物層領
域の不純物濃度を他の素子群の集積化される不純物層の
不純物濃度よりも高め、かつ書込み素子を従来よりも定
電流特性の良い方式で構成したことにより、従来よりも
信号電流のばらつきを大幅に低減でき、また他の素子群
の特性も向上し動作特性の優れたアクティブマトリクス
基板を容易に提供できる効果がある。また、本発明によ
れば、書込み素子を３または４素子で１組とし、それぞ
れの書込み素子のソースを互いに異なる書込み接地線に
接続する様な構成とし、書込み電流を互いに反対方向か
ら取り出し合成する事により、各書込み素子の基板上の
位置による書込み電流値の依存性を補償する事ができ、
従来よりも信号電流のばらつきが大幅に低減される。According to the present invention, the impurity concentration of the impurity layer region where the write element is integrated is made higher than the impurity concentration of the impurity layer region where the write element is integrated, and the write element has better constant current characteristics than before. By configuring this method, variations in signal current can be significantly reduced compared to the conventional method, and the characteristics of other element groups are also improved, making it possible to easily provide an active matrix substrate with excellent operating characteristics. Further, according to the present invention, three or four write elements are used as a set, and the sources of the respective write elements are connected to different write ground lines, so that write currents are taken out from opposite directions and combined. This makes it possible to compensate for the dependence of the write current value on the position of each write element on the substrate.
Variations in signal current are significantly reduced compared to conventional methods.
また本発明によれば、従来の様に書込み接地線の抵抗値
を減少させる為に書込み接地線の幅を大幅に拡げる必要
が少なくなり設計上の余裕度が太き（なりチップサイズ
の減少が計れ、コストダウンにも大きな効果がある。Furthermore, according to the present invention, there is no need to significantly increase the width of the write ground line in order to reduce the resistance value of the write ground line, which is the case with the conventional method. It also has a great effect on cost reduction.
第１〜４図は本発明の実施例を示す回路図。
第５図は従来例を示す回路図。
第６図はドレイン電圧−ドレインｘｉ特性図。
１・・・駆動電極、２・・・垂直スイッチ、３・・・垂
直スイッチ選択線、４・・・垂直信号線、５・・・水平
スイフチ、６・・・消去素子、７０・・・第１書込み素
子、７１・・・第２書込み素子、７２・・・第３書込み
素子、７３・・・第４書込み素子、８・・・第１書込み
接地線、８１・・・第２書込み接地線、９・・・書込み
ゲート制′４８線、１０・・・消去信号線、１１・・・
消去ゲート制御線、２０・・・水平走査回路、２１・・
・垂直走査回路、１００・７００・・・基板と異なる不
純物Ｎ領域、７５・・・第５書込み素子 ′
以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 最 上 務 他１名第３因
第５図1 to 4 are circuit diagrams showing embodiments of the present invention. FIG. 5 is a circuit diagram showing a conventional example. FIG. 6 is a drain voltage-drain xi characteristic diagram. DESCRIPTION OF SYMBOLS 1... Drive electrode, 2... Vertical switch, 3... Vertical switch selection line, 4... Vertical signal line, 5... Horizontal switch, 6... Erasing element, 70... No. 1 write element, 71... second write element, 72... third write element, 73... fourth write element, 8... first write ground line, 81... second write ground line , 9...Write gate system '48 line, 10...Erase signal line, 11...
Erase gate control line, 20...Horizontal scanning circuit, 21...
・Vertical scanning circuit, 100, 700... Impurity N region different from the substrate, 75... 5th write element ' Applicant: Seiko Epson Co., Ltd. Agent, Patent attorney Tsutomu Mogami and 1 other person Third cause No. 5 figure
Claims (2)
電極の選択を行なう複数個の垂直スイッチと上記垂直ス
イッチを接続する複数の垂直信号線と上記垂直信号線を
任意に選択するための水平スイッチと上記垂直信号線の
信号を制御するための複数の制御素子と上記垂直スイッ
チの開閉を行なう垂直走査回路及び上記水平スイッチの
開閉を行なう水平走査回路を備えたアクティブマトリク
ス基板において、 ａ）書込み素子の集積化される領域と上記各素子群を少
なくとも２つ以上の領域に集積化し、上記書込み素子と
各素子群の素子特性を変える手段として、基板と異なる
不純物層を設け、該不純物層領域の中に各素子群を集積
化し各素子群の素子特性をそれぞれに変えられるよう構
成されており、 ｂ）異なる不純物層領域に集積化される素子の特性を変
える手段として、基板主表面に設ける上記異なる不純物
層領域の不純物濃度を基板の不純物濃度より高め、かつ
それぞれの領域ごとに不純物濃度を異ならしめ、必要な
素子特性に従い各素子群を異なる不純物濃度の領域に集
積化しており、 ｃ）上記書込み素子の集積化される不純物層領域の不純
物濃度を他の素子群の集積化される不純物層領域の不純
物濃度よりも高くならしめており、 ｄ）書込み素子は第１、第２、第３、第４書込み素子か
ら成り、第１書込み素子のソースは第１書込み接地線に
接続されており、第１書込み素子のドレインは第２書込
み素子のソースに接続されており、第３書込み素子のソ
ースは第２書込み接地線に接続されており、第３書込み
素子のドレインは第４書込み素子のソースに接続されて
おり、第２書込み素子と第４書込み素子のドレインは水
平スイッチのソースに接続されており、第１、第２、第
３、第４書込み素子のゲートは書込みゲート制御線に接
続されており、 ｅ）第１書込み素子と第３書込み素子はドレイン電流の
飽和領域かまたは非飽和領域との遷移領域近傍を動作点
としてならしめ、 ｆ）第２書込み素子と第４書込み素子はドレイン電流の
飽和領域を動作点としてならしめることを特徴とするア
クティブマトリクス基板。(1) To arbitrarily select a plurality of drive electrodes arranged in a two-dimensional manner, a plurality of vertical switches for selecting the drive electrodes, a plurality of vertical signal lines connecting the vertical switches, and the vertical signal line. An active matrix substrate comprising a horizontal switch, a plurality of control elements for controlling signals of the vertical signal line, a vertical scanning circuit for opening and closing the vertical switch, and a horizontal scanning circuit for opening and closing the horizontal switch, comprising: a ) An impurity layer different from the substrate is provided as a means for integrating the region where the write element is integrated and each of the above-mentioned element groups into at least two or more regions and changing the element characteristics of the above-mentioned write element and each element group. It is configured such that each element group is integrated in a layer region and the element characteristics of each element group can be changed individually. The impurity concentration of the different impurity layer regions provided in the substrate is made higher than the impurity concentration of the substrate, and the impurity concentration is made different for each region, and each element group is integrated into regions with different impurity concentrations according to the required device characteristics, c) The impurity concentration of the impurity layer region where the write element is integrated is made higher than the impurity concentration of the impurity layer region where the other element groups are integrated, and d) The write element has a first, a second, The source of the first write element is connected to the first write ground line, the drain of the first write element is connected to the source of the second write element, and the source of the first write element is connected to the source of the second write element. The source of the element is connected to the second write ground line, the drain of the third write element is connected to the source of the fourth write element, and the drain of the second write element and the fourth write element are connected to the source of the horizontal switch. and the gates of the first, second, third, and fourth write elements are connected to the write gate control line, and e) the first write element and the third write element are in the saturation region of the drain current. or an active matrix substrate characterized in that an operating point is set near a transition region with a non-saturation region, and f) the second write element and the fourth write element have a saturated region of drain current set as an operating point.
第５書込み素子からなり、第５書込み素子のソースは第
１書込み素子と第３書込み素子のドレインに接続され、
第５書込み素子のドレインは水平スイッチのソースに接
続され、第５書込み素子はドレイン電流の飽和領域を動
作点としてならしめることを特徴とする特許請求の範囲
第１項に記載のアクティブマトリクス基板。(2) the second write element and the fourth write element are composed of one fifth write element, the source of the fifth write element is connected to the drains of the first write element and the third write element,
2. The active matrix substrate according to claim 1, wherein the drain of the fifth write element is connected to the source of the horizontal switch, and the fifth write element has a saturation region of drain current as an operating point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61142210A JPS62297889A (en) | 1986-06-18 | 1986-06-18 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61142210A JPS62297889A (en) | 1986-06-18 | 1986-06-18 | Active matrix substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62297889A true JPS62297889A (en) | 1987-12-25 |
Family
ID=15309958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61142210A Pending JPS62297889A (en) | 1986-06-18 | 1986-06-18 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62297889A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4940546A (en) * | 1987-09-03 | 1990-07-10 | Tecon Gmbh | Installation for aerobic biological purification of pollutant-containing water |
-
1986
- 1986-06-18 JP JP61142210A patent/JPS62297889A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4940546A (en) * | 1987-09-03 | 1990-07-10 | Tecon Gmbh | Installation for aerobic biological purification of pollutant-containing water |
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