JPS62291121A - Planar type semiconductor device - Google Patents
Planar type semiconductor deviceInfo
- Publication number
- JPS62291121A JPS62291121A JP13665286A JP13665286A JPS62291121A JP S62291121 A JPS62291121 A JP S62291121A JP 13665286 A JP13665286 A JP 13665286A JP 13665286 A JP13665286 A JP 13665286A JP S62291121 A JPS62291121 A JP S62291121A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- dielectric constant
- substrate
- type substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 abstract description 23
- 230000005684 electric field Effects 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 44
- 238000009792 diffusion process Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
１ 発明の詳細な説明
〔産業上の利用分野〕
本発明は、プレーナ型半導体装置に関し、特に接合を覆
う絶縁膜の構成に関する。DETAILED DESCRIPTION OF THE INVENTION 1. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a planar semiconductor device, and particularly to the structure of an insulating film covering a junction.
従来、プレーナ型半導体装置の耐圧向上技術の一つにフ
ィールドプレート構造がある。第３図にフィールドプレ
ート構造を持ったＰＮ接合型Ｓｉダイオードの一般例を
示し、以下にフィールドプレート構造の作用を説明する
。Conventionally, there is a field plate structure as one of the techniques for improving the withstand voltage of planar semiconductor devices. FIG. 3 shows a general example of a PN junction type Si diode having a field plate structure, and the action of the field plate structure will be explained below.
第３図のＳｔダイオードはＮ型基板２４にＰ型拡散層２
５が設けられ、ＰＮ接合端をおおって絶縁膜２１が設け
られ、この絶縁膜上にフィールドプレート２２が設けら
れている。まず仁のＰＮ接合に逆バイアスを印加すると
、第３図中破線に示す通ヤＮ型基板２４に空乏層が広が
る。この時、フィールドプレート２２の電位がＰ型拡散
層と同電位であることから、フィールドブレート直下の
絶縁［２１とＮ型基板２４との界面近傍の空乏層が伸び
、一般のフィールドプレート構造を持たないプレーナ型
半導体装置よシも、耐圧が同上する。The St diode in FIG. 3 has a P-type diffusion layer 2 on an N-type substrate 24.
5, an insulating film 21 is provided covering the PN junction end, and a field plate 22 is provided on this insulating film. First, when a reverse bias is applied to the normal PN junction, a depletion layer spreads in the N-type substrate 24 shown by the broken line in FIG. At this time, since the potential of the field plate 22 is the same as that of the P-type diffusion layer, the depletion layer near the interface between the insulation [21] directly under the field plate and the N-type substrate 24 is extended, resulting in a general field plate structure. Even planar type semiconductor devices that do not have the same breakdown voltage as above.
上述した従来のフィールドプレート構造では、フィール
ドプレートの材質が金属であるため、フィールドプレー
ト全域が等電位となシ、フィールドプレート端部の電界
が強く、外部イオンの吸着等が起シ易く、信頼性上の不
安定要因となる。また、フィールドプレート直下の電界
が強いと絶縁膜との界面近傍のＮ型基板表面がＰチャン
ネルに反転し、Ｐ散拡散層が伸びた状態になシ、最悪の
場合２段ブレークダウンを起すことがある。更に、上述
の現象は、絶縁膜中の電荷密度によって変化し、工程能
力上の問題も関係する
〔問題点を解決するための手段〕
本発明のプレーナ型半導体装置は、金属（Ａｎ等）のフ
ィールドプレート構造のかわシに、高誘電率の誘電体膜
を使用して、Ｎ型基板表面及び、フールドブレート端部
での電界集中を緩和するものである。In the conventional field plate structure described above, since the material of the field plate is metal, the entire field plate is not at an equal potential, and the electric field at the edge of the field plate is strong, which tends to cause adsorption of external ions, resulting in poor reliability. This causes the above instability. In addition, if the electric field directly under the field plate is strong, the surface of the N-type substrate near the interface with the insulating film will be inverted to a P-channel, leaving the P-diffusion layer stretched, resulting in a two-stage breakdown in the worst case. There is. Furthermore, the above-mentioned phenomenon changes depending on the charge density in the insulating film, and is also related to problems in process capability [Means for solving the problem] The planar semiconductor device of the present invention A dielectric film with a high dielectric constant is used in the field plate structure to alleviate electric field concentration on the surface of the N-type substrate and the edge of the field plate.
本発明のプレーナ型半導体装置は、ＰＮ接合を１つ以上
有するプレーナ型半導体装置において接合終端を保護し
ている第１の絶縁膜よに第１の絶縁膜の誘電率よシ高い
誘電率を有する第２の絶縁膜を形成されていることを特
徴とする。The planar semiconductor device of the present invention has a dielectric constant higher than that of the first insulating film that protects the junction termination in a planar semiconductor device having one or more PN junctions. A feature is that a second insulating film is formed.
好ましい実施態様では、第２の絶縁膜の形成されていな
い第１の絶縁膜上と第２の絶縁膜上とに第１の絶縁膜と
同じ、又はよシ低い誘電率を有し、且つ膜厚が第２の絶
縁膜と同じ又は、厚い第３の絶ｌｆ＆膜が形成されてい
る。In a preferred embodiment, on the first insulating film on which the second insulating film is not formed and on the second insulating film, a film having a dielectric constant equal to or lower than that of the first insulating film is formed. A third insulating film having the same or thicker thickness as the second insulating film is formed.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
Ｎ型基板４に形成されたＰ散拡散層５とのＰＮ接合端ｔ
−ａい、基板上に設けられた第１の絶縁膜ｌは、熱酸化
によって形成された比誘電率４．６〜４．８の５ｉＯｚ
膜である。第１の絶縁膜上に設けられ、ＰＮ接合端の上
部を覆う第２の絶縁膜２は、比誘電率８．６〜１０．５
のＡ７ｚＯｓＭＭである。第１および第２の絶縁膜上に
設けられた第３の絶縁膜３は、比誘電率４．０〜４．３
ｃＤＣＶＤＳｉＯｚＭｕＴ６る。PN junction end t with P diffusion layer 5 formed on N type substrate 4
-a, the first insulating film l provided on the substrate is a 5iOz film with a dielectric constant of 4.6 to 4.8 formed by thermal oxidation.
It is a membrane. The second insulating film 2 provided on the first insulating film and covering the upper part of the PN junction end has a dielectric constant of 8.6 to 10.5.
This is A7zOsMM. The third insulating film 3 provided on the first and second insulating films has a dielectric constant of 4.0 to 4.3.
cDCVDSiOzMuT6.
電極６は、Ｐ形波散層５にオーミック接触を持つＡｌ薄
膜であシ、電極７はＮ形基板ｌとオーミック接触を持つ
ＡＪ薄膜である。ここで電極６はｅｑｕｉｐｏｔｅｎｆ
ｉａｌ ｒｉｎｇ （ＥＱＰＲ）として働く。The electrode 6 is an Al thin film having ohmic contact with the P-type wave dispersion layer 5, and the electrode 7 is an AJ thin film having ohmic contact with the N-type substrate 1. Here, the electrode 6 is equipotenf
ial ring (EQPR).
まず、ＰＮ接合に逆バイアスを印加すると、Ｎ形基板４
中に空乏層が広がシ、第２の絶縁膜２の形成された部位
近傍を通る等電位線８は、第１図中に破線で示す通シと
なる。これは、第２の絶縁膜２の誘電率ε２が第１の絶
縁膜１の誘電率＃ｌよル高いため、第２の絶縁膜２中の
電界が弱くなシ、第２の絶縁膜２直下の第１の絶縁膜上
中の電界が強くなｈ、Ｎ形基板４表面付近の空乏層を伸
ばす方向に働く。更に、第２の絶縁膜２上には誘電率ｔ
３が第１の絶縁膜１と同程度の第３の絶縁膜が形成され
、第２の絶縁Ｍ２中も電気力線が通過するため、第３の
絶縁膜３上の電位分布は一様となシ、外部イオンの偏シ
による特性変動の少ないプレーナ型半導体装置となる。First, when a reverse bias is applied to the PN junction, the N type substrate 4
The depletion layer spreads therein, and the equipotential line 8 passing near the portion where the second insulating film 2 is formed becomes a line shown by a broken line in FIG. This is because the dielectric constant ε2 of the second insulating film 2 is higher than the dielectric constant #l of the first insulating film 1, so the electric field in the second insulating film 2 is weak. The electric field directly above the first insulating film is strong and acts in the direction of extending the depletion layer near the surface of the N-type substrate 4. Further, on the second insulating film 2 there is a dielectric constant t
Since the third insulating film 3 is the same as the first insulating film 1 and the electric lines of force pass through the second insulating film 1, the potential distribution on the third insulating film 3 is uniform. Moreover, a planar semiconductor device with less variation in characteristics due to unevenness of external ions can be obtained.
第２図は本発明の第２の実施例の縦断面図である。第２
の実施例は本発明をＭＯＳＦＥＴ 外周部に適用したも
のである。第１の絶縁膜４１は熱酸化によって形成され
た比誘電率４．６〜４．８のＳｉ０ｇ膜であシ、第２の
絶縁膜１２は、比誘電率３０〜１００のＴｉ０ｚ膜であ
る。第３の絶縁膜１３は、比［率４．０〜４．３０ＣＶ
ＤＳｉＯｚＭである。Ｎ型基板１４は、比抵抗２０〜６
０Ωαの基板であり、ＭＯＳＦＥＴのドレインとして働
く。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. Second
In this embodiment, the present invention is applied to the outer peripheral portion of a MOSFET. The first insulating film 41 is a Si0g film with a dielectric constant of 4.6 to 4.8 formed by thermal oxidation, and the second insulating film 12 is a Ti0z film with a dielectric constant of 30 to 100. The third insulating film 13 has a ratio of 4.0 to 4.30 CV.
It is DSiOzM. The N-type substrate 14 has a specific resistance of 20 to 6
It is a 0Ωα substrate and serves as the drain of the MOSFET.
Ｐ型拡散層１５は、Ｎ型基板１４内に形成され、ゲート
領域として働く拡散層である。高濃度Ｎ型拡散層１１ｊ
：Ｐ型拡散層１５内に形成され、ＭＯＳＦＥＴのソース
領域として働きＰ散拡散層よシ高濃度拡散層である。電
極１７はソース電極、電極１８はゲート電極（Ｐｏｌｙ
ｉ Ｓｉ ｅｔｃ）である。The P-type diffusion layer 15 is a diffusion layer formed within the N-type substrate 14 and serving as a gate region. High concentration N type diffusion layer 11j
: It is formed in the P-type diffusion layer 15, acts as a source region of the MOSFET, and is a highly doped diffusion layer compared to the P-type diffusion layer. The electrode 17 is a source electrode, and the electrode 18 is a gate electrode (Polymer
i Si etc).
まず、電極１７．１８間をショート状態で接地し、ドレ
イン領域に、正バイアスを印加すると、Ｎ型基板１４中
に空乏層が広がり、第２の絶縁膜１２の近傍の第１の絶
Ｒ膜とＮ型基板との界面の等電位線は第２図中に破線で
示す通シとなシ、空乏層が伸びゲート領域周辺部の電界
集中が緩和される。また、Ｎ型基板表面が反転すること
もなくなり、これまで耐圧保持のみであった外周領域も
、６一
電流経路として使用できる。First, when the electrodes 17 and 18 are grounded in a short-circuit state and a positive bias is applied to the drain region, a depletion layer spreads in the N-type substrate 14 and the first isolated R film near the second insulating film 12 The equipotential lines at the interface between the gate electrode and the N-type substrate are shown by broken lines in FIG. 2, and the depletion layer is extended, thereby relaxing the electric field concentration around the gate region. Furthermore, the surface of the N-type substrate is no longer inverted, and the outer peripheral region, which has been used only to maintain voltage resistance, can now be used as a current path.
以上説明したように本発明は、ＰＮ接合上を保護する第
１の絶縁膜の誘電率よシも高い誘電率を有する第２の絶
縁膜によシ、Ｎ型基板表面上の第１の絶縁膜中の電気力
線を変調させ、Ｎ型基板表面近傍の空乏層を伸ばすこと
ができる。As explained above, the present invention provides a second insulating film having a dielectric constant higher than that of the first insulating film that protects the PN junction. By modulating the electric lines of force in the film, the depletion layer near the surface of the N-type substrate can be extended.
また、第２の絶縁膜上は、第１の絶縁膜と同程度の誘電
率を有する第３の絶縁膜により覆われているため、半導
体装置表面での電位分布は一様となシ、フィールドプレ
ート構造におけるプレート端へのイオン集中による特性
変動が起らず、耐圧が向上できる効果がある。Furthermore, since the second insulating film is covered with a third insulating film having a dielectric constant comparable to that of the first insulating film, the potential distribution on the surface of the semiconductor device is not uniform, and the field Characteristic fluctuations due to concentration of ions at the edge of the plate in the plate structure do not occur, and the withstand voltage can be improved.
第１図は本発明の第１の実施例の縦断面図、第２図は本
発明の第２の実施例の縦断面図、第３図は従来のフィー
ルドプレート構造の縦断面図である。FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of a conventional field plate structure.
Claims (2)
において、接合終端を保護している第１の絶縁膜上に第
１の絶縁膜の誘電率より高い誘電率を有する第２の絶縁
膜が形成されていることを特徴とするプレーナ型半導体
装置。(1) In a planar semiconductor device having one or more PN junctions, a second insulating film having a dielectric constant higher than that of the first insulating film is provided on the first insulating film protecting the junction termination. A planar semiconductor device characterized in that:
膜上と第２の絶縁膜上とに第１の絶縁膜と同じ、又は低
い誘電率を有し、且つ膜厚が第２の絶縁膜と同じ、又は
厚い第３の絶縁膜３が形成されていることを特徴とする
特許請求の範囲第１項記載のプレーナ型半導体装置。(2) On the first insulating film on which the second insulating film is not formed and on the second insulating film, the dielectric constant is the same as or lower than that of the first insulating film, and the film thickness is the same as that of the first insulating film, or on the second insulating film. 2. The planar semiconductor device according to claim 1, further comprising a third insulating film 3 that is the same as or thicker than the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13665286A JPS62291121A (en) | 1986-06-11 | 1986-06-11 | Planar type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13665286A JPS62291121A (en) | 1986-06-11 | 1986-06-11 | Planar type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62291121A true JPS62291121A (en) | 1987-12-17 |
Family
ID=15180334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13665286A Pending JPS62291121A (en) | 1986-06-11 | 1986-06-11 | Planar type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62291121A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012105611A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor power device and method for producing same |
| JP2016015482A (en) * | 2014-06-09 | 2016-01-28 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
-
1986
- 1986-06-11 JP JP13665286A patent/JPS62291121A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012105611A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor power device and method for producing same |
| JP5858934B2 (en) * | 2011-02-02 | 2016-02-10 | ローム株式会社 | Semiconductor power device and manufacturing method thereof |
| US9472405B2 (en) | 2011-02-02 | 2016-10-18 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US9947536B2 (en) | 2011-02-02 | 2018-04-17 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US10515805B2 (en) | 2011-02-02 | 2019-12-24 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US10840098B2 (en) | 2011-02-02 | 2020-11-17 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US11276574B2 (en) | 2011-02-02 | 2022-03-15 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US12009213B2 (en) | 2011-02-02 | 2024-06-11 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| JP2016015482A (en) * | 2014-06-09 | 2016-01-28 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| US10361266B2 (en) | 2014-06-09 | 2019-07-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
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