JPS62285498A - Multilayer printed interconnection board - Google Patents

Multilayer printed interconnection board

Info

Publication number
JPS62285498A
JPS62285498A JP12849786A JP12849786A JPS62285498A JP S62285498 A JPS62285498 A JP S62285498A JP 12849786 A JP12849786 A JP 12849786A JP 12849786 A JP12849786 A JP 12849786A JP S62285498 A JPS62285498 A JP S62285498A
Authority
JP
Japan
Prior art keywords
resin
multilayer printed
base material
printed wiring
impregnated base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12849786A
Other languages
Japanese (ja)
Inventor
中井 道雄
小島 甚昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12849786A priority Critical patent/JPS62285498A/en
Publication of JPS62285498A publication Critical patent/JPS62285498A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔技術分野〕 この発明は、電子機器等に用いられる多層プリント配線
基板に関するものである。
[Detailed Description of the Invention] 3. Detailed Description of the Invention [Technical Field] The present invention relates to a multilayer printed wiring board used in electronic equipment and the like.

〔背景技術〕[Background technology]

従来の多層プリント配線基板は、内層材と外層材との間
に樹脂含浸基材を介在させて猜層成形して得られるもの
で、内層材表面の電4X回路の凹凸を充填するため樹脂
含浸基材の樹脂が流出し樹脂含浸基材自身の樹脂量が不
足し、多層プリント配#Si基板のハンダ加工時にミー
ズリング現象が多発し信頼性を低下させていたものであ
る。
Conventional multilayer printed wiring boards are obtained by interposing a resin-impregnated base material between an inner layer material and an outer layer material, and then molding the resin into layers. The resin in the base material leaked out, resulting in an insufficient amount of resin in the resin-impregnated base material itself, and the measling phenomenon occurred frequently during soldering of multilayer printed #Si boards, reducing reliability.

〔発明の目的〕[Purpose of the invention]

本発明の目的とするところはミーズリング現象の発生し
ない多層プリント配線基板を提供することにある。
An object of the present invention is to provide a multilayer printed wiring board in which the measling phenomenon does not occur.

〔発明の開示〕[Disclosure of the invention]

本発明は所要枚数の内層材の各表面に樹脂層を介して樹
脂含浸基材層が存在し、更に最外側に外層材が配設され
てなることを特徴とする多層プリント配線基板のため、
内層材表面の電気回路の凹凸を樹脂充填しても樹脂含浸
基材自身の樹脂量も充分確保できるためミーズリング現
象の発生を大巾に域少させることかできたもので、以下
本発明の詳細な説明する。
The present invention provides a multilayer printed wiring board characterized in that a resin-impregnated base material layer is present on each surface of a required number of inner layer materials via a resin layer, and an outer layer material is further disposed on the outermost side.
Even if the unevenness of the electric circuit on the surface of the inner layer material is filled with resin, the amount of resin in the resin-impregnated base material itself can be ensured, so the occurrence of the measling phenomenon can be greatly reduced. Detailed explanation.

本発明に用いる内層材としては片面又は両面金IIt張
贋層板を加工して、片面又は両面に電電回路を形成した
もので必要とする回路層数に応じて所要枚数用いるもの
である。内層材の表面に配役される樹脂層としてはフェ
ノ−/I/si脂、クレゾール樹脂、エポキシ樹脂、不
飽和ポリスルフォン樹脂、ポリイミド樹脂、ポリブタジ
ェン樹脂、ポリアミド樹脂、ポリスルフォン樹脂、ボリ
フエニレンサμファイド樹脂、ポリフェニレンオキサイ
ド樹脂、ポリブチレンテレフタレート樹脂、弗化mm等
の単独、変性物、混合物等が用いられ、液状樹脂の塗布
、フィルム或はシート状樹脂の載置、或は樹脂含浸基材
からの滲出樹脂による被覆等で樹脂?inを形成するも
のである。液状樹脂の塗布、フィルム或はシート状樹脂
の載置については好ましくは樹脂含浸基材に用いた樹脂
と同種の樹脂を用いることが接層性の点で望′ましいこ
とである。樹脂含浸基材からの滲出樹脂による被覆につ
いては、樹脂含浸基材の樹脂1を3〜5重漱%(以下単
に%と記す)増量して滲出樹脂量の増加を計ったり、樹
脂含浸基材のat脂アフロ−3〜5%低下させ、漬51
成形時の溶出樹脂量を抑制することによシ書出掴脂とし
て内1す材表面の凹凸充填が充分できるように計ったり
することができるものである。
The inner layer material used in the present invention is one in which an electric circuit is formed on one or both sides by processing a single-sided or double-sided gold IIt clad plate, and the required number is used depending on the number of circuit layers required. The resin layer cast on the surface of the inner layer material includes phenol/I/si resin, cresol resin, epoxy resin, unsaturated polysulfone resin, polyimide resin, polybutadiene resin, polyamide resin, polysulfone resin, polyphenylene resin, Polyphenylene oxide resin, polybutylene terephthalate resin, fluorinated mm, etc. alone, modified products, mixtures, etc. are used, and liquid resin is applied, film or sheet resin is placed, or resin oozes from a resin-impregnated base material. Is it covered with resin? This is what forms the in. For coating the liquid resin and placing the film or sheet resin, it is preferable to use the same type of resin as the resin used for the resin-impregnated base material from the viewpoint of adhesion. For coating with exuded resin from a resin-impregnated base material, increase the amount of resin 1 in the resin-impregnated base material by 3 to 5 weight percent (hereinafter simply referred to as %) to measure the increase in the amount of exuded resin, or At fat afro-3-5% reduction, pickled 51
By suppressing the amount of eluted resin during molding, it is possible to sufficiently fill in the irregularities on the surface of the inner material as a gripping grease.

又、液状樹脂の塗布、シート或はシートの載置、樹脂含
浸基材での調整を夫々単独で実施してもよく、必要に応
じて組合せて5!i!施してもよく任意である。樹脂層
の厚みは好ましくは10〜50ミクロンであることが望
ましいことである。即ち10ミクロン未満では内層材表
面の電気回路の凹凸を充分充填でき難く、ωミクロンを
こえると積層成形時の溶融樹脂が多くなり気泡を巻き込
み易くなシ成形性が低下する傾向にあるからである。樹
脂含浸基材としては、8N脂としてはフェノ−、/I/
樹脂、りVシー/l/樹脂、エポキシ樹脂、不飽和ポリ
エステy樹脂、ポリイミド樹脂、ポリゲタジエン樹脂、
ポリアミド樹脂、ポリスルフォン樹脂、ポリフェニレン
サルファイド樹月旨、ポリフェニレンオキサイド樹脂、
ポリブチレンテレフタレート樹脂、弗化樹脂等の単独、
変性物、混合物等が用いられ、基材としては、iフス、
アスベスト等の無機繊維やポリエステ〃、ポリアミド、
ポリビニyアyコーρ、アクリμ等の有機合成繊維や木
綿等の天然繊維からなる織布、不織布、マプト或は紙又
はこれらの岨介せ基材等である。外A材としては片面金
属張漬J板、両面金属張債層板の片面のみ回路形成した
費后板、銅、アμミニウム、真鍮、ニフグル、鉄等の金
属箔を用いることができるものである。以下本発明を実
施例にもとづいて説明する。
Furthermore, applying the liquid resin, placing the sheet or sheets, and adjusting the resin-impregnated base material may be performed individually, or may be combined as necessary. i! It is optional. It is desirable that the thickness of the resin layer is preferably 10 to 50 microns. That is, if it is less than 10 microns, it is difficult to sufficiently fill the unevenness of the electric circuit on the surface of the inner layer material, and if it exceeds ω microns, there will be a large amount of molten resin during laminated molding, which tends to trap air bubbles and deteriorate moldability. . As the resin-impregnated base material, as the 8N resin, pheno-, /I/
Resin, RI V C/L/resin, epoxy resin, unsaturated polyester resin, polyimide resin, polygetadiene resin,
Polyamide resin, polysulfone resin, polyphenylene sulfide juzukiji, polyphenylene oxide resin,
Single polybutylene terephthalate resin, fluorinated resin, etc.
Modified products, mixtures, etc. are used, and the base materials include i-fus,
Inorganic fibers such as asbestos, polyester, polyamide,
These include woven fabrics, nonwoven fabrics, Maputo or paper, or base materials interposed therebetween, made of organic synthetic fibers such as polyvinyl, acrylic, and natural fibers such as cotton. As the outer A material, it is possible to use a single-sided metal-clad J board, a double-sided metal-clad bond board with a circuit formed on only one side, or metal foil such as copper, aluminum, brass, nifgel, or iron. be. The present invention will be explained below based on examples.

実施例1 !侶回鴨部の厚みが70ミクロンである厚み 14の両
面に回路形成した内、響材のと、下面に、厚み0.1F
Jのガラス布にエポキシJ!:J脂フェスを樹脂量4%
1、グ併ゴ旨フロー32%(でなるように含浸、乾燥し
て得た樹脂含浸基材を2枚夫々配設し、更にその最外側
に厚みあミクロンのv4箔を配役した漬1q体を成形圧
力40 L9汐、170°Cで120分閲蹟想成形して
4PJプリント配線基板を得た。
Example 1! The thickness of the inner part is 70 microns.Among the circuits formed on both sides of 14, the thickness of the sounding material is 0.1F on the bottom surface.
Epoxy J on J glass cloth! :Resin amount of J fat festival is 4%
1. Two sheets of resin-impregnated base material obtained by impregnating and drying so as to give a 32% flow, and a V4 foil with a thickness of micron on the outermost side. A 4PJ printed wiring board was obtained by molding under a molding pressure of 40 L9 at 170° C. for 120 minutes.

実施例2 実施例1の樹脂含浸基材の樹脂フローを都翠にした以外
は実施例1と同様に処理して4府プリント配V都基板を
渇た。
Example 2 A 4-piece printed V-shaped board was dried in the same manner as in Example 1, except that the resin flow of the resin-impregnated base material in Example 1 was changed to Dusui.

実施例3 実施例1の樹脂含浸基材の樹脂フローを50%、樹脂フ
ローを28%にした以外は実施例1と同様に処理して4
層プリント配線基板を得た。
Example 3 The resin-impregnated base material of Example 1 was treated in the same manner as in Example 1 except that the resin flow was 50% and the resin flow was 28%.
A layered printed wiring board was obtained.

実施例4 実施例1の内層材の表面にエポキシ樹脂フェノを40ミ
クロン厚になるように塗布してから上、下面に、厚み0
.1 mのガラス布にエボキVa脂ワニスを樹月旨量4
5%、樹月旨フロー32%になるように含浸、乾燥して
得た樹118也浸基材を2枚夫々配設し、更にその最外
側に厚み墨ミクロンの素箔を配設した積層体を成形圧力
4o髪佃、170’Qで120分闇積M成形して4層プ
リント配線基板を得た。
Example 4 Epoxy resin pheno was applied to the surface of the inner layer material of Example 1 to a thickness of 40 microns, and then a layer of 0 thickness was applied to the upper and lower surfaces.
.. Amount of Eboki Va fat varnish on 1 m glass cloth
A laminated layer in which two sheets of wood-impregnated substrates obtained by impregnating and drying to a flow rate of 5% and a flow of 32% are placed, and a bare foil of black micron in thickness is placed on the outermost side. The body was molded in the dark for 120 minutes at a molding pressure of 4°C and 170'Q to obtain a 4-layer printed wiring board.

比較例 実施例1の樹脂含浸基、材の樹脂1を45%、樹脂フロ
ーを32%にした以外は実施例1と同様に処理して4肩
プリント配線基板を得た。
Comparative Example A four-shoulder printed wiring board was obtained in the same manner as in Example 1, except that the resin-impregnated base and resin 1 of Example 1 were changed to 45% and the resin flow was changed to 32%.

〔発明の効果〕〔Effect of the invention〕

実施例1乃至4と比較例のプリント配線基板の’AMf
Amtエツチングし、260’Cのハンダ浴にj秒間フ
ロートし、ハンダ処理面と反対側を水平研磨してミーズ
リングの有無を調べた結果12第1表で明白なように本
発明のものの性能はよく、本発明の多層プリント配線基
板の優れていることを確認した。
'AMf of printed wiring boards of Examples 1 to 4 and comparative example
Amt etched, floated in a solder bath at 260'C for j seconds, horizontally polished the side opposite to the soldered surface, and examined the presence or absence of measling. As is clear from Table 1, the performance of the present invention was We have confirmed that the multilayer printed wiring board of the present invention is excellent.

第   1   表Chapter 1 Table

Claims (2)

【特許請求の範囲】[Claims] (1)所要枚数の内層材の各表面に樹脂層を介して樹脂
含浸基材層が存在し、更に最外側に外層材が配設されて
なることを特徴とする多層プリント配線基板。
(1) A multilayer printed wiring board characterized in that a resin-impregnated base material layer is present on each surface of a required number of inner layer materials via a resin layer, and an outer layer material is further disposed on the outermost side.
(2)樹脂層の厚みが10〜50ミクロンであることを
特徴とする特許請求の範囲第1項記載の多層プリント配
線基板。
(2) The multilayer printed wiring board according to claim 1, wherein the resin layer has a thickness of 10 to 50 microns.
JP12849786A 1986-06-03 1986-06-03 Multilayer printed interconnection board Pending JPS62285498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12849786A JPS62285498A (en) 1986-06-03 1986-06-03 Multilayer printed interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12849786A JPS62285498A (en) 1986-06-03 1986-06-03 Multilayer printed interconnection board

Publications (1)

Publication Number Publication Date
JPS62285498A true JPS62285498A (en) 1987-12-11

Family

ID=14986205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12849786A Pending JPS62285498A (en) 1986-06-03 1986-06-03 Multilayer printed interconnection board

Country Status (1)

Country Link
JP (1) JPS62285498A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750485A (en) * 1993-08-05 1995-02-21 Nec Corp Manufacture of multilayer printed wiring board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6062194A (en) * 1983-09-14 1985-04-10 松下電工株式会社 Method of producing multilayer printed circuit board
JPS60107894A (en) * 1983-11-17 1985-06-13 沖電気工業株式会社 Method of producing multilayer printed circuit board
JPS60257598A (en) * 1984-06-04 1985-12-19 松下電工株式会社 Multilayer printed circuit board
JPS60257592A (en) * 1984-06-04 1985-12-19 松下電工株式会社 Multilayer printed circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6062194A (en) * 1983-09-14 1985-04-10 松下電工株式会社 Method of producing multilayer printed circuit board
JPS60107894A (en) * 1983-11-17 1985-06-13 沖電気工業株式会社 Method of producing multilayer printed circuit board
JPS60257598A (en) * 1984-06-04 1985-12-19 松下電工株式会社 Multilayer printed circuit board
JPS60257592A (en) * 1984-06-04 1985-12-19 松下電工株式会社 Multilayer printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750485A (en) * 1993-08-05 1995-02-21 Nec Corp Manufacture of multilayer printed wiring board

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