JPS62274785A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPS62274785A JPS62274785A JP61118731A JP11873186A JPS62274785A JP S62274785 A JPS62274785 A JP S62274785A JP 61118731 A JP61118731 A JP 61118731A JP 11873186 A JP11873186 A JP 11873186A JP S62274785 A JPS62274785 A JP S62274785A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- thin film
- film semiconductor
- semiconductor layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000010409 thin film Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 15
- 238000005530 etching Methods 0.000 abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 230000007850 degeneration Effects 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明はフォトセンサー等の薄膜半導体装置の製造方法
に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a thin film semiconductor device such as a photosensor.
フォトセンサー、太陽霊地等を構成するフォトダイオー
ドのような薄膜半導体装置は、導電性基板または第１電
極層の上に１．アモルファスシリフン（ａ −Ｓｉ ）
等からなる薄膜半導体層と第２電極層とをこの順序に且
つこれらが互いに少なくとも一部が重なるように積層し
た構造を有している。A thin film semiconductor device such as a photodiode constituting a photosensor, a solar power source, etc. is formed on a conductive substrate or a first electrode layer by 1. Amorphous silicon (a-Si)
It has a structure in which a thin film semiconductor layer and a second electrode layer made of the like are laminated in this order so that at least a portion thereof overlaps with each other.
この構造の薄膜半導体装置は従来から第２図に示す工程
に従って製造されていた。即ち、（ａ）基板１上にパタ
ーン化した第１電極層２を形成し、（ｂ）第１電極層２
上及び基板１上に全面にａ−３ｉのような薄膜半導体層
３を形成し、（Ｃ）薄膜半導体層３を選択的にエツチン
グしてパターン化し、（ｄ）この上に第２電極層４を全
面に形成し、（ｅ）最後に第２電極層４３選択的にエツ
チングしてパターン化することにより製造していた。Thin film semiconductor devices having this structure have conventionally been manufactured according to the steps shown in FIG. That is, (a) a patterned first electrode layer 2 is formed on a substrate 1, and (b) a first electrode layer 2 is formed on a substrate 1.
A thin film semiconductor layer 3 such as a-3i is formed on the top and the entire surface of the substrate 1, (C) the thin film semiconductor layer 3 is selectively etched and patterned, and (d) a second electrode layer 4 is formed on this. was formed on the entire surface, and (e) finally, the second electrode layer 43 was selectively etched to form a pattern.
尚、第２図には基板１上にパターン化した第１電極層２
を設けた例を示したが、第１電極層２はパターン化され
てＩ、ｚなくても良いし、基板１が導電性であれば第１
電極層２を形成せずに導電性基板１をそのま＼第１電極
層としても良い。Note that FIG. 2 shows a first electrode layer 2 patterned on the substrate 1.
Although the first electrode layer 2 does not need to be patterned and I, z is provided, if the substrate 1 is conductive, the first electrode layer 2 may be patterned.
The conductive substrate 1 may be used as the first electrode layer without forming the electrode layer 2.
しかし、第２図の従来の製造方法においては、第２図（
ｂ）〜（Ｃ）の薄膜半導体層３上にレジスト膜ヲ形成し
て選択的にエツチングする工程において、薄膜半導体層
３がレジスト膜の微細な欠陥個所を通して部分的にエツ
チングされること等により、薄膜半導体層３にピンホー
ルが発生して第１電極層２と第２電極層４とが短絡する
ことがあり、製造歩留を低下させる原因になっていた。However, in the conventional manufacturing method shown in FIG.
In the steps of b) to (C) of forming a resist film on the thin film semiconductor layer 3 and selectively etching it, the thin film semiconductor layer 3 is partially etched through minute defects in the resist film, etc. Pinholes may occur in the thin film semiconductor layer 3, causing a short circuit between the first electrode layer 2 and the second electrode layer 4, which causes a reduction in manufacturing yield.
又、この薄膜半導体層３のエツチングの際に、薄膜半導
体層３がレジスト膜やレジスト剥離剤と接触すること等
が原因となって薄膜半導体層３の表面が変質し、第２電
極層４との接触界面の状態が悪化して特性が低下するこ
とがあった。Furthermore, during etching of the thin film semiconductor layer 3, the surface of the thin film semiconductor layer 3 is altered due to contact with the resist film or resist stripping agent, etc., and the second electrode layer 4 and In some cases, the condition of the contact interface deteriorates and the properties deteriorate.
更に、第２図（ｄ）〜（ｅ）の第２電極層４をエツチン
グする工程において、先に形成した第１電極層２も第２
電極層４用の塩酸等のエッチャントにより一部エツチン
グされてしまうという欠点があった。Furthermore, in the step of etching the second electrode layer 4 in FIGS. 2(d) to (e), the previously formed first electrode layer 2 is also
There is a drawback that a portion of the electrode layer 4 is etched by an etchant such as hydrochloric acid.
本発明は、薄膜半導体層でのピンホールの発生及び表面
の変質？防ぎ、しかも第１電極層の不所望のエツチング
をなくし、特性の優れた薄膜半導体装置を高い歩留で製
造する方法企提供することを目的とする。The present invention does not require the generation of pinholes in the thin film semiconductor layer and the deterioration of the surface. It is an object of the present invention to provide a method for manufacturing thin film semiconductor devices with excellent characteristics at a high yield by preventing undesired etching of a first electrode layer.
本発明の薄膜半導体装置の製造方法は、第１′Ｋ。 The method for manufacturing a thin film semiconductor device of the present invention includes the first step.
極層の上に、薄膜半導体層と第２電極層とをこの順序に
互いに少なくとも一部が重なるように積層した薄膜半導
体装置の製造方法において、第１Ｎ極層を具えた基板上
の全面に薄膜半導体層Ｐ形成し、薄膜半導体層上の全面
に第２電極層を形成し、第２電極層を選択的にエツチン
グしてパターン化した後、薄膜半導体層を選択的にエツ
チングしてパターン化することを特徴としている。In a method for manufacturing a thin film semiconductor device in which a thin film semiconductor layer and a second electrode layer are laminated in this order on a pole layer so that at least a portion thereof overlaps with each other, a thin film is formed on the entire surface of a substrate having a first N pole layer. A semiconductor layer P is formed, a second electrode layer is formed on the entire surface of the thin film semiconductor layer, the second electrode layer is selectively etched and patterned, and then the thin film semiconductor layer is selectively etched and patterned. It is characterized by
この方法を第１図により詳しく説明する。This method will be explained in detail with reference to FIG.
（ａ）基板１上にクロム等ご全面に被覆し、選択的にエ
ツチングして第１電極層２を形成する。(a) A first electrode layer 2 is formed by coating the entire surface of the substrate 1 with chromium or the like and selectively etching it.
（ｂ）基板１及び第１電極層２上に全面にＮＩＰ型のａ
−Ｓｉのような薄膜半導体層３Ｐ形成する。(b) NIP type a on the entire surface of the substrate 1 and the first electrode layer 2
- Form a thin film semiconductor layer 3P such as Si.
（ｃ）この薄膜半導体層３の上に全面に酸化インジウム
錫のような第２ｉ！極層４を形成する。従って、薄膜半
導体層３は第２電極層４により完全に被覆されている。(c) A second i film such as indium tin oxide is applied on the entire surface of this thin film semiconductor layer 3! A polar layer 4 is formed. Therefore, the thin film semiconductor layer 3 is completely covered by the second electrode layer 4.
（ｄ）第２電極層４上にレジスト膜を形成し、選択的に
エツチングして第２電極層４をパターン化するっその後
、レジスト膜を剥離する。(d) After forming a resist film on the second electrode layer 4 and patterning the second electrode layer 4 by selectively etching, the resist film is peeled off.
（ｅ）この第２電極層４及び薄膜半導体層３上にレジス
ト膜を形成し、薄膜半導体層３を選択的にエツチングし
てパターン化する。(e) A resist film is formed on the second electrode layer 4 and the thin film semiconductor layer 3, and the thin film semiconductor layer 3 is selectively etched to pattern it.
尚、第１図には基板１上にパターン化した第１電極層２
を設けた例を示したが、第１電極層２はパターン化され
ていなくても良いし、基板１が導電性であれば第１電極
層２を形成せずに導電性基板１が第１電極層を兼ねても
よいことは前記の通りである。Note that FIG. 1 shows a first electrode layer 2 patterned on a substrate 1.
Although the first electrode layer 2 does not need to be patterned, and if the substrate 1 is conductive, the conductive substrate 1 can be formed without forming the first electrode layer 2. As mentioned above, it may also serve as an electrode layer.
薄膜半導体層３の有効表面は第１図（ｃ）及び（ｄ）に
示すように常に第２電極層４と接触して被覆されている
ので、（ｄ）〜（６）のエツチング工程において、薄膜
半導体層３用のエッチャントやレジスト剥離剤の影響号
受けることがなく、従ってピンホールが発生したり又は
表面の変質が起こることがない。Since the effective surface of the thin film semiconductor layer 3 is always in contact with and covered with the second electrode layer 4 as shown in FIGS. 1(c) and (d), in the etching steps (d) to (6), It is not affected by the etchant or resist stripping agent for the thin film semiconductor layer 3, and therefore pinholes or surface deterioration do not occur.
又、第１電極層２及び基板１を被覆している薄膜半導体
層３は第２電極層４のエッチアントによってエツチング
されないので、第１図（ｃ）〜（ｄ）のエツチング工程
において、既に所定の寸法形状に形成しである第１電極
層２は第２電極層４をエツチングする際に薄膜半導体層
３で保護されているので更にエツチングされることがな
い。Furthermore, since the thin film semiconductor layer 3 covering the first electrode layer 2 and the substrate 1 is not etched by the etchant of the second electrode layer 4, it has already been etched in a predetermined manner in the etching steps shown in FIGS. 1(c) to (d). The first electrode layer 2, which is formed to have the dimensions and shape, is protected by the thin film semiconductor layer 3 when etching the second electrode layer 4, so that it is not further etched.
第１図の工程に従って、基板１上に真空蒸着によりＯｒ
を膜厚ｘｏｏｏｆに堆積させ、部分的にレジスト膜を形
成した後、硝酸第２セリウム＋過塩素酸＋水で選択的に
エツチングしてパターン化したａｒの第１電極層２を形
成した（第１図（ａ）参照）。According to the process shown in FIG. 1, Or is deposited on the substrate 1 by vacuum deposition.
was deposited to a film thickness of xooof to partially form a resist film, and then selectively etched with ceric nitrate + perchloric acid + water to form a patterned first electrode layer 2 of ar. (See Figure 1(a)).
パターン化した第１ｉ１極層２及び基板１上に、プラズ
マＣｖＤ法により基板温度２００ＣでＮ工Ｐ構造のａ−
３ｉ薄膜半導体層３を全面に形成した（第１図（ｂ）参
照）。このａ−３ｉ薄膜半導体層３の各層の膜厚ハＮ＝
５００ ！、 、工＝５０００ Ｘ及ヒｐ＝２ｏｏ１で
あった。On the patterned 1i1 pole layer 2 and the substrate 1, an a-
A 3i thin film semiconductor layer 3 was formed on the entire surface (see FIG. 1(b)). The film thickness of each layer of this a-3i thin film semiconductor layer 3 is N=
500! , , engineering = 5000 X and hip = 2oo1.
次に、ａ−３ｉ薄膜半導体層３上に、真空蒸着により膜
厚２０００ Ｒの酸化インジウム錫の第２Ｎ極層４を全
面に形成したく第１図（Ｃ）参照）。Next, a second N-pole layer 4 of indium tin oxide having a thickness of 2000 R is formed over the entire surface of the a-3i thin film semiconductor layer 3 by vacuum evaporation (see FIG. 1C).
＠２電極層４上に部分的にレジスト膜企形成し、第２電
極層４を塩酸を用いて選択的にエツチングすることによ
り、第１電極層２上に第２Ｎ極層４を残すようにパター
ン化した（第１図（ｄ）参照）。@2 A resist film is partially formed on the electrode layer 4, and the second electrode layer 4 is selectively etched using hydrochloric acid, so that the second N-pole layer 4 is left on the first electrode layer 2. It was patterned (see Figure 1(d)).
最後に、パターン化した第２電極層４とａ−Ｓｉ薄膜半
導体層３の上に部分的にレジスト膜を形成し、Ｏｐ ４
１０２（５％）ガスでａ−３ｉ薄膜半導体層３を選択的
にプラズマエツチングして、Ｃｒの第１電極＠２と酸化
インジウム錫の第２ｉ！極層４との間にａ−Ｓｉ薄膜半
導体層３を有するフォトダイオードを形成し、た（第１
図（ｅ）参照）。Finally, a resist film is partially formed on the patterned second electrode layer 4 and the a-Si thin film semiconductor layer 3, and Op 4
The a-3i thin film semiconductor layer 3 is selectively plasma etched with 102 (5%) gas to form a first electrode @2 of Cr and a second electrode @2 of indium tin oxide. A photodiode having an a-Si thin film semiconductor layer 3 is formed between the pole layer 4 and the (first
(See figure (e)).
レト発明によれば、薄膜半導体層にピンホールが発生し
たり、又はその表面が変質したりすることがなく、シか
も第１電極層が不所望なエツチングに、、 ：”らされ
る・二ともないので、特性の優れた薄膜４′１体装置を
従来より工程数を増やすことなく高い歩留で製造するこ
とができる。According to the invention, pinholes are not generated in the thin film semiconductor layer or the surface thereof is altered, and the first electrode layer is not subjected to undesired etching. Therefore, a single thin film 4' device with excellent characteristics can be manufactured at a higher yield without increasing the number of steps than in the past.
第１ス（ａ）〜（ｅ）は本発明の薄膜半導体装置の製造
方法を工程別に示した断面図である。第２ｔｉＵ（ａ）
〜（ｅ）は従来の製造方法を工程別に示した断面図であ
る。
１・・基板 ２・・第１電極層First steps (a) to (e) are cross-sectional views showing each step of the method for manufacturing a thin film semiconductor device of the present invention. 2nd tiU(a)
-(e) are cross-sectional views showing each step of a conventional manufacturing method. 1. Substrate 2. First electrode layer
Claims (1)
をこの順序に互いに少なくとも一部が重なるように積層
した薄膜半導体装置の製造方法において、第１電極層を
具えた基板上の全面に薄膜半導体層を形成し、薄膜半導
体層上の全面に第２電極層を形成し、第２電極層を選択
的にエッチングしてパターン化した後、薄膜半導体層を
選択的にエッチングしてパターン化することを特徴とす
る薄膜半導体装置の製造方法。(1) A method for manufacturing a thin film semiconductor device in which a thin film semiconductor layer and a second electrode layer are laminated in this order on the first electrode layer so that at least a portion thereof overlaps with each other, the substrate comprising the first electrode layer. A thin film semiconductor layer is formed on the entire surface of the thin film semiconductor layer, a second electrode layer is formed on the entire surface of the thin film semiconductor layer, the second electrode layer is selectively etched to pattern it, and then the thin film semiconductor layer is selectively etched. 1. A method of manufacturing a thin film semiconductor device, comprising patterning the device using a method of manufacturing a thin film semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61118731A JPS62274785A (en) | 1986-05-23 | 1986-05-23 | Manufacture of thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61118731A JPS62274785A (en) | 1986-05-23 | 1986-05-23 | Manufacture of thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274785A true JPS62274785A (en) | 1987-11-28 |
Family
ID=14743677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61118731A Pending JPS62274785A (en) | 1986-05-23 | 1986-05-23 | Manufacture of thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274785A (en) |
-
1986
- 1986-05-23 JP JP61118731A patent/JPS62274785A/en active Pending
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