JPS6225731A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce DC component due to a capacity between a gate and a source drain and to improve performance and reliability by adding an offset voltage beforehand to signals applied to the data line of a liquid crystal or to the voltage applied to a counter electrode. CONSTITUTION:One of source drain of a thin film transistor (TFT) 3 is connected to a data line, and another is connected to a liquid crystal 4, and the gate electrode is connected to a control line. The offset voltage is added to the signals applied to the data line or to the voltage applied to a counter transparent electrode to cancel the DC component in order to prevent the application of the DC component to the liquid crystal 4. For instance, the offset voltage applied to the data line is supposed to be +VB. That is, if a time constant determined by a capacity Cgs between the gate and source drain, the capacity CLC of the liquid crystal, the resistance RLC of the liquid crystal and the off resistance ROFF of TFT is longer than a period, the DC component in the state of voltage VB=0 is given approximately by -Vg.Cgs/(Cgs+CLC) when a pulse height is Vg. Accordingly, it is enough to give approximately Vg.Cgs/(Cgs+CLC) as voltage VB.

Description

【発明の詳細な説明】 （発明の利用分野〕 本発明はアクティブマトリクス形液晶表示装置の駆動方
法に係り、特に中間表示に好適で、信頼性を向上させる
駆動方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a driving method for an active matrix liquid crystal display device, and particularly to a driving method suitable for intermediate display and improving reliability.

〔発明の背景〕[Background of the invention]

液晶表示装置を高精細化するため１．アクティブマトリ
クス方式が活発に研究されている。１１５１図にアクテ
ィブマトリクス方式の等価回路を示す。To improve the definition of liquid crystal display devices: 1. Active matrix methods are being actively researched. Figure 1151 shows an equivalent circuit of the active matrix system.

互いに直交する複数の行配線１　（制御線と呼ぶ）と複
数の列配線２（データ線と呼ぶ）との各文点にＦＥＴ３
を配置し、ＦＥＴのソース・ドレインの片方をデータ線
に、もう一方を液晶４に、ゲート電極を制御線に接続す
る。液晶は上記ＦＥ、Ｔと配線をつくりこんだ基板と対
向する全面透明電極の基板との間にはさまれ、電気的に
は容量を形成する。対向電極は一定電位（通常ＯＶ）に
される。FET3 is installed at each point of a plurality of row wirings 1 (referred to as control lines) and a plurality of column wirings 2 (referred to as data lines) that are orthogonal to each other.
One of the source and drain of the FET is connected to the data line, the other to the liquid crystal 4, and the gate electrode to the control line. The liquid crystal is sandwiched between the substrate on which the FE, T and wiring are formed, and the opposing substrate with a completely transparent electrode, forming an electrical capacitor. The counter electrode is brought to a constant potential (usually OV).

通常１周期ごとに正負反転する交流電圧を信号線に印加
して液晶に加わる実効値があるしきい値を越えると配向
し、−偏光方向の光を通過させる。Usually, an alternating current voltage whose polarity is reversed every cycle is applied to the signal line, and when the effective value applied to the liquid crystal exceeds a certain threshold value, the liquid crystal is oriented and allows light in the -polarization direction to pass through.

ＦＥＴとしてはＴ　ｅ　、　ＣｄＳ　、　ｄ　−Ｓ　ｉ
　、　ｐｏｌｙｓｉ等を半導体をもついわゆるＴ　Ｆ　
Ｔ　（Ｔｈｉｎ　ＦｉｌｍＴ　ｒｕｎｓｉｇｔｏｒ）が
用いられる。As FETs, T e , CdS, d-S i
So-called TF with semiconductors such as , polysi etc.
A Thin Film Transistor (T) is used.

１つの画素に着目して第２図を用いてその動作を説明す
る。同図に示すような印加電圧関係をとるのが普通であ
る。ゲートに正の電圧が加わるとＴＦＴ３はオンとなり
、ドレイン電流が流れて液晶の容量４に電荷が注入され
、やがて接点りの電位はデータＶＤと等しくなる。（Ｔ
ＦＴのオン電流が低いとゲートに正電圧が印加されてい
る時間１ｓの間にＬの電位がＶＤに達しない。この時に
は正負波形が対称ではなくなり、液晶に直流成分が加わ
る。）次にゲート電位は０ないし負となり、Ｔ　Ｐ　Ｔ
はオフとなり、液晶に蓄積された電荷は液晶の抵抗ＲＬ
ｃ、容量ＣＬｃ、ＴＦＴのオフ抵抗ＲｏＦＦで決まる時
定数で徐々に放電されてゆく。Focusing on one pixel, its operation will be explained using FIG. Usually, the applied voltage relationship is as shown in the figure. When a positive voltage is applied to the gate, the TFT 3 is turned on, and a drain current flows to inject charge into the capacitor 4 of the liquid crystal, and eventually the potential at the contact point becomes equal to the data VD. (T
If the on-current of the FT is low, the potential of L will not reach VD during the time period 1 s during which a positive voltage is applied to the gate. At this time, the positive and negative waveforms are no longer symmetrical, and a DC component is added to the liquid crystal. ) Then the gate potential becomes 0 or negative, T P T
is turned off, and the charge accumulated in the liquid crystal is transferred to the resistance RL of the liquid crystal.
c, capacitance CLc, and TFT off-resistance RoFF.

通常この時定数を大きくするよう設計する。他の画素の
選択が終了し、−８Ｍ経過するゲート電圧が再び正とな
り、ＴＦＴはオンとなる。今度は−ｖＤの電位がデータ
線に加わり、電荷が接点りからデータ線側に放電され、
やがて接点りの電位も−ｖＤとなる。ゲート電圧が負又
はＯになると先と同じように徐々にこの電位が減衰して
ゆく。Usually, the design is made to increase this time constant. After the selection of other pixels is completed, the gate voltage after -8M becomes positive again, and the TFT is turned on. This time, a potential of -vD is applied to the data line, and the charge is discharged from the contact to the data line side.
Eventually, the potential at the contact point also becomes -vD. When the gate voltage becomes negative or O, this potential gradually attenuates as before.

これによって第２図に示したように液晶には、正負・交
互に反転した電圧が印加される。またデータがＯＶであ
れば液晶にもＯＶがかかる。As a result, as shown in FIG. 2, voltages that are alternately reversed (positive and negative) are applied to the liquid crystal. Moreover, if the data is OV, OV is also applied to the liquid crystal.

これの変形として第３図に示したように液晶の対向電極
に直流電位Ｖ。を印加し、データをＶＤ＋ｖｏ、−ＶＤ
十Ｖ、とｖｃを中心とシテ±ｖＤにふる方法もある。（
鵜飼他「α−３ｉ薄膜トランジスタによるアクティブマ
トリクスＧＨＬＣＤの試作」電子通信学会技術報告ＩＥ
８２−６９）しかし、一般にＭＩＳ形ＦＥＴにおいては
ゲートとソース、ドレイン間に容量（Ｃａ−ｓと呼ぶ）
ｆｉ′″ が存在する。このＣｔ　Ｓがスター構造と呼ばれる通常
のＴＦＴの構造では大きくならざるを得ない。As a modification of this, as shown in FIG. 3, a DC potential V is applied to the opposite electrode of the liquid crystal. is applied, and the data are VD+vo, -VD
There is also a method of applying 10V and VC to the center and ±vD. (
Ukai et al. “Prototype of active matrix GHLCD using α-3i thin film transistor” Institute of Electronics and Communication Engineers Technical Report IE
82-69) However, in general, in MIS type FETs, there is a capacitance (called Ca-s) between the gate, source, and drain.
fi''' exists. This Ct S must be large in a normal TFT structure called a star structure.

力ゝ゛ 第４図はスタが構造ＴＦＴの断面図である。５は絶縁性
基板６がゲートを極、７，８がソース、ドレイン電極、
９が半導体層、１０がゲート絶縁膜である。ゲートとソ
ース、ドレイン間には重なり部分が存在する。一般にこ
の重なり部分の幅は２〜１０μｍ程度であり、Ｃ１３と
しては０．０５〜０．２　ｐ　Ｆとなる。一方、一画素
に接続される液逼の容量Ｃｃｏは画素の大きさにもよる
が、０．１−１ｐＦであり、Ｃ１８とＣＬｃは同程度と
なっている。このように大きなＣ８８が存在すると、液
晶にかかる電圧にゲート電圧パルスがもれこむ。（池田
他「α−３ｉ薄膜トランジスターを用いた液晶ディスプ
レイ」電子通信学会技術研究報告ＣＰＭ８３−２２）第
５図を用いて説明する。まずゲートに正電圧パルスが印
加されると、接点りの電位はパルス高さＶ、に応じてＴ
ＦＴはオンになるのでこの電位を出発点にしてＬの電位
は高くなってゆき、先の場合と同様、ＶＤ□におちつく
。ゲートパルスが立下がると接低くなる。この後、ＴＦ
Ｔはオフ状態であるので電位は保持される。先の場合と
同様、ＣＬｃ。Figure 4 is a sectional view of a TFT with a star structure. 5 is an insulating substrate 6 serving as a gate electrode; 7 and 8 are source and drain electrodes;
9 is a semiconductor layer, and 10 is a gate insulating film. There is an overlap between the gate, source, and drain. Generally, the width of this overlapping portion is about 2 to 10 μm, and C13 is 0.05 to 0.2 pF. On the other hand, the capacitance Cco of a liquid connected to one pixel is 0.1-1 pF, although it depends on the size of the pixel, and C18 and CLc are approximately the same. If such a large C88 exists, the gate voltage pulse will leak into the voltage applied to the liquid crystal. (Ikeda et al. "Liquid Crystal Display Using α-3i Thin Film Transistors" Institute of Electronics and Communication Engineers Technical Research Report CPM83-22) This will be explained using FIG. First, when a positive voltage pulse is applied to the gate, the potential at the contact point changes to T according to the pulse height V.
Since the FT is turned on, the potential of L increases from this potential as a starting point and settles at VD□ as in the previous case. When the gate pulse falls, the contact becomes low. After this, TF
Since T is in the off state, the potential is held. As in the previous case, CLc.

Ｃ３ｌｌ、ＲｏＦＦ、ＲＬｃで決まる時定数で徐々に放
電される。−週期して信号か−ｖＤとなった時にも同様
の事がおきる。その結果、第５図に示すように液晶にか
かる電圧は正負非対称となり、液晶に常にＤＣ成分が加
わる事になる。このようになると第６図のように入力電
圧ＶＤに対し、液晶にかかる実効値電圧は非線形となる
。はなはだしい場合には入力がＯＶであってもゲートパ
ルスのもれこみによって液晶にかかる実効値電圧が液晶
のしきい値を越えてしまい、オン状態となってしまう、
また液晶にＤＣ成分が加えられていると寿命の点で問題
がある。It is gradually discharged with a time constant determined by C3ll, RoFF, and RLc. -The same thing happens when the signal becomes -vD. As a result, as shown in FIG. 5, the voltage applied to the liquid crystal becomes asymmetric between positive and negative, and a DC component is always applied to the liquid crystal. In this case, as shown in FIG. 6, the effective value voltage applied to the liquid crystal becomes nonlinear with respect to the input voltage VD. In extreme cases, even if the input is OV, the leakage of gate pulses will cause the effective voltage applied to the liquid crystal to exceed the threshold of the liquid crystal, resulting in an on state.
Furthermore, if a DC component is added to the liquid crystal, there is a problem in terms of lifespan.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上述したＣ１ｇによる直流成分を減少さ
せ、高性能、高信頼性の液晶表示装置を提供する事にあ
る。An object of the present invention is to provide a liquid crystal display device with high performance and high reliability by reducing the DC component caused by C1g mentioned above.

〔発明の概要〕[Summary of the invention]

本発明では液晶表示装置の構造をかえる事無く、印加す
る波形を変える事によりＤＣ成分を減少させるものであ
る。即ち、液晶に印加しようとする電圧を±ｖＤから＋
ｖＤ　”　Ｖ　ｅ　＋　　Ｖ　Ｏ＋　Ｖ　Ｂと直流的オ
フセット成分を含むよう変える事により実現するもので
ある。In the present invention, the DC component is reduced by changing the applied waveform without changing the structure of the liquid crystal display device. In other words, the voltage to be applied to the liquid crystal is changed from ±vD to +
This is realized by changing it to include a direct current offset component such as vD''Ve+VO+VB.

〔発明の実施例〕[Embodiments of the invention]

（実施例１）第７図にの印加電圧波形を示す、？！号線
に加える電圧を＋ｖ日だけ増加させている。(Example 1) The applied voltage waveform is shown in FIG. 7, ? ! The voltage applied to the line is increased by +v days.

Ｃ，ｓ、ＣＬｏ、ＲＬｃ、ＲｏＦＦで決まる時定数が一
周期に比べて長いとすればｖＩ１１＝０の状態に程度を
与えてやれば良い。実際には高いｖｌの時にもＶＤ＝Ｏ
の部分の画質に問題がでてこなければ良い。If the time constant determined by C, s, CLo, RLc, and RoFF is longer than one cycle, it is sufficient to give a degree to the state of vI11=0. In reality, VD=O even at high vl
It would be fine if there were no problems with the image quality in that part.

（実施例２）これはより簡単な方法で実現しようという
ものである。第８図の印加波形のように信号線にかける
電圧は変えずに、対向電極にかけるＤＣ成分をｖｏから
Ｖ。−ｖｌｌとする。ＶＢの値は先の実施例と同じであ
る。(Embodiment 2) This is an attempt to realize this using a simpler method. As shown in the applied waveform in Figure 8, the DC component applied to the opposing electrode is changed from vo to V without changing the voltage applied to the signal line. -vll. The value of VB is the same as in the previous embodiment.

上記、実施例ではＣ，ＦＩによる直流成分を減少させる
ようにｖ８を設定すると述べたが、直流成分としては先
に述べたようにＴＦＴの速度が遅いための成分も存在す
る。この成分をも打消すようにＶＢを設定する事が望ま
しいのは言うまでもない。In the above embodiment, it has been stated that v8 is set so as to reduce the DC component due to C and FI, but as described above, there is also a component due to the slow speed of the TFT as the DC component. Needless to say, it is desirable to set VB so as to cancel this component as well.

〔発明の効果〕〔Effect of the invention〕

本発明によれば液晶表示装置の構造をかえる事なく、液
晶にかかるＤＣ成分を減少でき、高性能。According to the present invention, the DC component applied to the liquid crystal can be reduced without changing the structure of the liquid crystal display device, resulting in high performance.

高信頼性を有する液晶表示装置が得られる。A highly reliable liquid crystal display device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は液晶表示装置の平面等価回路、第２図。 第３図、及び第５図は従来の駆動方法を説明するための
図、第４図は従来のＴＦＴを示す断面図、第６図はＶＤ
と液晶にかかる実効値電圧の関係を示す図、第７図及び
第８図は本発明の実施例を示す図である。 ｌ・・・データ線、２・・・制御線、３・・・ＴＦＴ。 ４・・・液晶。 ｃ ｔｓ 第４図 ０Ｌ：オーハ゛ラノフ“棒や Ｄ 第、５′図FIG. 1 shows a planar equivalent circuit of a liquid crystal display device, and FIG. 2 shows a planar equivalent circuit of a liquid crystal display device. 3 and 5 are diagrams for explaining the conventional driving method, FIG. 4 is a sectional view showing a conventional TFT, and FIG. 6 is a VD
FIGS. 7 and 8 are diagrams showing an example of the present invention. l...Data line, 2...Control line, 3...TFT. 4...Liquid crystal. c ts Figure 4 0L: Ohranoff's "Bar D" Figure 5'

Claims (1)

【特許請求の範囲】 １、複数個のデータ線と直交する複数個の制御線を備え
、その各文点に薄膜トランジスタ （ＴＦＴ）を形成した基板と、全面透明導電体を形成し
た基板を有し、両基板の間に液晶をはさみ、前記ＴＦＴ
を用いて各画素の液晶に加れる電圧を制御する液晶表示
装置の駆動方法において、液晶に直流成分が加わらない
ようにデータ線に印加する信号又は対向透明電極に印加
する電圧にあらかじめ、オフセット電圧を加え、前記直
流成分を打消す事を特徴とする液晶表示装置の駆動方法
。[Claims] 1. A substrate including a plurality of control lines orthogonal to a plurality of data lines, a thin film transistor (TFT) formed at each point thereof, and a substrate formed with a transparent conductor over the entire surface. , a liquid crystal is sandwiched between both substrates, and the TFT
In a method of driving a liquid crystal display device in which the voltage applied to the liquid crystal of each pixel is controlled using A method for driving a liquid crystal display device, characterized in that the direct current component is added to cancel the direct current component.