JPS62256494A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS62256494A JPS62256494A JP9994586A JP9994586A JPS62256494A JP S62256494 A JPS62256494 A JP S62256494A JP 9994586 A JP9994586 A JP 9994586A JP 9994586 A JP9994586 A JP 9994586A JP S62256494 A JPS62256494 A JP S62256494A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- resist coating
- coating film
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000576 coating method Methods 0.000 claims description 44
- 239000011248 coating agent Substances 0.000 claims description 40
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 230000000873 masking effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 7
- 238000005476 soldering Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000009420 retrofitting Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、電子部品実装用の印刷配線板に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a printed wiring board for mounting electronic components.
（従来の技術）
印刷配線板へ電子部品を実装するにあたり、電子部品を
挿入してリフローまたはディップ等の一括半田付けを行
なった後、更に他の電子部品を後付けする場合には、後
付は用のランドおよび接栓部分等に半田が付着しないよ
うに、マスキングを施す必要がある。(Prior art) When mounting electronic components on a printed wiring board, after inserting the electronic components and performing bulk soldering such as reflow or dip, if other electronic components are to be retrofitted, retrofitting is required. It is necessary to apply masking to prevent solder from adhering to the lands and plugging parts.
従来、このマスキングはマスキングテープを貼付けるこ
とにより行われていたが、作業性を向上させるために、
ビニル系の樹脂からなる可剥性のソルダレジストを必要
な部分に塗布して塗膜を形成する方式が採用されつつあ
る。Traditionally, this masking was done by pasting masking tape, but in order to improve workability,
A method is being adopted in which a peelable solder resist made of vinyl resin is applied to the required areas to form a coating film.
第２図は半田付は面に可剥性のソルダレジスト塗膜が塗
布された印刷配線板を示す平面図である。FIG. 2 is a plan view showing a printed wiring board whose soldering surface is coated with a peelable solder resist coating.
同図において１は基板母材、２はその表面に形成された
導体パターン、３は電子部品のリードが挿入されて一括
半田付けされるスルーホールランド（以下、露出スルー
ホールランドと称する）、４は可剥性のソルダレジスト
塗膜、５は電子部品を後付けするためにソルダレジスト
塗膜４により覆われたスルーホールランド（以下、被覆
スルーホールランドと称する）、６はやはりソルダレジ
スト塗膜４により覆われた接栓である。In the figure, 1 is a substrate base material, 2 is a conductive pattern formed on its surface, 3 is a through-hole land (hereinafter referred to as an exposed through-hole land) into which electronic component leads are inserted and soldered together, and 4 5 is a peelable solder resist coating, 5 is a through-hole land covered with a solder resist coating 4 (hereinafter referred to as a covered through-hole land) for retrofitting electronic components, and 6 is also a solder resist coating 4. It is a plug covered by
ところでこのような印刷配線板は、一括半田付けが終了
した後に基板母材１からソルダレジスト塗膜４を剥がさ
なければならないが、ソルダレジスト塗膜４は基板母材
１上に点在して設けられているため、それぞれのソルダ
レジスト塗膜を別々に剥がざなれけばならず、その作業
に多くの手間と時間がかかるという問題があった。By the way, in such a printed wiring board, the solder resist coating 4 must be peeled off from the substrate base material 1 after the batch soldering is completed, but the solder resist coating 4 is provided in spots on the substrate base material 1. Therefore, each solder resist coating must be peeled off separately, which poses the problem of requiring a lot of effort and time.
（発明が解決しようとする問題点）
本発明は上述したような事情によりなされたもので、半
田に対するマスキングが必要な複数箇所に可剥性のレジ
スト塗膜が形成されてなる印刷配線板において、レジス
ト塗膜を剥がす作業を極めて容易にすることを目的とし
ている。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and provides a printed wiring board in which a peelable resist coating is formed at multiple locations where masking for solder is required. The purpose is to make it extremely easy to remove resist coatings.
° ［発明の構成］
（問題点を解決するための手段）
本発明の印刷配線板は、半田に対するマスキングが必要
な複数箇所に可剥性のレジスト塗膜が形成され、各レジ
スト塗膜がそれぞれ可剥性のレジストブリッジ塗膜によ
り連結されたものである。° [Structure of the Invention] (Means for Solving the Problems) In the printed wiring board of the present invention, peelable resist coating films are formed at multiple locations where masking for solder is required, and each resist coating film is They are connected by a peelable resist bridge coating.
（作用）
本発明の印刷配線板は、いずれか１箇所のレジスト塗膜
を剥がすと、隣接するレジスト塗膜も連鎖的に剥がれる
ので、一括半田付けの後にレジスト塗膜を剥がす作業が
極めて容易になる。(Function) In the printed wiring board of the present invention, when one resist coating film is peeled off, the adjacent resist coating films are also peeled off in a chain reaction, making it extremely easy to remove the resist coating film after batch soldering. Become.
（実施例）
以下、本発明の実施例の詳細を図面に基づいて説明する
。(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.
第１図は本発明の印刷配線板の一実施例の構成を示す平
面図であり、第２図と共通する部分には共通の符号が付
されている。FIG. 1 is a plan view showing the structure of an embodiment of the printed wiring board of the present invention, and parts common to those in FIG. 2 are given the same reference numerals.
同図において１は基板母材、２はその表面に形成された
導体パターン、３は電子部品のリードが挿入されて一括
半田付けされる露出スルーホールランド、４は可剥性の
ソルダレジスト塗膜、５は電子部品を後付けするために
ソルダレジスト塗膜４により覆われた被覆スルーホール
ランド、６はやはりソルダレジスト塗膜４により覆われ
た接栓、そして７は各ソルダレジスト塗膜４を連結する
レジストブリッジ塗膜である。In the figure, 1 is the substrate base material, 2 is a conductor pattern formed on its surface, 3 is an exposed through-hole land into which electronic component leads are inserted and soldered all at once, and 4 is a peelable solder resist coating. , 5 is a covered through-hole land covered with a solder resist coating 4 for retrofitting electronic components, 6 is a plug also covered with a solder resist coating 4, and 7 is a connection between each solder resist coating 4. It is a resist bridge coating film.
なお本実施例の印刷配線板において、スルーボールラン
ド５を覆うソルダレジスト塗膜４と各ソルダレジスト塗
膜４を連結するレジストブリッジ塗膜７とは同一工程で
形成されている。In the printed wiring board of this embodiment, the solder resist coating film 4 that covers the through ball lands 5 and the resist bridge coating film 7 that connects each solder resist coating film 4 are formed in the same process.
すなわち本実施例の印刷配線板は、基板母材の所定の位
置に電子部品のリード挿入用の孔を穿設した後、８孔の
開口部の周囲にスルーホールランドを形成し、必要に応
じて各ランドおよび接栓の部分を除いて非剥離性のソル
ダレジスト塗膜を形成し、更に電子部品が後付けされる
べきスルーホールランド、接栓およびこれらの間に一括
して可剥性のソルダレジストを塗布し、乾燥することに
より得ることができる。In other words, in the printed wiring board of this example, after holes for inserting leads of electronic components are drilled at predetermined positions in the substrate base material, through-hole lands are formed around the openings of the eight holes, and holes are formed as needed. A non-peelable solder resist film is formed on each land and plug area, and a peelable solder resist is applied all at once to the through-hole lands and plugs to which electronic components are to be attached, and between them. It can be obtained by applying a resist and drying it.
かくして本発明の印刷配線板では、リフローまたはディ
ップ等の一括半田付けが終了した俊にソルダレジスト塗
膜を剥がす際、いずれか１箇所のツルダレジス１〜塗膜
を剥がすと、隣接するソルダレジスト塗膜が連鎖的に剥
がれる。Thus, in the printed wiring board of the present invention, when the solder resist coating film is peeled off immediately after batch soldering such as reflow or dip soldering, if any one of the solder resist coatings is peeled off, the adjacent solder resist coating film will be removed. peels off in a chain.
なお本実施例では、各ソルダレジスト塗膜と、その間の
レジストブリッジ塗膜とが同一工程により形成されてい
るが、本発明はこれに限定されるものではない。たとえ
ば各ソルダレジスト塗膜４を形成し、次の工程でレジス
トブリッジ塗膜７を形成してもよい。In this example, each solder resist coating film and the resist bridge coating film therebetween are formed by the same process, but the present invention is not limited to this. For example, each solder resist coating 4 may be formed, and the resist bridge coating 7 may be formed in the next step.
また本発明の印刷配線板では、各ソルダレジスト塗膜４
が比較的細いレジストブリッジ塗膜７により連結されて
いるが、レジストブリッジ塗膜７は露出スルーホールラ
ンド３を損なわない限り、基板母材１上のオープンスペ
ースに任意の形状で形成することができる。Further, in the printed wiring board of the present invention, each solder resist coating 4
are connected by a relatively thin resist bridge coating film 7, but the resist bridge coating film 7 can be formed in any shape in the open space on the substrate base material 1 as long as the exposed through hole land 3 is not damaged. .
［発明の効果］
以上説明したように本発明の印刷配線板は、各レジスト
塗膜がそれぞれレジストブリッジ塗膜により連結されて
いるので、各レジスト塗膜を連鎖的に剥がすことができ
、レジスト塗膜を剥がす作業が極めて容易になる。[Effects of the Invention] As explained above, in the printed wiring board of the present invention, each resist coating film is connected by a resist bridge coating film, so each resist coating film can be peeled off in a chain, and the resist coating The work of peeling off the film becomes extremely easy.
第１図は本発明の印刷配線板の一実施例を示す平面図、
第２図は従来の印刷配線板の一例を示す平面図である。
１・・・・・・・・・基板母材
２・・・・・・・・・導体パターン
３・・・・・・・・・露出スルーホールランド４・・・
・・・・・・ソルダレジスト塗膜５・・・・・・・・・
被覆スルーホールランド６・・・・・・・・・接 栓
７・・・・・・・・・レジストブリッジＩＩＦＪ出願人
株式会社 東芝
代理人 弁理士 須 山 佐 −
；Ｆ″＜１ｖｌ
第２図FIG. 1 is a plan view showing an embodiment of the printed wiring board of the present invention;
FIG. 2 is a plan view showing an example of a conventional printed wiring board. 1...Base material 2...Conductor pattern 3...Exposed through-hole land 4...
・・・・・・Solder resist coating film 5・・・・・・・・・
Covered through-hole land 6・・・・・・・・・Plug 7・・・・・・Resist Bridge IIFJ Applicant Toshiba Corporation Representative Patent Attorney Suyama Sa − ;F″<1vl Figure 2
Claims (2)
性のレジスト塗膜が形成されてなる印刷配線板において
、前記各レジスト塗膜がそれぞれ可剥性のレジストブリ
ッジ塗膜により連結されていることを特徴とする印刷配
線板。(1) In a printed wiring board in which peelable resist coatings are formed at multiple locations where masking for solder is required, each of the resist coatings is connected by a peelable resist bridge coating. A printed wiring board featuring:
工程により形成されている特許請求の範囲第１項記載の
印刷配線板。(2) The printed wiring board according to claim 1, wherein the resist coating film and the resist bridge coating film are formed by the same process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9994586A JPS62256494A (en) | 1986-04-30 | 1986-04-30 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9994586A JPS62256494A (en) | 1986-04-30 | 1986-04-30 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62256494A true JPS62256494A (en) | 1987-11-09 |
Family
ID=14260843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9994586A Pending JPS62256494A (en) | 1986-04-30 | 1986-04-30 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62256494A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS617069B2 (en) * | 1980-07-28 | 1986-03-04 | Victor Company Of Japan |
-
1986
- 1986-04-30 JP JP9994586A patent/JPS62256494A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS617069B2 (en) * | 1980-07-28 | 1986-03-04 | Victor Company Of Japan |
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