JPS62254091A - Electronic timepiece - Google Patents

Electronic timepiece

Info

Publication number
JPS62254091A
JPS62254091A JP8100787A JP8100787A JPS62254091A JP S62254091 A JPS62254091 A JP S62254091A JP 8100787 A JP8100787 A JP 8100787A JP 8100787 A JP8100787 A JP 8100787A JP S62254091 A JPS62254091 A JP S62254091A
Authority
JP
Japan
Prior art keywords
voltage
transistor
constant voltage
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8100787A
Other languages
Japanese (ja)
Inventor
Hajime Kobayashi
肇 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP8100787A priority Critical patent/JPS62254091A/en
Publication of JPS62254091A publication Critical patent/JPS62254091A/en
Pending legal-status Critical Current

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  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To obtain a stable power source despite changes in the load, by outputting a specified range of voltage to a negative-side terminal of a lithium battery to keep the oscillation from being stopped when a power source voltage changes sharply. CONSTITUTION:A block B is a constant voltage circuit to form an auxiliary power source. Transistors T3 and T4 are at the inputs of a differential amplifier and the transistor T4 works in a depression mode unlike the others working in the enhancement mode to be a reference of the constant voltage circuit, always being conducting. A voltage compared with an input voltage of the transistor T3 is amplified with transistors T6 and T7 and connected to a transistor T5 acting as switch for the supply of a constant voltage. Transistors T1 and T2 change over an output voltage of the constant voltage circuit. When the oscillation stops, an output of a block D moves to a low level and the transistor T2 is turned ON to output 1.55V, for instance. When the lighting of a lamp or the driving of a buzzer is carried out, the transistor T1 is turned ON to output 1.35V, for instance. The transistor T5 also controls the timing of supplying a constant voltage.

Description

【発明の詳細な説明】 本発明a比較的内部低抗の尚い電池を便用した時計の補
助機構が作動したときに電源電圧が急激に減少し、その
時に主要部分が作動しなくならないエラに補助電fAを
作動させ九電子時計に関する。
Detailed Description of the Invention The present invention a solves an error in which when the auxiliary mechanism of a watch that conveniently uses a battery with relatively low internal resistance is activated, the power supply voltage suddenly decreases and the main parts do not stop working at that time. This relates to a nine-electronic watch that operates the auxiliary electric fA.

従来の電源装置としてalを子時計a定電圧装置あない
に、大容量のコンデンサを用いるコトにニジ電源に余裕
?待たせ、dカの変動を防出していた。−例として1.
5vの電圧を約t1vrukめて常時1.1vで作動さ
せておき、消費電力の大きな液晶表示用のランプを点燈
したときHIIt源電圧が変動して時計ムーブメントに
影響k 丁6 ;Fc h 、ランプ電源は電池1.5
vから直接供給していた。ま*、短時間の電源変動に対
してにコンデンサを電池と並列に接続して電源のりップ
ル會防止していた。これに対して最近信頼性の高い6v
に近いリナウム電池が実用され出したが、照明用のラン
プあ小いにアラーム用のブザー−!kf’ll:動さぜ
ゐと電池の内部抵抗が比軟釣人であるため電圧が2v近
くまで低下する。したがって時計のムーブメントを駆動
する分向1発掘1表示体駆動回路等にその影響r受けな
い工うに対策tしなければならない。
As a conventional power supply device, do you have sufficient power supply to use a large capacity capacitor instead of using AL as a slave clock or a constant voltage device? By making them wait, they were preventing fluctuations in d power. -For example 1.
When the voltage of 5V is changed by about t1vruk and the voltage is constantly operated at 1.1V, and the lamp for the liquid crystal display which consumes a large amount of power is turned on, the HIIT source voltage fluctuates and affects the clock movement. Lamp power source is battery 1.5
It was supplied directly from v. *In order to prevent short-term power fluctuations, a capacitor was connected in parallel with the battery to prevent ripples in the power supply. On the other hand, recently reliable 6v
Linium batteries, which are similar to linium batteries, have been put into practical use, but there are small lamps for lighting and buzzers for alarms! kf'll: When the battery is moved, the internal resistance of the battery is relatively soft, so the voltage drops to nearly 2V. Therefore, measures must be taken to ensure that the circuits for driving the clock movement, such as the display drive circuit, are not affected by this.

本発明はかかる欠点ケ除くため圧電池剋圧會)挿圧して
常時に使用しており、%に大負荀が作動したときに時計
のムーブメントVC,aEOU路的に別の定電圧電源を
供給するものである。
In order to eliminate such drawbacks, the present invention uses a pressure battery (pressure pump) and uses it at all times, and when the large voltage regulator operates, a separate constant voltage power source is supplied to the watch movement VC and aEOU. It is something to do.

本発明の目的に負荷の変動に対して安定化した電源1*
え九時計を提供することにある。
A power supply stabilized against load fluctuations for the purpose of the present invention 1*
Our goal is to provide nine clocks.

本発明の他の目的に内部抵抗の高い′1池忙安定化して
1史つことにあ;bo 本発明のさらに曲の目的rIス負荷が作動したときタイ
マー装置が作動して一定時間琢aすることにLジ電池電
圧が完全VC,復帰丁心までホールドする機能を備えた
安全装置r提供することにあめ。
Another object of the present invention is to stabilize a high-internal-resistance battery for a certain period of time. In addition, we provide a safety device with a function to hold the voltage of the L-type battery until it returns to full VC.

第1図B本発明による回路図である。分向回路FF1工
りFF12までに入力信号1024H2r分周して1.
5秒信号tとり出している。時計のムーブメントを駆動
する(口)路より1024H2の信号をもらっているが
、1.5秒信号金他の手段、例えばORの時定数r利用
してとり出してもかまわない。この1.5秒信号a俊述
する時計の負荷としてランプ、ブザー等の人1!流の負
荷が働いて電源電圧が下がったときに補助′亀源が働く
fこめのタイマー信号として用いられる。
FIG. 1B is a circuit diagram according to the present invention. The input signal 1024H2r is divided by dividing circuit FF1 and FF12 to 1.
I am taking out the 5 second signal t. A signal of 1024H2 is obtained from the circuit that drives the clock movement, but it may be obtained using a 1.5 second signal or other means, such as using the OR time constant r. This 1.5 second signal a-ton describes the clock's load as a lamp, buzzer, etc. It is used as a timer signal to activate an auxiliary voltage source when the power supply voltage drops due to a current load.

Aブロックは降出回路部であり、リチウム電池(6V 
〜2.2V )2−VI3.2とVLID間に接続する
The A block is the step-down circuit section and is powered by a lithium battery (6V
~2.2V) 2-Connect between VI3.2 and VLID.

−t−rコンチンv03 と04 ’l直列に接続した
状態に一■882とvDD間の電圧で光電する。矢にコ
ンデンサC3と04の極性が同極になるようにして並列
に接続する。この動作を裸ジ返丁ことによってコンデン
サC3の両端、丁なわち−V88.とVDD間からリチ
ウム電池の電圧の半分の電圧(1,5V〜t I V 
)全取り出している。
-trContin is connected in series with v03 and 04'l and is photoelectrically charged at a voltage between 1882 and vDD. Connect capacitors C3 and 04 in parallel so that their polarities are the same as shown by the arrow. By repeating this operation, both ends of the capacitor C3, namely -V88. and VDD to half the voltage of the lithium battery (1.5V to t I V
) All are taken out.

Bブロックは補助電源tつくり出丁定電圧回路である、
トランジスタTs * Tj In差動増幅器の入力で
あり%T4μ他のトランジスタがエンノ・ンスメントモ
ードであると異なりデプレションモードのトランジスタ
であり、常時導通状態になってい王、定電圧回路′電圧
の基準となっている。T3の入力端子と比較され九′砥
圧rsTs*”yで増幅されて定′成圧供給のスイッチ
用トランジスタTsに接続されている。トランジスタT
、〜T+4!’!定電流を供給するためのものである。
The B block is a constant voltage circuit that creates an auxiliary power supply.
Transistor Ts * Tj In is the input of the differential amplifier and is a depletion mode transistor, unlike the other transistors which are in the enforcement mode, and is always in a conductive state. It becomes. It is compared with the input terminal of T3, is amplified by 9' abrasive pressure rsTs*"y, and is connected to a switching transistor Ts that supplies a constant voltage. Transistor T
,~T+4! '! It is for supplying constant current.

’rt 、T、は定電圧回路の出力電圧を切り換える窺
めのトランジスタであり、発逗が停止した場合μDブロ
ックの出力クローレベルとなり、Ttがオンし1.55
Vが出力される。またランプ点燈とブザー駆動時にはT
、がオンレ1.55 Vが出力される。またTsH定電
圧供給のタイミングも制御しており、ランプやブザーの
大負荷の信号が入ってから、クロックパルス1024H
2の1クロック分だケ定電圧胞路からの供給に遅らせる
。また降圧回路動作の1.5vに復帰するときにa大負
荷の信号が解除されてから1.5秒後に定電圧回路から
の供給を切る。
'rt and T are transistors that switch the output voltage of the constant voltage circuit, and when the start-up stops, the output of the μD block becomes the low level, and Tt turns on and the voltage becomes 1.55.
V is output. Also, T when lighting the lamp and driving the buzzer.
, 1.55 V is output. It also controls the timing of TsH constant voltage supply, and after receiving a heavy load signal from a lamp or buzzer, clock pulse 1024H is applied.
The supply from the constant voltage cell line is delayed by one clock of 2. Furthermore, when the voltage is restored to 1.5V for the step-down circuit operation, the supply from the constant voltage circuit is cut off 1.5 seconds after the a large load signal is released.

Cフロックはフリップ・フロップ21固から構成される
遅延回路であり、前述したクロックパルス1024Hz
の1クロック分の遅ff1kつくっている。
The C-flock is a delay circuit composed of 21 flip-flops, and the clock pulse 1024Hz mentioned above is
A delay ff1k of one clock is created.

Dブロックは入力クロック1024Hzの信号の有無を
検出する回路である。1024Hz信号が入力されると
コンデンサOt と抵抗にLる遅延に工りEX・ORの
出力にパルス音生じ、コンデンサCIにローレベルに光
電される。従って1(1241(z信号が入力されてい
る時μDブロックの出力はハイレベルになる。1024
H2信号が停止した時はEx・ORの出力はローレベル
に固定になり、コンデンサC!α並列に接続された抵抗
により放電されハイレベルとなり、Dブムツクの出力は
ローレベルとなる。従ってフリップ・フロップFF1〜
’FF12からなるタイマー回路のFF8〜FF12が
リセットされ定電圧回路のBブロックが動作し、トラン
ジスタTt モオンし、−■B II 1の端子にi、
5svl出カフ4゜E〕゛ロック框ブザー駆l1liI
l信号インターフェイスである。入力端子全ハイレベル
にすることに工り出力端子もハイレベルになり、これが
外部に設けたブザー、1g1llll!+回路の制御1
3号となる。−万、Eフロックからげタイマー回路のF
Il’8〜FIP12を制御する信号を取り出しである
ので、入力信号全ハイレベルに設定子^と定電圧回路の
Bフロックが動作し、トランジスタTIがオンL/% 
 Vastの端子に1.557を出力する。
The D block is a circuit that detects the presence or absence of an input clock signal of 1024 Hz. When a 1024 Hz signal is input, a pulse sound is generated at the output of EX/OR due to the delay caused by the capacitor Ot and the resistor, and the signal is photoelectronized to a low level to the capacitor CI. Therefore, 1 (1241 (When the z signal is input, the output of the μD block becomes high level.1024
When the H2 signal stops, the output of Ex・OR is fixed at low level, and the capacitor C! α is discharged by the resistor connected in parallel and becomes a high level, and the output of the D boom becomes a low level. Therefore, flip-flop FF1~
FF8 to FF12 of the timer circuit consisting of FF12 are reset, the B block of the constant voltage circuit is activated, the transistor Tt is turned on, and the -■B II 1 terminal is connected to i,
5svl output cuff 4゜E゛lock frame buzzer drive l1liI
l signal interface. By setting all the input terminals to high level, the output terminal also goes to high level, and this is the external buzzer, 1g1llll! +Circuit control 1
It will be number 3. -10,000, F of E flock Karaage timer circuit
Since the signals that control Il'8 to FIP12 are taken out, the setter ^ and the constant voltage circuit B block operate when all input signals are at high level, and the transistor TI turns on L/%.
Output 1.557 to the Vast terminal.

Fフロックにランプ点燈信号インターフェイスである。This is a lamp lighting signal interface to the F flock.

入力端子tハイレベルにすることにLり出力端子もハイ
レベルになり、この信号で外部に設けたランプ回路を制
#する。また前述したEブロックと同様に定電圧回路に
エリー■、□端子に1、55 Vを出力する。
When the input terminal t is set to high level, the L output terminal also becomes high level, and this signal controls the lamp circuit provided outside. Also, like the E block mentioned above, 1.55 V is output to the Erie ■ and □ terminals of the constant voltage circuit.

本発明a電源電圧+vDD+  ”5112間に大電流
の負荷が与えられたため、その電源電圧が急減に変動し
て一■■、に所定の低位が倚られなかったとき、例えば
電源が2vに下り、出力が1■となると発振がとまり時
計の機能に悪影響するため、その際に一■、5.に1,
5vから1.5vの出力を出し、発振全停止させず、時
計全土めない工うに配慮されている。本発明は電源電池
の電圧が高く、内部抵抗の比較的高い電源を用い′fc
磯批について利用価値が鳥いものである。
In the present invention, when a large current load is applied between power supply voltage +vDD+ and 5112, the power supply voltage fluctuates rapidly and cannot reach a predetermined low level, for example, when the power supply voltage drops to 2V, When the output reaches 1■, oscillation stops and has a negative effect on the function of the clock.
It outputs an output of 5v to 1.5v, and is designed to prevent oscillation from completely stopping and preventing the entire clock from going off. The present invention uses a power source with a high voltage battery and a relatively high internal resistance.
The utility value of Isochuri is amazing.

【図面の簡単な説明】[Brief explanation of drawings]

第1内σ本発明になる回路図でおる。 C3,C4に降圧コンデンサ、T、〜T1.は補助電源
出力用トランジスタ、FFI〜FF12[タイマー用分
周1」路。 以上
The first inner σ is a circuit diagram according to the present invention. C3, C4 are step-down capacitors, T, ~T1. is an auxiliary power output transistor, FFI to FF12 [frequency division 1 for timer] path. that's all

Claims (1)

【特許請求の範囲】[Claims] 電源電池と、前記電源電池の電池電圧をコンデンサの直
・並列の切換えによつて降圧する降圧回路Aと、前記降
圧回路の降圧電圧を受ける時計の電子回路と、前記電源
電池から電圧供給を受けるブザー、ランプ等の補助機構
とを備える電子時計において、前記補助機構の駆動信号
を受けて前記電池電圧より一定電圧を形成する定電圧回
路Bと、前記駆動信号を受けて前記電子回路への前記降
圧電圧の供給を停止する第1のゲートNR_3、NR_
4と、前記駆動信号を受けて前記一定電圧を前記電子回
路に供給する第2のゲートT_5とを具備することを特
徴とする電子時計。
A power supply battery, a step-down circuit A that steps down the battery voltage of the power supply battery by switching between series and parallel capacitors, an electronic circuit of a watch that receives the step-down voltage of the step-down circuit, and receives voltage supply from the power supply battery. In an electronic watch equipped with an auxiliary mechanism such as a buzzer or a lamp, a constant voltage circuit B receives a drive signal from the auxiliary mechanism and forms a constant voltage from the battery voltage; First gate NR_3, NR_ that stops supplying the step-down voltage
4, and a second gate T_5 that receives the drive signal and supplies the constant voltage to the electronic circuit.
JP8100787A 1987-04-03 1987-04-03 Electronic timepiece Pending JPS62254091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8100787A JPS62254091A (en) 1987-04-03 1987-04-03 Electronic timepiece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8100787A JPS62254091A (en) 1987-04-03 1987-04-03 Electronic timepiece

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP17181379A Division JPS5696273A (en) 1979-12-28 1979-12-28 Electronic timepiece

Publications (1)

Publication Number Publication Date
JPS62254091A true JPS62254091A (en) 1987-11-05

Family

ID=13734454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8100787A Pending JPS62254091A (en) 1987-04-03 1987-04-03 Electronic timepiece

Country Status (1)

Country Link
JP (1) JPS62254091A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240371A (en) * 1975-09-27 1977-03-29 Citizen Watch Co Ltd Electronic watch
JPS53101473A (en) * 1977-02-16 1978-09-04 Seiko Instr & Electronics Ltd Electronic watch
JPS549665A (en) * 1977-06-23 1979-01-24 Nippon Precision Circuits Electronic timepiece
JPS5527926A (en) * 1978-08-18 1980-02-28 Seiko Instr & Electronics Ltd Electronic clock
JPS6240671A (en) * 1985-08-16 1987-02-21 Toshiba Corp Track jumping-over control circuit for disk reproducing device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240371A (en) * 1975-09-27 1977-03-29 Citizen Watch Co Ltd Electronic watch
JPS53101473A (en) * 1977-02-16 1978-09-04 Seiko Instr & Electronics Ltd Electronic watch
JPS549665A (en) * 1977-06-23 1979-01-24 Nippon Precision Circuits Electronic timepiece
JPS5527926A (en) * 1978-08-18 1980-02-28 Seiko Instr & Electronics Ltd Electronic clock
JPS6240671A (en) * 1985-08-16 1987-02-21 Toshiba Corp Track jumping-over control circuit for disk reproducing device

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