JPS62242362A - Hybrid optical waveguide circuit - Google Patents

Hybrid optical waveguide circuit

Info

Publication number
JPS62242362A
JPS62242362A JP61085260A JP8526086A JPS62242362A JP S62242362 A JPS62242362 A JP S62242362A JP 61085260 A JP61085260 A JP 61085260A JP 8526086 A JP8526086 A JP 8526086A JP S62242362 A JPS62242362 A JP S62242362A
Authority
JP
Japan
Prior art keywords
optical waveguide
waveguide circuit
optical
active layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61085260A
Other languages
Japanese (ja)
Other versions
JPH0654805B2 (en
Inventor
Yasubumi Yamada
泰文 山田
Hiroshi Terui
博 照井
Akira Himeno
明 姫野
Morio Kobayashi
盛男 小林
Makoto Yamada
誠 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP61085260A priority Critical patent/JPH0654805B2/en
Publication of JPS62242362A publication Critical patent/JPS62242362A/en
Publication of JPH0654805B2 publication Critical patent/JPH0654805B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025—Array arrangements, e.g. constituted by discrete laser diodes or laser bar
    • H01S5/4031—Edge-emitting structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optical Integrated Circuits (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To enable installation of semiconductor laser array elements in the P-side down condition having extremely high positioning accuracy by a method wherein both of optical waveguide circuit parts and element retaining parts are projectedly provided on a substrate making the optical waveguide circuit parts so as to become higher than the element retaining part. CONSTITUTION:A semiconductor laser array 4 is loaded on element retainers 7 in the P-side down condition as to make the edge surface on the active layer side (the P-side) of the laser array 4 to come in contact with the upper surface of the element retainers 7. Because multistage step difference are formed to the optical circuit substrate and the element retainers 7 are formed in a projecting type, when the semiconductor laser and the optical waveguide circuit are hybridizedly integrated, equipment of the element thereof can be attained in the P-side down condition having high precision, of positioning and at the same time, in the elements formed in an array, because electric connection is performed according to gold wires 6 utilizing space on the lower side of the semiconductor laser 4 without forming an electric wiring pattern on the substrate, electric wiring can be attained while maintaining electric insulation between the respective elements.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、光通信、光情報処理において必要となる元集
権回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central control circuit required in optical communication and optical information processing.

〔従来の技術〕[Conventional technology]

光等波回路と光半導体素子等を同一基板上で偵合一体化
したへイ１リッド元導波回路は、元スイッチ、光合分波
器等の光通信、光１ｗ報処理用元回路の実現手段として
期待されている。しかし、この分野は未だ基礎研究段階
にあり、これまでに実用に用いられている光回路はほと
んどない。The 1-lid original waveguide circuit, which integrates an optical equal-wave circuit and optical semiconductor elements on the same substrate, realizes the original circuit for optical communication and optical 1W information processing such as original switches and optical multiplexers/demultiplexers. It is expected to be used as a means. However, this field is still at the basic research stage, and so far very few optical circuits have been put into practical use.

ところで、この棟のハイブリッド光集槓回路のプロット
タイプとして、Ｓｉ基板上に形成した石英系光導波路と
半導体レーザとを複合一体化した例が報告されている（
ＬＨ，アレイ　その他（Ｈ。By the way, as a plot type of the hybrid optical concentrator circuit in this building, an example has been reported in which a silica-based optical waveguide formed on a Si substrate and a semiconductor laser are integrated (
LH, Array Others (H.

Ｔｅｒｕｊ　　ｅｔａｌ、）エレクトロニクス　レター
ズ（Ｅｌｅｃｔｒｏｎ、　Ｌｅｔｔ、　）　２１刊（１
９８５）６４６ページ】。Teruj etal, ) Electronics Letters (Electron, Lett, ) 21st issue (1
985) Page 646].

第Ｓ図（ａ）〜（Ｃ）は、この際の半導体レーザと光導
波路との複合化方法を示したものである。図中符号１は
Ｓｉ基板、ｌａは基板表面、２は石英系光導波路、２ａ
は導波路コア層、２ｂはバッファ層、２Ｃはクラッド層
である。また、３はレーザ・ガイド、４は半導体レーザ
であり、これは（ｂ）に示すように基板４ａ上にエピタ
キシャル成長層４ｂが形成された構造になっている。５
は活性層である。Figures S (a) to (C) show a method of combining a semiconductor laser and an optical waveguide in this case. In the figure, 1 is a Si substrate, la is the substrate surface, 2 is a quartz optical waveguide, 2a
is a waveguide core layer, 2b is a buffer layer, and 2C is a cladding layer. Further, 3 is a laser guide, and 4 is a semiconductor laser, which has a structure in which an epitaxial growth layer 4b is formed on a substrate 4a, as shown in (b). 5
is the active layer.

また６は給電用金ワイヤ、７は導電膜である。Further, 6 is a gold wire for power feeding, and 7 is a conductive film.

半導体レーザ４の活性層５と基板裏面４０間の距離！、
と、導波路コア層２ａの中心とＳｉ基板１の表面ｌａ間
の距１ｈとは、１１＝ノ、のように設定する。したがっ
て、半導体レーザ４をＳｉ基板上に塔載することにより
、レーザ導波路間の位置合せができる。現在、ｌ、の寸
法設定は、基板４ａを所望の厚さに研磨することにより
行ない、！、の寸法表定は、石英系光導波路のバッフ７
層２ｂの厚さを制御することにより行なっている。Distance between active layer 5 of semiconductor laser 4 and substrate back surface 40! ,
The distance 1h between the center of the waveguide core layer 2a and the surface la of the Si substrate 1 is set as follows. Therefore, by mounting the semiconductor laser 4 on the Si substrate, alignment between the laser waveguides can be achieved. Currently, the dimensions of l are set by polishing the substrate 4a to the desired thickness, and! The dimensions of , are for the buffer 7 of the silica optical waveguide.
This is done by controlling the thickness of layer 2b.

これにより、Ｃ＝ｌｔ　±２μ講程度の精度で寸法合わ
せができるので、多モード光導波回路への適用は十分可
能である。なお、半導体レーザ４の電気配線については
活性層（ＩＩＩ（ｐサイド）は、金ワイヤ６によって行
ない、基板側（ｎサイプ）は、導ＩＩＥ膜６ａを介して
Ｓｊ基板側より行なっている。As a result, the dimensions can be adjusted with an accuracy of about C=lt ±2 μm, so it is fully applicable to multimode optical waveguide circuits. It should be noted that electrical wiring of the semiconductor laser 4 is performed on the active layer (III (p-side)) using a gold wire 6, and on the substrate side (n-sipe) from the Sj substrate side via a conductive IIE film 6a.

このようにすれば、腹数個のレーザが並列になったレー
ザ・アレイを塔載しても、ｐサイドは各素子毎に独立し
て配線でざるので１１Ｌ％配線が可能である。In this way, even if a laser array with several lasers arranged in parallel is mounted, 11L% wiring is possible because the p-side is not wired independently for each element.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、単一モード糸光導波回路と光半導体素子との
光結合を行なう場合、両者の位置合せ精度は±０．５μ
票以内とする必要があり、上記手段では、この精度は実
現できない。By the way, when performing optical coupling between a single mode fiber optical waveguide circuit and an optical semiconductor element, the alignment accuracy between the two is ±0.5μ.
It needs to be within a vote, and the above method cannot achieve this accuracy.

位置合せ精度の向上をはかる手段としては半導体レーザ
４の活性層側上面（ｐサイド）４ｄを下向きにして８１
基板１上に塔載し、この面４ｄと活性層５との距離１ｏ
が、光導波回路側の距離＾と等しくなるようにすること
が考えられる。この場合、距離ノ。の制御は、エピタキ
シャル成長層４ｂの厚さをａＩ＃することにより実現で
き、しかもエピタキシャル成長層４ｂの厚さは、０．１
μｍの精度での設定が可能である。したがって、半導体
レーザ４の活性層側上面４ｄを基準とすることにより、
大幅な位置決め精度の向上が期待できる。As a means of improving alignment accuracy, the upper surface (p side) 4d of the semiconductor laser 4 on the active layer side is facing downward 81.
mounted on the substrate 1, and the distance between this surface 4d and the active layer 5 is 1o.
It is conceivable to make it equal to the distance ^ on the optical waveguide circuit side. In this case, the distance. can be controlled by setting the thickness of the epitaxial growth layer 4b to aI#, and the thickness of the epitaxial growth layer 4b is 0.1
Settings can be made with an accuracy of μm. Therefore, by using the upper surface 4d of the semiconductor laser 4 on the active layer side as a reference,
A significant improvement in positioning accuracy can be expected.

しかしながらこの場合には、レーザーアレイを塔載する
際ガイド３及び導波路３を形成した後の数１０ｐＩ１１
の段差のある基板表面に、各素子のｐサイドの゛電気配
線バタンを形成することが困難であることから、各素子
毎の電気的絶縁が弁溝に難しいという問題があった。However, in this case, when mounting the laser array, after forming the guide 3 and waveguide 3,
Since it is difficult to form an electrical wiring button on the p-side of each element on a substrate surface with a step difference, there is a problem in that it is difficult to electrically insulate each element in the valve groove.

このように従来技術では、同一基板上での光導波回路と
光半導体素子との複合一体化にあたり、光導波回路と光
半導体素子との精密位置合せ、特にアレイ化した光半導
体素子において、各素子間の′電気的絶縁を保ったまま
での精密位置合せが困難であるという問題点があったが
、本発明の目的は、このような素子間絶縁と精密位置合
せの問題を解決したハイブリッド光導波回路を提供する
ことにある。In this way, in the conventional technology, when integrating an optical waveguide circuit and an optical semiconductor element on the same substrate, precision alignment of the optical waveguide circuit and optical semiconductor element, especially in an arrayed optical semiconductor element, is required. However, the purpose of the present invention is to develop a hybrid optical waveguide that solves these problems of inter-element insulation and precise alignment. The purpose is to provide circuits.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、光導波回路と光半導体素子とのハイブリッド
集積化にあたり、単一モード系光導波回路に適用できる
位置決め精度を実現するため、およびアレイ化した光半
導体素子を配設する場合各素子間の電気的絶縁を保つた
めに１光牛導体素子を活性層側上面を下（ｐサイド・ダ
ウン）にして基板上に突出させた保持台に塔載するよう
にしている。The present invention aims to achieve positioning accuracy applicable to single-mode optical waveguide circuits in hybrid integration of optical waveguide circuits and optical semiconductor devices, and to improve positioning accuracy between each element when arrayed optical semiconductor devices are arranged. In order to maintain electrical insulation of the substrate, one optical conductor element is mounted on a holder protruding above the substrate with the upper surface facing the active layer facing down (p side down).

〔実施例〕〔Example〕

第１図及びｗ、、２図は本発明の′ｗＪ、１実施例であ
り、光導波回路と、半導体レーザ・アレイをハイブリッ
ド集権化したものである。Figures 1 and 2 show an embodiment of the present invention, which is a hybrid centralization of an optical waveguide circuit and a semiconductor laser array.

第１図（ａ）は光導波回路側イブリッド集積部分の構造
を示したもので、図中符号１はＳｉ基板、２は石英系光
導波路、２ｂはバッファ層である。また、７は光半導体
素子保持台、８は光導波路２と同軸上に光導波路２から
離間して設けられた電気配線台、６ａは導電膜である。FIG. 1(a) shows the structure of the hybrid integrated portion on the optical waveguide circuit side, in which reference numeral 1 is a Si substrate, 2 is a quartz optical waveguide, and 2b is a buffer layer. Further, 7 is an optical semiconductor element holding stand, 8 is an electric wiring stand provided coaxially with the optical waveguide 2 and spaced apart from the optical waveguide 2, and 6a is a conductive film.

この回路において、バッファ層２ｂの上面高さ１１、は
素子保持台７の上面間さｌＩ！と等しくなっている。こ
れは、バッファＩｔｉｊ２ｂと保持台７とが同一条件下
でのエラチン・グにより得られる関係上、必然的に成る
ものである。また、導波路コア層２ａ中心と素子保持台
７の上面間の距離１　ｔｓは、後述する半導体レーザ４
の活性層５側端面と活性層５間の距Ｍｌｊ　Ａ！　＋４
に略等しくなるよう設定しである。In this circuit, the top surface height 11 of the buffer layer 2b is the distance between the top surfaces of the element holding table 7 lI! is equal to This is inevitable because the buffer Itij2b and the holding table 7 are obtained by erasing under the same conditions. Further, the distance 1 ts between the center of the waveguide core layer 2a and the upper surface of the element holding table 7 is the distance 1ts between the center of the waveguide core layer 2a and the upper surface of the element holding table 7
The distance Mlj A! between the side end surface of the active layer 5 and the active layer 5 +4
It is set to be approximately equal to .

このように、多段の段差を有する石英系光導波路を得る
には、例えば、コ櫨類の異なる材質からなるマスク材を
用いて、第一層目に第１のマスク材をバッファＭ２ｂ１
素子保持台７及び１上％配殊台８の形状にバタン化し、
その上に％２のマスク材を導波路２の形状にバタン化し
積載した後に、−ｉのドライエツチングにより石英系光
導波膜の不要部分を除去するといった方法（段差付エツ
チング法・％願昭６０−２０５０１２　）がある。In this way, in order to obtain a quartz-based optical waveguide having multiple steps, for example, using mask materials made of different materials such as oak, the first mask material is added to the buffer M2b1 in the first layer.
It is slammed into the shape of the element holding table 7 and the 1% arrangement table 8,
After stacking a mask material of %2 in the shape of the waveguide 2 on top of it, unnecessary parts of the silica-based optical waveguide film are removed by dry etching of -i (stepped etching method, patented in 1983). -205012).

第１図（ｂ）は半導体レーザ・アレイ部の１？＃１造を
示したものであり、４は半導体レーザ・アレイ、５は前
記導波路コア層２ａに合わせて所定間隔置に配設された
活性層、９はヒートシンク、１０は上ｓ電極である。上
記半導体レーザ・アレイ４の各活性層５間は素子間分離
溝１１でｍ気的に絶縁されている。Figure 1(b) shows the semiconductor laser array section 1? #1 structure, 4 is a semiconductor laser array, 5 is an active layer arranged at predetermined intervals in accordance with the waveguide core layer 2a, 9 is a heat sink, and 10 is an upper S electrode. . The active layers 5 of the semiconductor laser array 4 are electrically insulated by element isolation grooves 11.

第２図は、半導体レーザ・アレイ４を石英系光導波回路
上に塔載した図である。半導体レーザ・アレイ４の活性
Ｎ０１ｌｌ端面（ｐサイド）が素子保持台７の上面に接
するように、ｐサイド・ダウン状態にレーザ・アレイ４
を塔載した。保持台７上へのレーザ・アレイの固定は接
着剤によっても、また、半田等によってもよい。電気配
線については、上部電極１０と電気配線台８上の導′Ｗ
Ｌ膜６ａとの間を金ｆｆＭ６で接続することにより、ｐ
サイドの配線を行ない、上部電極は各素子とも共通電極
として、ヒートシンク９側より取り出す。FIG. 2 is a diagram in which the semiconductor laser array 4 is mounted on a silica-based optical waveguide circuit. The laser array 4 is placed in a p-side down state so that the active N01ll end face (p-side) of the semiconductor laser array 4 is in contact with the upper surface of the element holding table 7.
was published. The laser array may be fixed onto the holding table 7 by adhesive, solder, or the like. For electrical wiring, connect the upper electrode 10 and the conductor W on the electrical wiring stand 8.
By connecting between the L film 6a and the gold ffM6, p
Side wiring is performed, and the upper electrode is taken out from the heat sink 9 side as a common electrode for each element.

このように、本実施例では、光回路基板に多段の段差を
つけて素子保持台７を凸状としているので、半導体レー
ザと光導波回路なハイブリッド集権化するにあたり、位
置決め精度の高いｐサイド・ダウンでこの素子装着が行
なえると同時に、アレイ化した素子においても、基板上
に電気配線パターンを形成することな（、半導体レーザ
４の下側の空間を利用し金線６により電気的接続を行な
っているため、各素子間の！気的絶縁を保ったままでの
電気配置？１Ｍが可能となるというメリットがある。さ
らに、本実施例においては、保持台上への素子固定に先
立って、元導体素子の寛気配−を完了することができ１
．このためレーザ・アレイを発光させながら、光導波回
路との位置合せを行なうことが可能となり、極めて高い
位置決め積属を実現できるという効果も得られる。As described above, in this embodiment, since the optical circuit board has multiple steps and the element holding table 7 is made convex, it is possible to use the p-side and high-positioning precision for hybrid centralization of semiconductor lasers and optical waveguide circuits. At the same time, it is possible to mount this element down, and at the same time, even in an arrayed element, there is no need to form an electrical wiring pattern on the substrate. This has the advantage of enabling an electrical arrangement of 1M while maintaining gaseous insulation between each element.Furthermore, in this embodiment, prior to fixing the elements on the holding table, The relaxation of the original conductor element can be completed 1
．． Therefore, it is possible to perform alignment with the optical waveguide circuit while emitting light from the laser array, and it is also possible to achieve the effect of realizing extremely high positioning accuracy.

第３図は不発明の第２実施例である。同図において１は
８４基板、２は左右（図中Ｘ方向）に所定間隔をあげて
同軸上に配された複数列の石英系光導波路、２１はそれ
ら複数列の光導波路２の下側に一体に形成された光半導
体素子保持台、８は１１Ｅ気配線台、６ａは導電膜、５
は金線、２２は保持台２１上に光導波路２１Ｃ隣接して
設けられた素子間分離溝である。この実施例は光をしゃ
断または透過するための元ゲートスイッチのゲート装着
部であり、導波路２の間に第１図で示すものと全（同様
の構造をした半導体ゲートスイッチをｐサイド・ダウン
状態で装着するようになっている。FIG. 3 shows a second embodiment of the invention. In the figure, 1 is an 84 substrate, 2 is a plurality of rows of quartz-based optical waveguides arranged coaxially at a predetermined interval on the left and right (in the X direction in the figure), and 21 is the lower side of the multiple rows of optical waveguides 2. An optical semiconductor element holding stand integrally formed, 8 is an 11E wiring stand, 6a is a conductive film, 5
2 is a gold wire, and 22 is an inter-element isolation groove provided on the holding table 21 adjacent to the optical waveguide 21C. This embodiment is a gate mounting part of a former gate switch for blocking or transmitting light, and a semiconductor gate switch having a similar structure (a semiconductor gate switch having a similar structure to that shown in FIG. It is designed to be installed in the same condition.

この実施例においては、導波路２のコア層の中心部と素
子保持台２１の上面、すなわち導電膜６ａとの間の距離
Ａｌｌが、第１図で示す構造をした半導体ゲートスイッ
チにおける活性層側上面と活性層間の距離に等しくなる
ように設定しである。したがって、半導体ゲートスイッ
チなｐサイド・ダウンで素子保持台２１上に装着するこ
とにより、光導波路２及び活性層５の高さ方向の精密位
置合せが実現できる。また、横方向（図中Ｙ方向ンの位
置合せは、光導波路２と半導体ゲートスイッナの上部電
極とを合せることにより実現する。半導体ゲートスイッ
チ２３は熱圧着等を用いて、素子支持台２１上に固定さ
れ、このとぎ同時に、ｐすイドの電極と導ｉｔ膜６ａと
が電気的に接続される。In this embodiment, the distance All between the center of the core layer of the waveguide 2 and the upper surface of the element holding table 21, that is, the conductive film 6a, is on the active layer side of the semiconductor gate switch having the structure shown in FIG. The distance is set to be equal to the distance between the top surface and the active layer. Therefore, by mounting the semiconductor gate switch p-side down on the element holder 21, precise alignment of the optical waveguide 2 and the active layer 5 in the height direction can be realized. In addition, alignment in the lateral direction (in the Y direction in the figure) is achieved by aligning the optical waveguide 2 and the upper electrode of the semiconductor gate switcher. At the same time, the p-side electrode and the conductive IT film 6a are electrically connected.

第ダ図に、半導体光ゲート２３を光導波回路上に装着し
た時の斜視図を示す。この際素子支持台２１には、素子
間分離溝２２が形成されているので、半導体ゲート・ア
レイの各素子苺に、導伝膜６ａはｍ動的に絶縁される５
こととなる。FIG. 3 shows a perspective view of the semiconductor optical gate 23 mounted on the optical waveguide circuit. At this time, since an inter-element isolation groove 22 is formed in the element support 21, the conductive film 6a is dynamically insulated from each element of the semiconductor gate array.
That will happen.

以上述べたように、本実施例においては、導電膜６ａを
形成した素子保持台２１上に１凹状の素子間分離溝２２
を設け、光導波路２とこの素子量分ｌｌ！Ｉ溝２２とに
より、′４屯膜６ａ間の電気的絶縁を行なうようにした
ので、光導波回路２と光半導体素子２３とｋ　ハイブリ
ッド集積化するにあたり、アレイ化した光半導体素子２
３をｐサイド・ダウンで装着でき、かつ各素子間の！気
的絶縁ができるという効果がある。As described above, in this embodiment, one concave element isolation groove 22 is formed on the element holding table 21 on which the conductive film 6a is formed.
, and the optical waveguide 2 and the amount of this element ll! Since the I-groove 22 provides electrical insulation between the four-layer film 6a, the optical waveguide circuit 2 and the optical semiconductor element 23 are connected to each other.
3 can be installed p-side down, and between each element! It has the effect of providing electrical insulation.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明では、ハイブリッド光導波
回路において、基板上に光導波回路部と素子保持部とを
光導波回路部が素子保持部よりも高くなるように双方突
出させて設けたので、極めて高い位置決め精度が得られ
るｐサイド・ダウンでの素子装着を行ない、かつ、アレ
イ状の光半導体素子の場合であっても、各素子間の′ａ
電気的絶縁とることができるという利点がある。As explained above, in the present invention, in the hybrid optical waveguide circuit, the optical waveguide circuit part and the element holding part are provided on the substrate so that both protrude so that the optical waveguide circuit part is higher than the element holding part. , the elements are mounted p-side down, which provides extremely high positioning accuracy, and even in the case of arrayed optical semiconductor elements, the 'a' between each element is
It has the advantage of providing electrical insulation.

本発明は、光半導体素子と導波路の精密位置合せが容易
なことから特に、元ゲートスイッチ等の単一モード系の
ハイブリッド光導波回路への応用に有効である。The present invention is particularly effective in application to single-mode hybrid optical waveguide circuits such as original gate switches because precise alignment of the optical semiconductor element and the waveguide is easy.

【図面の簡単な説明】[Brief explanation of drawings]

第１［３１は本発明の第１の実袖例の（ａ）光導波回路
部分の斜視図、（ｂ）光半導体素子の斜視図である。 第２図はＭ／図の光導波回路と光半導体素子とをハイブ
リッド集棟化した光回路の斜視図、！ｉｇ３図は本発明
の第２実施例の光導波回路の斜視図、第ｌＩ図は第３図
の光導波回路に元ゲート素子を装着した状態の斜視図、
第５図はｐサイド・アップで半導体素子を装着する従来
提案されているハイブリッド光導波回路の説明図である
。 １・・・・・・Ｓｉ基板、２・・・・・・石英系光導波
路、２ｂ・・・・・・バッファ層、４・・・・・・半導
体レーザ・アレイ、５パ・・・・活性層、６・・・・・
・金線、６ａ・・・・・・導電膜、７・・・・・・素子
保持台、１０・・・・・・上部電極、１１・・・・・・
溝、２１・・・・・・素子保持台、２２・川・・溝、２
３・・・・・・半導体ゲートスイッチ。No. 1 [31] is (a) a perspective view of an optical waveguide circuit portion and (b) a perspective view of an optical semiconductor element of the first practical example of the present invention. Figure 2 is a perspective view of an optical circuit in which the optical waveguide circuit shown in Figure M/ and the optical semiconductor element are integrated into a hybrid structure. Fig. ig3 is a perspective view of the optical waveguide circuit according to the second embodiment of the present invention, and Fig. lI is a perspective view of the optical waveguide circuit of Fig. 3 with the original gate element attached.
FIG. 5 is an explanatory diagram of a conventionally proposed hybrid optical waveguide circuit in which a semiconductor element is mounted with the p side up. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Silica-based optical waveguide, 2b... Buffer layer, 4... Semiconductor laser array, 5... Active layer, 6...
・Gold wire, 6a... Conductive film, 7... Element holding stand, 10... Upper electrode, 11...
Groove, 21... Element holding stand, 22 River... Groove, 2
3...Semiconductor gate switch.

Claims (2)

【特許請求の範囲】[Claims] （１）基板上に光導波回路部と素子保持部とを、光導波
回路部が素子保持部よりも高くなるよう双方突出させて
設け、かつ、素子保持部の上面と光導波回路部のコア層
の中心部の高さの差を、塔載すべき光半導体素子の活性
層側の端面と活性層との高さの差に等しくなるように設
定し、光半導体素子の活性層側の端面を素子保持部の上
面に接触させて、光導波回路部のコア層の中心と光半導
体素子の活性層とが一致するよう光半導体素子を保持し
ていることを特徴とするハイブリッド光導波回路。(1) An optical waveguide circuit section and an element holding section are provided on a substrate so that both protrude so that the optical waveguide circuit section is higher than the element holding section, and the upper surface of the element holding section and the core of the optical waveguide circuit section are provided. The height difference between the centers of the layers is set to be equal to the height difference between the active layer side end face of the optical semiconductor element to be mounted and the active layer, and the height difference between the active layer side end face of the optical semiconductor element A hybrid optical waveguide circuit, characterized in that the optical semiconductor element is held in contact with the upper surface of the element holding part so that the center of the core layer of the optical waveguide circuit part and the active layer of the optical semiconductor element coincide. （２）基板上に光導波回路部と素子保持部とを、光導波
回路部が素子保持部よりも高くなるよう双方突出させて
設け、かつ、素子保持部の上面と光導波回路部のコア層
の中心部の高さの差を、塔載すべき光半導体素子の活性
層側の端面と活性層との高さの差に等しくなるように設
定し、素子保持部上面に所望形状の溝を形成するととも
に同上面に導電膜を形成し、光半導体素子の活性層側の
端面を素子保持台上の導電膜に機械的かつ電気的に接触
させて、光導波回路部のコア層の中心と光半導体素子の
活性層とが一致するよう光半導体素子を保持しているこ
とを特徴とするハイブリッド光導波回路。(2) An optical waveguide circuit section and an element holding section are provided on the substrate so that both protrude so that the optical waveguide circuit section is higher than the element holding section, and the upper surface of the element holding section and the core of the optical waveguide circuit section are provided. The height difference between the centers of the layers is set to be equal to the height difference between the active layer and the end surface of the optical semiconductor element to be mounted on the active layer side, and a groove of a desired shape is formed on the upper surface of the element holding part. At the same time, a conductive film is formed on the same upper surface, and the end face of the optical semiconductor element on the active layer side is brought into mechanical and electrical contact with the conductive film on the element holding table, and the center of the core layer of the optical waveguide circuit section is 1. A hybrid optical waveguide circuit, wherein an optical semiconductor element is held such that the active layer of the optical semiconductor element and the active layer of the optical semiconductor element are aligned with each other.
JP61085260A 1986-04-14 1986-04-14 Hybrid optical waveguide circuit Expired - Lifetime JPH0654805B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61085260A JPH0654805B2 (en) 1986-04-14 1986-04-14 Hybrid optical waveguide circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61085260A JPH0654805B2 (en) 1986-04-14 1986-04-14 Hybrid optical waveguide circuit

Publications (2)

Publication Number Publication Date
JPS62242362A true JPS62242362A (en) 1987-10-22
JPH0654805B2 JPH0654805B2 (en) 1994-07-20

Family

ID=13853601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61085260A Expired - Lifetime JPH0654805B2 (en) 1986-04-14 1986-04-14 Hybrid optical waveguide circuit

Country Status (1)

Country Link
JP (1) JPH0654805B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638829A1 (en) * 1993-08-09 1995-02-15 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
US6894269B2 (en) 2001-04-30 2005-05-17 Optun (Bvi) Ltd. Configuration for detecting optical signals in at least one optical channel in a planar light circuit, attenuator including the configuration, and method for manufacturing the configuration

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638829A1 (en) * 1993-08-09 1995-02-15 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
US5621837A (en) * 1993-08-09 1997-04-15 Nippon Telegraph & Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit and process for fabricating platform
EP0831349A2 (en) * 1993-08-09 1998-03-25 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module,opto-electronic hybrid integration circuit, and process for fabricating platform
EP0831349A3 (en) * 1993-08-09 1998-04-01 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module,opto-electronic hybrid integration circuit, and process for fabricating platform
US6027254A (en) * 1993-08-09 2000-02-22 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
US6164836A (en) * 1993-08-09 2000-12-26 Yamada; Yasufumi Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
EP1083450A1 (en) * 1993-08-09 2001-03-14 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
EP1089101A1 (en) * 1993-08-09 2001-04-04 Nippon Telegraph And Telephone Corporation Opto-electronic hybrid integration platform, optical sub-module, opto-electronic hybrid integration circuit, and process for fabricating platform
US6894269B2 (en) 2001-04-30 2005-05-17 Optun (Bvi) Ltd. Configuration for detecting optical signals in at least one optical channel in a planar light circuit, attenuator including the configuration, and method for manufacturing the configuration

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