JPS62235726A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62235726A JPS62235726A JP7976686A JP7976686A JPS62235726A JP S62235726 A JPS62235726 A JP S62235726A JP 7976686 A JP7976686 A JP 7976686A JP 7976686 A JP7976686 A JP 7976686A JP S62235726 A JPS62235726 A JP S62235726A
- Authority
- JP
- Japan
- Prior art keywords
- film
- ions
- silicon
- crystallinity
- sos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 28
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 22
- 239000010980 sapphire Substances 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 abstract description 44
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000007790 solid phase Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 125000001153 fluoro group Chemical group F* 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はサファイア基板上にエピタキシャル成長させた
シリコン薄膜の電気的特性を改善する方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for improving the electrical properties of silicon thin films epitaxially grown on sapphire substrates.
従来の技術
従来、サファイア基板上にシリコン薄膜をエピタキシャ
ル成長させたＳＯ８膜はサファイアとシリコンの格子定
数の違いから、シリコン−サファイア界面で格子の不整
合が生じ、このためシリコ２ベーゾ
〜ンーサファイア界面近傍を中心に、シリコン膜中に多
数の欠陥が存在している。このため、これらのＳＯ８膜
上に作製したＭＯ８型トランジスタはバルクシリコン上
に作製したＭＯ８型トランジスタに比ベキャリア移動度
が低く、さらにドレイン漏れ電流が多い等の欠点を持っ
ていた。Conventional technology Conventionally, in SO8 films made by epitaxially growing a silicon thin film on a sapphire substrate, lattice mismatch occurs at the silicon-sapphire interface due to the difference in lattice constant between sapphire and silicon. There are many defects in the silicon film, mainly . For this reason, the MO8 type transistors fabricated on these SO8 films had disadvantages such as lower carrier mobility than MO8 type transistors fabricated on bulk silicon, and also higher drain leakage current.
これらの電気的特性を改善するため従来は第２図ｄ〜第
２図ｑに示すような工程流れ図に従った工程が提案され
ていた。以下第２図ａ〜第２図ｑを参照して従来のＳＯ
８膜の電気的特性の改善法について説明する。In order to improve these electrical characteristics, a process according to process flowcharts as shown in FIGS. 2d to 2q has heretofore been proposed. The conventional SO
A method for improving the electrical characteristics of the 8 film will be explained.
即ち、まず第一に第２図ａに示すようにＳＯ８膜中で結
晶欠陥が高密度に存在しているシリコン−サファイア界
面近傍に第２図すに示すようにＳｉ”イオンを高濃度に
イオン注入し、シリコン−サファイア界面近傍を非晶質
化し非晶質層Ｉ４する。このときＳＯ８膜は液体窒素温
度に保持しておく。続いて、第２図Ｃに示すように前記
ＳＯ８膜を６００℃以上の窒素雰囲気中で熱処理を行な
う。これにより非晶質化された部分に向かって表３ベー
ノ
面から同相成長がおこり、第２図ｄに示すように非晶質
層Ｉ４は単結晶化され、シリコン−サファイア界面近傍
の結晶性が改善され結晶性改善領域■５となる。その結
果ＳＯ８膜のシリコン−サファイア界面近傍の電気的特
性が改善され、本ＳＯ８膜上にＭＯ８型トランジスタを
形成した場合、ドレイン漏れ電流は低減できる。次に第
２図ｅに示すようにＳＯＳ膜の表面近傍の電気的特性改
善のためＳｉ＋イオンをＳＯ８膜表面付近６に高濃度に
イオン注入し、６００℃以上の窒素雰囲気中で熱処理を
行なう。これにより第２図ｆに示すように今度はＳＯ８
膜中から表面に向かって固相成長が起シ第２図９に示す
ように表面付近の結晶性が改善され、結晶性改善領域■
となる。その結果ＳＯ８膜表面近傍の電気的特性が改善
され、本ＳＯ８膜上にＭＯ８型トランジスタを形成した
場合、移動度が改善される。That is, first of all, as shown in Fig. 2a, Si'' ions are ionized at a high concentration near the silicon-sapphire interface where crystal defects exist at a high density in the SO8 film, as shown in Fig. 2a. The SO8 film is implanted to amorphize the vicinity of the silicon-sapphire interface to form an amorphous layer I4.At this time, the SO8 film is kept at liquid nitrogen temperature.Subsequently, as shown in FIG. Heat treatment is performed in a nitrogen atmosphere at a temperature higher than ℃.As a result, in-phase growth occurs from the Beno plane in Table 3 toward the amorphous portion, and the amorphous layer I4 becomes a single crystal as shown in Figure 2d. As a result, the crystallinity near the silicon-sapphire interface is improved, resulting in an improved crystallinity region 5. As a result, the electrical characteristics near the silicon-sapphire interface of the SO8 film are improved, and an MO8 type transistor is formed on this SO8 film. In this case, the drain leakage current can be reduced.Next, as shown in Fig. 2e, in order to improve the electrical characteristics near the surface of the SOS film, Si+ ions were implanted at a high concentration near the surface of the SO8 film 6, and the temperature was increased to 600°C. Heat treatment is performed in the above nitrogen atmosphere.As a result, as shown in Fig. 2 f, SO8
Solid-phase growth occurs from the inside of the film toward the surface, and as shown in Figure 2, the crystallinity near the surface is improved, resulting in a crystallinity-improved region.
becomes. As a result, the electrical characteristics near the surface of the SO8 film are improved, and when an MO8 type transistor is formed on this SO8 film, the mobility is improved.
発明が解決しようとする問題点
このような従来の方法は主にＳＯ８膜を非晶質化し、同
相成長の効果により結晶性を改善し、その結果、ＳＯ８
膜の電気的特性を改善するものであり、固相成長により
ＳＯ８膜の結晶性を改善した後も、シリコン−サファイ
ア界面や膜中には数多くのシリコン原子の未結合手が残
されている。Problems to be Solved by the Invention These conventional methods mainly make the SO8 film amorphous and improve its crystallinity through the effect of in-phase growth.
This method improves the electrical properties of the film, and even after improving the crystallinity of the SO8 film by solid-phase growth, many dangling bonds of silicon atoms remain at the silicon-sapphire interface and in the film.
従来のＳｔ”イオンを用いたイオン注入ではシリコン原
子が４価であることから、膜中のシリコン未結合手を電
気的に不活性にすることができず、ＳＯ８膜中にはまだ
結晶欠陥が数多く残されていた。さらにＳｉ＋イオンの
質量数が２８であることからイオン注入時に窒素による
汚染の問題がある。In conventional ion implantation using St'' ions, silicon atoms are tetravalent, so it is not possible to make silicon dangling bonds in the film electrically inactive, and crystal defects still exist in the SO8 film. Further, since the mass number of Si+ ions is 28, there is a problem of contamination by nitrogen during ion implantation.
本発明はこれらの問題を解決するもので他イオンの汚染
なしにイオン注入が行なえ、ＳＯ８膜中のシリコン未結
合手を電気的に不活性化し、ＳＯ８膜の電気的特性を効
果的に改善することを目的とする。The present invention solves these problems by performing ion implantation without contaminating other ions, electrically inactivating silicon dangling bonds in the SO8 film, and effectively improving the electrical characteristics of the SO8 film. The purpose is to
問題点を解決するための手段
前記問題点を解決するため本発明はサファイア基板上に
エピタキシャル成長させた一導電型のシリコン薄膜にＳ
ｉＦ＋イオン又はＳｉＨ＋イオンを２×１０ ｃｒｎ
以上の高濃度にイオン注入し、６ページ
其の後７００℃から９００℃の温度範囲で熱処理を行な
うことを特徴とする半導体装置の製造方法を提供する。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a silicon thin film of one conductivity type epitaxially grown on a sapphire substrate.
iF+ ions or SiH+ ions at 2×10 crn
Provided is a method for manufacturing a semiconductor device, characterized in that ions are implanted at a high concentration as described above, and then heat treatment is performed in a temperature range of 700° C. to 900° C. after 6 pages.
作 用
ＳｉＦ＋イオン又はＳｉＨ＋イオンをイオン注入の注入
イオンとして用いることにより、ＳｉＦ＋イオン又はＳ
ｉＨ＋イオンによるＳＯ８膜の非晶質化による通常の固
相成長の結晶性改善の効果に加え、弗素原子又は水素原
子がシリコン−サファイア界面及びＳＯ８膜中に存在す
る。Function By using SiF+ ions or SiH+ ions as implantation ions, SiF+ ions or S
In addition to the effect of improving the crystallinity of normal solid phase growth due to the amorphization of the SO8 film by iH+ ions, fluorine atoms or hydrogen atoms are present at the silicon-sapphire interface and in the SO8 film.
実施例
以下、本発明の一実施例を第１図ａ〜第１図ｑの工程流
れ図を参照して説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to process flowcharts shown in FIGS. 1a to 1q.
まず、第１図ａに示すようなシリコン膜厚０．６μｍの
ＳＯ８基板に第１図すに示すようにＳｉＦ”イオンをド
ーズ量５ Ｘ １０” ｃｍ−２の濃度でシリコン表面
から０．６５μｍ付近にイオン飛程の中心がくるような
加速エネルギーでイオン注入を行なう。First, SiF" ions were applied to an SO8 substrate with a silicon film thickness of 0.6 μm as shown in FIG. Ion implantation is performed with acceleration energy such that the center of the ion range is located nearby.
これによシシリコンーサファイア界面近傍には非晶質層
Ｉ４が形成される。このときイオン注入に６ページ
用いるガスはＳ Ｉ Ｆ４ガスを用い、注入中ＳＯ８膜
は注入による温度上昇を防ぐ目的と非晶質化を効果的に
行なうため液体窒素で冷却する。次に、第１図Ｃに示す
ようにこのＳＯ８膜を７００℃の窒素雰囲気中で６ｏ分
間熱処理する。これにより非晶質層に固相成長がおこり
単結晶化されると同時に弗素原子がシリコン−サファイ
ア界面に存在するシリコンの未結合手を電気的に不活性
化する。As a result, an amorphous layer I4 is formed near the silicon-sapphire interface. At this time, the gas used for ion implantation is SIF4 gas, and during the implantation, the SO8 film is cooled with liquid nitrogen in order to prevent a temperature rise due to the implantation and to effectively make it amorphous. Next, as shown in FIG. 1C, this SO8 film is heat-treated for 60 minutes in a nitrogen atmosphere at 700°C. As a result, solid-phase growth occurs in the amorphous layer to form a single crystal, and at the same time, fluorine atoms electrically inactivate the dangling bonds of silicon present at the silicon-sapphire interface.
また熱処理中に過剰な弗素原子はＳＯ８膜表面に向かっ
て拡散しその時ＳＯ８膜中に存在する未結合手を電気的
に不活性化する。これらの工程により第１図ｄに示すよ
うにＳＯ８膜のシリコン−サファイア界面近傍の結晶性
が改善され、結晶性改善領域Ｉ５となる。Further, during the heat treatment, excessive fluorine atoms diffuse toward the surface of the SO8 film, and at that time, the dangling bonds present in the SO8 film are electrically inactivated. Through these steps, the crystallinity near the silicon-sapphire interface of the SO8 film is improved, forming a crystallinity-improved region I5, as shown in FIG. 1d.
続いて、第１図ｅに示すようにＳＯ８膜の表面から０．
１μｍ付近にイオンの飛程の中心がくるような加速エネ
ルギーでＳｉＦ＋イオンヲ５×１ｏ１５ｔＭ”−２のド
ーズ量でイオン注入する。これによシ第１図ｆに示すよ
うにＳＯＳ膜の表面近傍に非晶質層■６が形成される。Subsequently, as shown in FIG. 1e, 0.0.
SiF+ ions are implanted at a dose of 5×1o15tM''-2 using acceleration energy such that the center of the ion range is around 1 μm.This allows the SiF+ ions to be implanted near the surface of the SOS film as shown in Figure 1f. An amorphous layer (6) is formed.
次いで、第１図ｑに示す７ベーノ
ようにこのＳＯ８膜に７００℃の窒素雰囲気中で熱処理
を施こすことによりＳＯ８膜中から表面に向かって固相
成長がおこり表面付近の結晶性が改善され、結晶性改善
領域■７となる。以上の処理によｐｓｏｓ膜のシリコン
−サファイア界面近傍シリコン薄膜中、シリコン表面の
全領域にわたって結晶性が改善される。なお、本実施例
ではＳｉＦ＋イオンを例に説明したが、ＳｉＨ＋イオン
でも同様の効果が期待できる。またＳｉＦ＋イオンを用
いる場合はその質量数が４７であることから窒素汚染の
問題が生じない。Next, as shown in Figure 1q, by heat-treating this SO8 film in a nitrogen atmosphere at 700°C, solid-phase growth occurs from within the SO8 film toward the surface, improving the crystallinity near the surface. , crystallinity improved region (7). The above treatment improves the crystallinity over the entire region of the silicon surface in the silicon thin film near the silicon-sapphire interface of the psos film. Although this embodiment has been described using SiF+ ions as an example, similar effects can be expected with SiH+ ions. Further, when SiF+ ions are used, since their mass number is 47, the problem of nitrogen contamination does not occur.
発明の効果
以上のように本発明によればＳＯ８膜のシリコン−サフ
ァイア界面と、シリコン薄膜中、シリコン表面の全領域
にわたって結晶性を効果的に改善することが可能であシ
、これによυ本りＯ８膜上に形成したｈｖｉ ＯＳ型ト
ランジスタのドレイン漏れ電流は低減化され、実効移動
度は増大するためＳｏＳ膜上に作製したＭＯＳ型集積回
路を高性能化することが可能である。Effects of the Invention As described above, according to the present invention, it is possible to effectively improve the crystallinity at the silicon-sapphire interface of the SO8 film and over the entire silicon surface area in the silicon thin film. Since the drain leakage current of the HVI OS type transistor formed on the O8 film is reduced and the effective mobility is increased, it is possible to improve the performance of the MOS type integrated circuit formed on the SoS film.
第１図は本発明の実施例による半導体装置の製造方法を
示す工程断面図、第２図は従来の半導体装置の製造方法
を示す工程断面図である。
１・・・・・・サファイア基板、２・・・・・・シリコ
ンエピタキシャル層、３・・・・・・シリコン−サファ
イア界面、４・・・・・・ＳｉＦ＋イオン注入による非
晶質層１．５・・・・・・固相成長による結晶性改善領
域Ｉ、６・・・・・・ＳｉＦ”イオン注入による非晶質
層■、７・・・・・・固相成長による結晶性改善領域■
。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名リ
（）憾
（FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device. 1... Sapphire substrate, 2... Silicon epitaxial layer, 3... Silicon-sapphire interface, 4... Amorphous layer by SiF+ ion implantation. 5... Crystallinity improved region I by solid phase growth, 6... Amorphous layer ■ by SiF" ion implantation, 7... Crystallinity improved region by solid phase growth ■
. Name of agent: Patent attorney Toshio Nakao and one other person
() regret
(
Claims (1)
のシリコン薄膜にＳｉＦ＾＋イオン又はＳｉＨ＾＋イオ
ンを２×１０＾１＾５ｃｍ＾−＾２以上の高濃度にイオ
ン注入し、其の後７００℃から９００℃の温度範囲で熱
処理を行なうことを特徴とする半導体装置の製造方法。SiF^+ ions or SiH^+ ions are implanted at a high concentration of 2 x 10^1^5 cm^-^2 or more into a silicon thin film of one conductivity type epitaxially grown on a sapphire substrate, and then at 700°C. A method for manufacturing a semiconductor device, characterized in that heat treatment is performed in a temperature range of 900°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7976686A JPS62235726A (en) | 1986-04-07 | 1986-04-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7976686A JPS62235726A (en) | 1986-04-07 | 1986-04-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62235726A true JPS62235726A (en) | 1987-10-15 |
| JPH0533527B2 JPH0533527B2 (en) | 1993-05-19 |
Family
ID=13699333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7976686A Granted JPS62235726A (en) | 1986-04-07 | 1986-04-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62235726A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0752719A1 (en) * | 1995-07-07 | 1997-01-08 | Plessey Semiconductors Limited | Method of manufacturing a silicon on sapphire integrated circuit arrangement |
| US6090648A (en) * | 1993-07-12 | 2000-07-18 | Peregrine Semiconductor Corp. | Method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| JP2012506132A (en) * | 2008-10-02 | 2012-03-08 | ヴァリアン セミコンダクター イクイップメント アソシエイツ インコーポレイテッド | Temperature control method for embedding process |
-
1986
- 1986-04-07 JP JP7976686A patent/JPS62235726A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6090648A (en) * | 1993-07-12 | 2000-07-18 | Peregrine Semiconductor Corp. | Method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| EP0752719A1 (en) * | 1995-07-07 | 1997-01-08 | Plessey Semiconductors Limited | Method of manufacturing a silicon on sapphire integrated circuit arrangement |
| JP2012506132A (en) * | 2008-10-02 | 2012-03-08 | ヴァリアン セミコンダクター イクイップメント アソシエイツ インコーポレイテッド | Temperature control method for embedding process |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533527B2 (en) | 1993-05-19 |
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