JPS62221168A - Photodiode - Google Patents
PhotodiodeInfo
- Publication number
- JPS62221168A JPS62221168A JP61064064A JP6406486A JPS62221168A JP S62221168 A JPS62221168 A JP S62221168A JP 61064064 A JP61064064 A JP 61064064A JP 6406486 A JP6406486 A JP 6406486A JP S62221168 A JPS62221168 A JP S62221168A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ingaasp
- buffer layer
- junction
- inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000031700 light absorption Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 3
- 240000002329 Inga feuillei Species 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 16
- 238000009825 accumulation Methods 0.000 abstract description 5
- 125000005842 heteroatom Chemical group 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052793 cadmium Inorganic materials 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000003708 ampul Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は長波長光通信に用いられるホトダイオードに係
り、特に高速応答を可能にするＰＩＮホトダイオードの
構造を提供する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photodiode used in long wavelength optical communication, and particularly provides a PIN photodiode structure that enables high-speed response.
従来の１．６μｍｔｆｔに受信可能なホトダイオードの
構造は、 １９８５年のレーザ研究１３巻の１１７ペー
ジにおいて三角らが示しているようにＩｎＧａＡｓ光吸
収層内にｐｎ接合を形成することにより、ＩｎＰウィン
ドウ層とＩｎＧａＡｓ光吸収層のへテロ界面で生じる正
孔の蓄積効果による応答速度の劣化を防いできた（第３
図）、なお、第３図において、１はｎ ＋ −ＩｎＰ基
板、２はｎ″″−ＩｎＰ層、３はｎ−−ＩｎＧａＡｓ光
吸収層、４はｎ″″−ＩｎＰウィンドウ層、５はＺｎま
たはＣｄ拡散層、６はＳｉＮｘパッシベーション膜、７
はｐ形電極、８はｎ形電極をそれぞれ示す。The structure of a conventional photodiode capable of receiving 1.6 μm TFT was achieved by forming a pn junction in an InGaAs light absorbing layer, as shown by Misumi et al. in Laser Research Vol. 13, page 117 in 1985. This has prevented the response speed from deteriorating due to the hole accumulation effect generated at the hetero interface between the InGaAs light absorption layer and the InGaAs light absorption layer.
In FIG. 3, 1 is an n + -InP substrate, 2 is an n""-InP layer, 3 is an n--InGaAs light absorption layer, 4 is an n""-InP window layer, and 5 is a Zn or Cd diffusion layer, 6 is SiNx passivation film, 7
8 indicates a p-type electrode, and 8 indicates an n-type electrode.
しかし、ＩｎＧａＡｓ光吸収層のキャリア濃度が低いた
めに、ｐｎ接合をペテロ界面の近傍に制御することが難
しいという欠点があった。However, since the carrier concentration of the InGaAs light absorption layer is low, there is a drawback that it is difficult to control the pn junction in the vicinity of the Peter interface.
本発明の目的は、上記欠点を克服し、かつ高速応答な可
能なＰＩＮホトダイオードの構造を提供することにある
。SUMMARY OF THE INVENTION The object of the present invention is to overcome the above-mentioned drawbacks and to provide a PIN photodiode structure capable of high-speed response.
上記目的を実現するため１本発明ではＩｎＰウィンドウ
層とＩｎＧａＡｓ光吸収層との間にキャリア濃度が少し
高い（速い拡散が生じないキャリア濃度で。In order to achieve the above object, in the present invention, the carrier concentration is slightly high between the InP window layer and the InGaAs light absorption layer (at a carrier concentration that does not cause rapid diffusion).
一般にＩ Ｘ １０ ｌＢａｍ−”以上） ＩｎＧａＡ
ｓＰバッファ層を設け、たこと及び、バッファ層内にｐ
ｎ接合を形成したことを特徴としている。InGaA
An sP buffer layer is provided, and p is provided in the buffer layer.
It is characterized by the formation of an n-junction.
また、バッファ層の禁止帯幅をウィンドウ層（０，９２
μｍ）と光明収層（１，６７μｍ）の中間（１，２〜１
．４μｍ）として高速化を実現したことも特徴としてい
る。In addition, the forbidden band width of the buffer layer is set to the window layer (0,92
μm) and the photoconcentration layer (1,67 μm) (1,2~1 μm)
．． Another feature is that it achieves high speed as 4μm).
一般に、化合物半導体へのＺｎまたはＣｄのｐ型不純物
拡散は、第２図のように二段拡散となることが知られて
いる。なお、第２図において横軸は拡散の深さ、縦軸は
キャリア濃度であり、Ａは遅い拡散、Ｂは速い拡散を示
す。Generally, it is known that p-type impurity diffusion of Zn or Cd into a compound semiconductor is a two-stage diffusion as shown in FIG. In FIG. 2, the horizontal axis is the depth of diffusion, and the vertical axis is the carrier concentration, where A indicates slow diffusion and B indicates fast diffusion.
ホトダイオードを高性能化する立場からウィンドウ層４
はキャリア濃度が低い方が望まい１力１、ｐｎ接合形成
の立場からは速い拡散が生じる＆まとにキャリア濃度を
低くすることは、接合の位置の制御性を悪くすることに
なる１本発明のように。Window layer 4 from the standpoint of improving the performance of photodiodes
It is desirable for the carrier concentration to be low.From the standpoint of forming a pn junction, fast diffusion occurs; lowering the carrier concentration at all will impair the controllability of the junction position. Like an invention.
キャリア濃度が高いバッファ層を設けることにより、ウ
ィンドウ層のキャリア濃度を低くすることができ、かつ
ｐｎ接合を制御性良く形成することができる。By providing a buffer layer with a high carrier concentration, the carrier concentration of the window layer can be lowered, and a pn junction can be formed with good controllability.
以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図において、１１はｎ÷−ＩｎＰ基板、１２はｎ″
″−ＩｎＰ層（厚みｌｐｍ）、１３はｎ −−ＩｎＧａ
Ａｓ光吸収層（３ｕｍ） 、１４はｎ−ＩｎＧａ、＾β
ノ（ツファ層（０，５ｐｍ） 、１５はｎ″″−ＩｎＰ
ウィンドウ層（２μｍ）、１６はｐ◆拡散層（ｐ＋−ｘ
ｎｐ及びｐ″″’−ＩｎＧａＡｓｐ） 、１７はパッシ
ベーション膜、１８はｐ型オーミック電極、１９はｉ型
オーミック電極である。In FIG. 1, 11 is n÷-InP substrate, 12 is n''
″-InP layer (thickness lpm), 13 is n--InGa
As light absorption layer (3um), 14 is n-InGa, ^β
ノ(Tuffa layer (0.5pm), 15 is n″″-InP
Window layer (2μm), 16 is p◆diffusion layer (p+-x
17 is a passivation film, 18 is a p-type ohmic electrode, and 19 is an i-type ohmic electrode.
以下に製造方法の概略を示す。An outline of the manufacturing method is shown below.
ｎ型ＩｎＰ基板１１の上に気相成長法または減圧ＯＭ−
ＶＰＥ法を用い、ｎ型ＩｎＰ層１２．ｎ型ＩｎＧａＡｓ
層１３．ｎ型ＩｎＧａＡｓ層１４．ｎ型ＩｎＰ層１５を
連続成長させる。尚、バッファ層１４は拡散を該バッフ
ァ層内に制御すること、結晶成長における厚さ方向の組
成のずれを防止すること等力１ら０．５μｍ程度が好ま
しい１次に、予め設定された温度分布を持つ電気炉に結
晶基板と拡散ソースを真空封止したアンプルを挿入する
ことにより、ＺｎまたはＣｄのｐ型不純物拡散を行う。On the n-type InP substrate 11, vapor phase growth method or reduced pressure OM-
Using the VPE method, an n-type InP layer 12. n-type InGaAs
Layer 13. n-type InGaAs layer 14. The n-type InP layer 15 is grown continuously. The buffer layer 14 is heated at a preset temperature, preferably about 1 to 0.5 μm, to control diffusion within the buffer layer and to prevent deviations in composition in the thickness direction during crystal growth. A p-type impurity of Zn or Cd is diffused by inserting an ampoule in which a crystal substrate and a diffusion source are vacuum-sealed into an electric furnace having a distribution.
その後１周知のＣＶＤ法により、ＳｉＮｘ／ Ｐ Ｓ
Ｇ／５ｉＯｚのパッシベーション膜を形成し、最後番こ
ｐ型オーミック電極、Ａｕ／Ｐｔ／Ｔｉ、ｎ型オーミッ
ク電極Ａ ｕ ／ Ｐ ｄ ／ ＡｕＧｅＮｉを周知の
蒸着法を用いて形成する。After that, SiNx/PS was formed using the well-known CVD method.
A passivation film of G/5iOz is formed, and finally a p-type ohmic electrode, Au/Pt/Ti, and an n-type ohmic electrode, Au/Pd/AuGeNi, are formed using a well-known vapor deposition method.
なお、本実施例においては、光吸収層にＩｎＧａＡｓウ
ィンドウ層にＩｎＰを用いたが、他の化合物半導体系例
えばＧａＡｓ層 ＧａＡ Ｑ Ａｓ系においてもヘテロ
界面に禁止帯の不整が生じる場合には、同様の効果を得
ることができる。In this example, InGaAs is used for the light absorption layer, and InP is used for the window layer, but the same method can be applied to other compound semiconductor systems, such as GaAs layers, GaA Q As systems, if band gap irregularities occur at the hetero interface. effect can be obtained.
本実施例においてｐｎ接合は比較的キャリア濃度の高い
（１０五６３″″＋１以上） ＩｎＧａＡｓＰ層（λ＝
１．３μｍ）内に形成されるため、不純物拡散の制御性
が従来の±０．５μｍから±０．２μｍへ向上している
。また価電子帯のへテロ障壁にもとづく、正孔の蓄積を
防ぐことが可能となり、低ノ（イアスミ圧（−１０Ｖ以
下）で高速動作が可能となる。In this example, the pn junction has a relatively high carrier concentration (10563''+1 or more) and an InGaAsP layer (λ=
1.3 μm), the controllability of impurity diffusion is improved from the conventional ±0.5 μm to ±0.2 μm. Furthermore, it is possible to prevent the accumulation of holes based on the heterobarrier of the valence band, and high-speed operation is possible at low Iasumi pressure (-10 V or less).
〔発明の効果〕
本発明によれば、ＩｎＧａＡｇ光吸収層とＩｎＰウィン
ドウ層間のへテロ界面に生じる正孔の蓄積を防ぐことが
できるので、高速応答可能なプレーナ型長波長ＰＩＮホ
トダイオードを実現可能にする。[Effects of the Invention] According to the present invention, it is possible to prevent the accumulation of holes generated at the hetero interface between the InGaAg light absorption layer and the InP window layer, thereby making it possible to realize a planar type long wavelength PIN photodiode capable of high-speed response. do.
また、ｐｎ接合を比較的キャリア濃度が高い。Further, the pn junction has a relatively high carrier concentration.
ＩｎＧａＡｓＰバッファ層中に形成するため、制御性も
、 向上し、経済的利益も大きい。Since it is formed in the InGaAsP buffer layer, controllability is improved and economic benefits are also large.
第１＠は本発明の実施例であるプレーナ型ＰＩＮホトダ
イオードの縦断面図、第２図は、遅い拡散と速い拡散を
概念的に示す図、第３図は従来形のプレーナ型ＰＩＮホ
トダイオード縦断面図である。
１１−ｎ＋−ＩｎＰ基板、１２− ｎ−−ＩｎＰ層、１
３−・・ｎ−ＩｎＧａＡｓ層（禁止帯幅１．６７ μｍ
） 、１４・・−ｎ ＩｎＧａＡｓＰ層（禁止帯組成
１．３ μｍ） 、１５・＝ｎ −−ＩｎＰ層（禁止帯
幅０．９２ｐｍ） 、１６−ｐ＋−ＩｎＰ層及びｐ ＋
−ＩｎＧａＡｓＰ層、１７・・・パッシベーションｌ
Ｉ％ （Ｓｉ（ｈ／ Ｐ Ｓ Ｇ ／５ｉＮｚ） 、
１８− Ｐ型オーミック電極（Ａｕ／Ｐｄ／Ｔｉ）
、１９−ｎ型￥：Ｊ １ 図
ＹＺ 図
纂 ３ 図Figure 1 is a vertical cross-sectional view of a planar PIN photodiode according to an embodiment of the present invention, Figure 2 is a diagram conceptually showing slow diffusion and fast diffusion, and Figure 3 is a vertical cross-sectional view of a conventional planar PIN photodiode. It is a diagram. 11-n+-InP substrate, 12-n--InP layer, 1
3-...n-InGaAs layer (bandgap width 1.67 μm
), 14...-n InGaAsP layer (forbidden band composition 1.3 μm), 15-=n −-InP layer (forbidden band width 0.92 pm), 16-p+-InP layer and p +
-InGaAsP layer, 17...passivation l
I% (Si(h/PSG/5iNz),
18- P-type ohmic electrode (Au/Pd/Ti)
, 19-n type ￥: J 1 Figure YZ Figure 3 Figure
Claims (1)
含む複数の半導体層を積層して形成するプレーナ型ホト
ダイオードにおいて、光吸収層とウィンドウ層間にバッ
ファ層を設け、ｐｎ接合のフロントをバッファ層中に形
成したことを特徴とするホトダイオード。 ２、特許請求の範囲第１項においてバッファ層の禁止帯
幅を１．２μｍから１．４μｍの間にすることを特徴と
するホトダイオード。 ３、特許請求の範囲第１項において、光吸収層をＩｎＧ
ａＡｓ、ウィンドウ層をＩｎＰ、バッファ層をＩｎＧａ
ＡｓＰ（禁止帯幅：１．３μｍ）としたことを特徴とす
るホトダイオード。[Claims] 1. In a planar photodiode formed by stacking a plurality of semiconductor layers including at least a light absorption layer and a window layer on an n-type substrate, a buffer layer is provided between the light absorption layer and the window layer, and a pn A photodiode characterized in that a junction front is formed in a buffer layer. 2. A photodiode according to claim 1, characterized in that the forbidden band width of the buffer layer is between 1.2 μm and 1.4 μm. 3. In claim 1, the light absorption layer is made of InG.
aAs, window layer InP, buffer layer InGa
A photodiode characterized by being made of AsP (forbidden band width: 1.3 μm).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61064064A JPS62221168A (en) | 1986-03-24 | 1986-03-24 | Photodiode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61064064A JPS62221168A (en) | 1986-03-24 | 1986-03-24 | Photodiode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62221168A true JPS62221168A (en) | 1987-09-29 |
Family
ID=13247287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61064064A Pending JPS62221168A (en) | 1986-03-24 | 1986-03-24 | Photodiode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62221168A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100403824B1 (en) * | 1996-09-24 | 2004-05-17 | 삼성전자주식회사 | Photodiode detector and fabricating method thereof |
-
1986
- 1986-03-24 JP JP61064064A patent/JPS62221168A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100403824B1 (en) * | 1996-09-24 | 2004-05-17 | 삼성전자주식회사 | Photodiode detector and fabricating method thereof |
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