JPS62219961A - Manufacture of thin film mos structure semiconductor device - Google Patents
Manufacture of thin film mos structure semiconductor deviceInfo
- Publication number
- JPS62219961A JPS62219961A JP6444986A JP6444986A JPS62219961A JP S62219961 A JPS62219961 A JP S62219961A JP 6444986 A JP6444986 A JP 6444986A JP 6444986 A JP6444986 A JP 6444986A JP S62219961 A JPS62219961 A JP S62219961A
- Authority
- JP
- Japan
- Prior art keywords
- film
- deposited
- semiconductor device
- islands
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010408 film Substances 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 30
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000007772 electrode material Substances 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 238000004380 ashing Methods 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 27
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
発明の分野
本発明は薄膜型ＭＯＳ構造半導体装置の製造法に関する
ものであシ、具体的には、ＴＰＴ （Ｔｈｉｎ Ｆｉ１
ｍＴｒａｎｓｉａｔｏデ；薄膜トランジスタ）の素子分
離工程に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a thin film type MOS structure semiconductor device, and specifically relates to a method of manufacturing a thin film type MOS structure semiconductor device.
The present invention relates to an element isolation process for thin film transistors.
従来の技術
薄膜型ＭＯＳ構成半導体装置の素子間分離は、基本的に
は以下の工程で行われる。Conventional technology Isolation between elements of a thin film type MOS semiconductor device is basically performed in the following steps.
第２図に示すように、絶縁基板１の上にポリシリコン等
のＳｉ膜を形成し、フォトリングラフィ技術によシ、各
能動領域間の！Ｉｔ ＠を除去し、アイランドτを形成
した後、熱酸化によりゲート酸化膜３を形成すれば、各
能動素子は電気的に分離し得る。次いでゲート酸化膜上
にゲート電極材を成模し、フォトリソグラフィで所要の
形状にバターニングを行い、ゲート電極４を形成し以後
通常のＭＯＳ工程でＭＯ３構造素子を成膜させる。As shown in FIG. 2, a Si film such as polysilicon is formed on an insulating substrate 1, and a Si film such as polysilicon is formed between each active region using photolithography technology. After removing It@ and forming islands τ, each active element can be electrically isolated by forming a gate oxide film 3 by thermal oxidation. Next, a gate electrode material is formed on the gate oxide film and patterned into a desired shape by photolithography to form a gate electrode 4. Thereafter, an MO3 structure element is formed by a normal MOS process.
この製法は、処理方法が単純で工程数が少ないことが特
長であるが、次の欠点を有している。Although this manufacturing method is characterized by a simple processing method and a small number of steps, it has the following drawbacks.
その１は、Ｓ（アイランドの側面と、下地の絶縁基板が
接触する所（第２図のＡ点）で、ゲート酸化膜が薄くな
ることである。素子の使用時ＫＡ点近傍のゲート酸化膜
が絶縁破壊を起こす危険が高くなる。The first is that the gate oxide film becomes thinner at the point where the side surface of the island (S) contacts the underlying insulating substrate (point A in Figure 2).When the device is used, the gate oxide film near the KA point increases the risk of dielectric breakdown.
その２は、素子表面の段差が大きく、以後の工程で配線
の断線や短絡の要因となシ得ること、またフォトリソグ
ラフィの精度を低下させることである。The second problem is that the level difference on the element surface is large, which can cause disconnection or short circuit of wiring in subsequent steps, and also reduces the accuracy of photolithography.
また、素子表面を平坦化する技術として、第３図に示す
ように、絶縁基板１′上にＳｔアイランド２′を形成し
た後（第３図ａ ）、ＣＶＤ法やスパッタ法でＳ（Ｑ、
３’をＳ（アイランド２′の膜厚以上に堆積し、その
上にレジスト４′を塗布して表面を平坦化した後（第３
図６）、ドライエツチングする（第３図Ｃ）いわゆるエ
ッチパック法がある。この素子間分離法は表面の平坦性
は得られるが次の欠点がある。In addition, as a technique for flattening the element surface, as shown in Fig. 3, after forming an St island 2' on an insulating substrate 1' (Fig. 3a), S(Q,
3' is deposited to a thickness greater than that of island 2', and a resist 4' is applied thereon to flatten the surface (3rd layer).
There is a so-called etch pack method in which dry etching (FIG. 3C) is performed. Although this inter-element isolation method provides surface flatness, it has the following drawbacks.
その１は、ＣＶＤ法、あるいはスパッタ法で段差上に堆
積し九５ｔ（ｈ嘆は、ＣＶＤ法では次の文献（村本、中
島；電子通信学会誌Ｖｏ１．６６、 ＮＯ，７，１９８
３）で、またスパッタ法では次の文献（Ｔ、Ｊａデｔｋ
ａｗａ ａｎｄＴ、Ｙａａ屓 ： Ｊ、ＥｌｅａＤｏａ
ｈａｍ、Ｂｏａ、ｔ＋ｏｊ−１２１Ｌ Ｊ’９１８．１
９Ｓｉ ）に各々述べられているように、段差の側壁に
は粗な膜質のＳｔＯ鵞が付着する。この粗な膜質の部分
が以後のエツチングや拡散の工程で欠陥を生じやすい。The first method is to deposit 95t on the step using the CVD method or the sputtering method.
3), and in the sputtering method, the following literature (T, Ja de tk
awa and T, Yaa: J, EleaDoa
ham, Boa, t+oj-121L J'918.1
9Si), a coarse film of StO is deposited on the side wall of the step. This rough film is likely to cause defects in subsequent etching and diffusion steps.
その２は、１積ＳｔＯ，の場合、熱酸化膜に比べＳ（膜
との界面での単位に関連したリーク電流等素子特性を変
動させる要因が多い。従って、ゲート絶縁模の絶縁破壊
や、段差形状や、堆積Ｓｔｏｗ＠の膜質不均一や界面準
位の不安定性等の欠点を排除するため、一般には、Ｓｉ
ウェハＭＯ３ＬｓＩ工程に採用されているｗｃｏｓ法に
準じた素子間分離法（コプレーナプロセス）にょシ製造
されている。Second, in the case of 1 product StO, there are many factors that change device characteristics such as leakage current related to the unit at the interface with S (film) compared to thermal oxide films.Therefore, dielectric breakdown of the gate insulation model, In general, Si
It is manufactured using an element isolation method (coplanar process) similar to the WCOS method adopted in the wafer MO3LsI process.
＠４図ａＫ示した絶縁基板１の上に１ポリシリコン等の
Ｓｉ膜２を堆積する。熱漬化法で薄いＳｔへ層５を形成
した後、ＣＶＤ法で１化シリコン６゜５＋（Ｑ、 ７を
順次堆積する。@4 A Si film 2 such as polysilicon is deposited on the insulating substrate 1 shown in FIG. After forming a layer 5 on a thin St layer by a hot dipping method, silicon monide 6°5+(Q, 7) is sequentially deposited by a CVD method.
下地のＳｔＯ，層５はＳｉ膜２と窒化シリコン６が反応
する等のＳ（膜２と窒化シリコン６が接触することによ
って発生するトラブルを防止するためである。第４図す
て示す如く、フォトリソグラフィ技術で、先ず表面の５
ｉｆｔ ７を部分的に除去し、（第４図Ｃ）更に、それ
をマスクとして窒化シリコン６、 、！（Ｏ＠ ５．
５（１（！’２を順次エツチング除去して第４図ｇの構
造を得る。The underlying StO layer 5 is to prevent troubles caused by contact between the Si film 2 and silicon nitride 6, such as reaction between the Si film 2 and the silicon nitride 6. As shown in FIG. Using photolithography technology, first the surface 5
Partially remove ift 7 (FIG. 4C) and use it as a mask to further remove silicon nitride 6, , ! (O@5.
5(1(!'2) are sequentially removed by etching to obtain the structure shown in FIG. 4g.
次に、Ｓｉｎ雪膜７を除去し、この時Ｓ（膜を約半分の
厚さだけ残すことが、このプロセスの要点である。次に
熱酸化すると、窒化シリコンで被覆されていない部分の
Ｓｉ膜２′は完全に酸化すると約２倍の厚さになシ、第
４図−に示した構造となる。Next, the Si snow film 7 is removed, and the key point of this process is to leave only about half the thickness of the S film. When the film 2' is completely oxidized, it becomes about twice as thick and has the structure shown in FIG.
窒化シリコン６およびその下のｓｔｏｗ ｓを除去する
と第４図！で示した如（５ｉ（ｈ ９とＳ（アイランド
２′の上表面が連続した平坦な素子間分離の構造が得ら
れる。Figure 4 shows the removal of silicon nitride 6 and the stow s below it! As shown in (5i (h 9 and S), a flat element isolation structure in which the upper surface of the island 2' is continuous is obtained.
その後、再度Ｓ（アイランド上にゲート酸化膜３′を形
成しく第４図ｇ）、その上にゲート電極材４を堆積しく
第４図ｈ）、フォトリソグラフィ技術でパターニングを
行いゲート電極８′を形成しく８はレジスト）（第今図
５ｓｊ）、以後通常のプロセスでＭＯ３型素子を形成し
最終的に第４図にの構造となって工程を完了する。After that, the gate oxide film 3' is formed on the island again (Fig. 4g), the gate electrode material 4 is deposited on it (Fig. 4h), and patterning is performed using photolithography to form the gate electrode 8'. 8 is a resist) (FIG. 5sj). Thereafter, an MO3 type element is formed by a normal process, and finally the structure shown in FIG. 4 is obtained, and the process is completed.
以上説明した従来の素子間分離法は工程数が多く、工程
所要時間が長い、更に、Ｓｉ膜の約半分の厚さをエツチ
ング時に残すことが要点になっていてエツチングの制御
性が悪く平坦度に変動が生じる欠点を有している。工程
所要時間が長くなるのは次の理由による。The conventional device isolation method described above requires a large number of steps and takes a long time.Furthermore, the key point is to leave approximately half the thickness of the Si film during etching, resulting in poor etching controllability and poor flatness. It has the disadvantage that fluctuations occur. The reason why the process takes longer is as follows.
（イ）選択酸化のマスクとして窒化シリコンを堆積する
必要がある。(a) It is necessary to deposit silicon nitride as a mask for selective oxidation.
（−この窒化シリコンを用いるため、８４０１層で窒化
シリコンをサンドイッチ構造にする必要がある。(-In order to use this silicon nitride, it is necessary to form a silicon nitride sandwich structure with 8401 layers.
（ハ）堆積したＳｔＯ，、窒化シリコンを除去する必要
がある。(c) It is necessary to remove the deposited StO and silicon nitride.
によるものである。This is due to
発明の目的
本発明は以上の欠点を解決するために提案するもので、
その目的とする所は、局部的ゲート絶縁破壊を防止した
平坦化効果のある薄膜型半導体装置の素子間分離を簡潔
な工程の組合せでしかも少い所要時間で成膜させる方法
を提供することＫある。Purpose of the Invention The present invention is proposed to solve the above-mentioned drawbacks.
The purpose is to provide a method for forming element isolation in a thin film semiconductor device with a flattening effect that prevents local gate dielectric breakdown by using a simple combination of steps and in a short amount of time. be.
、１！關９ｓ叙
発明の要約
上記の目的を達するため、本発明は、絶縁基板上に第１
のポリシリコン等のＳｉ膜を成膜させる工程と、このＳ
（膜をフォトリングラフィ技術で素子形成領域だけをア
イランドとして残し、その他をエツチング除去する工程
と、
このＳｉアイランドを形成した後、更に全面に第１のＳ
ｉ膜厚よシ薄い第２のポリシリコン等のＳｉ膜を堆積す
る工程と、この第２の堆積したポリシリコン等のＳ（膜
を熱酸化で完全にＳｔＯ，にする工程と。, 1! Summary of the Invention In order to achieve the above object, the present invention provides a first
The process of forming a Si film such as polysilicon, and this S
(The film is etched using photolithography technology, leaving only the element formation area as an island and removing the rest by etching. After forming this Si island, the first S
A step of depositing a second Si film such as polysilicon that is thinner than the thickness of the i film, and a step of thermally oxidizing the second deposited S film of polysilicon or the like to completely convert it into StO.
第１のＳｉ膜によるＳ（アイランド表面のＳｔＯ，をフ
ォトエツチング法、あるいはエッチバック法で除去する
工程と、その後、Ｓｉアイランド表面にゲート酸化膜を
成膜させる工程と、ゲート酸化膜上にゲート電極材を堆
積してパターニングしてゲート電極を成膜させる工程と
を含むことを特徴とする薄膜型ＭＯｆｌ ｐ造の素子間
分離の製造法を提供するものである。A process of removing S (StO on the island surface) from the first Si film by a photoetching method or an etch-back method, followed by a process of forming a gate oxide film on the Si island surface, and a process of forming a gate oxide film on the gate oxide film. The present invention provides a method for manufacturing element isolation in a thin film type MOflp structure, which is characterized by including a step of depositing and patterning an electrode material to form a gate electrode.
従来の窒化シリコンを用いた複雑多岐にわたる工程を要
する選択酸化法と同等の性能を有する素子間分離を、第
１の３４膜の上にポリシリコン等の第２のＳ（膜を堆積
し、酸化するだけの簡潔単純な短工糧で形成し得ること
に本発−の特長がある。A second S film, such as polysilicon, is deposited on top of the first 34 films, and a second S (film) such as polysilicon is deposited on top of the first 34 films, and then oxidized. The feature of this invention is that it can be formed with simple and simple steps.
実施例 本発明の実施１例を図面に基づいて説明する。Example An embodiment of the present invention will be described based on the drawings.
なお、実施例は一つの例示であって、本発明の主旨を逸
脱しない範囲で種々の変更、あるいは改良を行い得るこ
とは云うまでもない。Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
まｆ−１ＭＯＪ構造の半導体素子について説明している
が、本発明による素子間分離は、バイポーラ素子等の能
動素子や、キャパシター、抵抗等の受動素子間の分離法
としても有効であることは明白である。Although a semiconductor device with an f-1 MOJ structure has been described, it is clear that the device isolation according to the present invention is also effective as a method for separating active devices such as bipolar devices, and passive devices such as capacitors and resistors. It is.
第１図α〜ｊに、本発明の半導体装置の製造法の実施例
（工程図）を示す。FIGS. 1a to 1j show an embodiment (process diagram) of the method for manufacturing a semiconductor device of the present invention.
第１図αに示す絶縁基板（石英製）１の上に１ＣＶＤ法
によシポリシリコン膜２と２００ＯＡ堆積した。A polysilicon film 2 of 200 OA was deposited on an insulating substrate (made of quartz) 1 shown in FIG. 1α by the 1CVD method.
次に、フォトリングラフィ技術を用いてポリシリコン膜
の素子形成領域以外をＣＣ１，Ｆ、を用いたプラズマエ
ツチングで除去し、第１図すに示すポリシリコンのアイ
ランド２′構造を形成した。６００℃の酸素雰囲気中で
レジストを灰化除去した後、再度この表面に第２のポリ
シリコン２１をＣＶＤ 法によシ約８００Ｘの厚さに堆
積した（第１図６）。次に、９００Ｃ６０分のウェット
熱酸化法でこの第２のポリシリコン膜２′を完全に酸化
して５ｉｎＨ層９に変えると、素子を成膜させるポリシ
リコンアイランド２′が熱酸化膜で分離された素子間分
離構造が第１図ｄＫ示した如く形成される。ポリシリコ
ンアイランド間の８４０．９の厚さは約１５０ＯＡであ
る。この熱酸化工程では、超過に対して、即ち第１のポ
リシリコン膜２′まで酸化が進行しても支障はなく、素
子間分離工程における条件の許容範囲が広く、再現性の
高いプロセスである。Next, using a photolithography technique, the polysilicon film other than the element formation region was removed by plasma etching using CC1, F to form a polysilicon island 2' structure as shown in FIG. After the resist was ashed and removed in an oxygen atmosphere at 600° C., second polysilicon 21 was deposited on this surface again to a thickness of about 800× by CVD method (FIG. 1, 6). Next, when this second polysilicon film 2' is completely oxidized by a wet thermal oxidation method of 900C for 60 minutes and turned into a 5inH layer 9, the polysilicon islands 2' on which the elements are formed are separated by a thermal oxide film. A device isolation structure is formed as shown in FIG. 1dK. The thickness of 840.9 between polysilicon islands is approximately 150 OA. In this thermal oxidation process, there is no problem even if the oxidation progresses to the first polysilicon film 2', and the tolerance range of conditions in the element isolation process is wide, making it a highly reproducible process. .
この実施例では、この後、ポリシリコンアイランド２′
上のＳｔＯ，を通常のポジレジストによるフォトリング
ラフィ技術を用いて、フォトレジスト８でマスクし、緩
衝弗酸溶液でエツチング除去し、第４図−１ｆに示した
構造とし、続いて９００℃２０分のウェット熱酸化法で
１００ＯＡのゲート酸化膜３を形成した（第１図ｇ）。In this embodiment, after this, the polysilicon island 2'
The above StO was masked with a photoresist 8 using a photolithography technique using a normal positive resist, and etched away with a buffered hydrofluoric acid solution to obtain the structure shown in Fig. 4-1f. A gate oxide film 3 of 100 OA was formed using a wet thermal oxidation method for 10 minutes (FIG. 1g).
以後、通常のプロセス通りに、ゲート電極材４としてポ
リシリコンを堆積し、バターニング後ソース、トレー７
１０をイオン注入法で形成しく第１図ん、ｉ）、続いて
スパッタＳｔＯ，で層間絶縁膜１１を４積し、スルーホ
ールを介して、４ｊ１４１極１２で接続し、最終的に第
３図ｊに示す構造の、薄膜型ＭＯＳ構造半導体装置を完
成した。Thereafter, polysilicon is deposited as the gate electrode material 4 according to the usual process, and after buttering, the source and tray 7 are deposited.
10 is formed by ion implantation (Fig. 1, i), then four interlayer insulating films 11 are deposited by sputtering StO, and connected by 4j141 poles 12 via through holes, finally as shown in Fig. 3. A thin film MOS semiconductor device having the structure shown in j was completed.
以上説明した本発明の実施例では、ポリシリコンアイラ
ンド上の５ｉ０２を最も簡単なフォトレジストを用い友
邦酸系ウェットエツチングで除去する方法を示した。こ
の方法では、第１図ｆでわかる通り、アイランド周縁に
第２ポリシリコンを酸化した５ｉｆｔが残存して、完全
平坦な構造とはなっていない。しかしこの段差は１５０
０７以下と薄いことウェットエツチングや、ゲート酸化
時に角が滑らかとなるためゲート電極の断線等素子特性
に支障を起こすものではない。しかも、第２ポリシリコ
ンの堆積膜厚でこの段差を制御することが可能である。In the embodiment of the present invention described above, a method was shown in which 5i02 on a polysilicon island was removed by amic acid-based wet etching using the simplest photoresist. In this method, as can be seen from FIG. 1(f), 5ifts formed by oxidizing the second polysilicon remain at the periphery of the island, and a completely flat structure is not obtained. However, this step is 150
Since the thickness is less than 0.07 mm, the corners are smooth during wet etching and gate oxidation, so there is no problem with device characteristics such as disconnection of the gate electrode. Moreover, it is possible to control this step difference by controlling the deposited film thickness of the second polysilicon.
高密度化等の対策として、よシ平坦化が必須の場合には
、第２ポリシリコンの酸化後の膜厚が、第１ポリシリコ
ンアイランドの膜厚と同等以上になるように第２ポリシ
リコンを堆積し、次に７オトレジストをその表面が平坦
を得るに充分な膜厚に全面塗布した後、イオンエツチン
グでポリシリコンアイランドの表面が現われるまで全面
をエツチング除去するいわゆるエッチバック法を用いれ
ば、熱酸化膜で平坦な素子間分離を成膜させることがで
きる。If planarization is essential as a countermeasure for higher density, etc., the second polysilicon film should be made so that the film thickness after oxidation of the second polysilicon island is equal to or greater than the film thickness of the first polysilicon island. If we use the so-called etch-back method, in which we deposit 7 photoresist on the entire surface to a thickness sufficient to obtain a flat surface, and then use ion etching to remove the entire surface until the surface of the polysilicon island appears. A flat device isolation can be formed using a thermal oxide film.
発明の効果
以上のように本発明によれば、薄膜型半導体装置の素子
間分離を、単純で、再現性の高い工程を用いて、平坦か
つ耐絶繰性に優れた構造として形成し得る利点がある。Effects of the Invention As described above, the present invention has the advantage that the isolation between elements of a thin film semiconductor device can be formed into a flat structure with excellent repeatability using a simple and highly reproducible process. There is.
更に、従来の方法と比較して素子間分離に要する工程数
を４０幅以上低減できる利点がある。Furthermore, compared to conventional methods, there is an advantage that the number of steps required for isolation between elements can be reduced by more than 40 widths.
半導体装置の製造法を示す工程図である。FIG. 3 is a process diagram showing a method for manufacturing a semiconductor device.
第２図、第３図ａ −ａ工程図及び第４図α〜に工程図
は、従来の薄膜型ＭＯＳ構造半導体装置の製造法を説明
するための図である。The process diagrams in FIGS. 2 and 3 a-a and FIGS.
１・・・絶縁基板
２・・・ポリシリコン等Ｓ（膜（基板Ｓｉ膜）２′・・
・分離されたＳｉ膜
２′・・・第１のＳｔＨに重さねて准覆し九Ｓｉ膜３・
・・ゲート酸化膜
４・・・ゲート電極（材）
５・・・下地ｓｔｏ、 ｇ
６゛・・・窒化Ｓｉ膜
７・・・マスクＥｊｉ０２膜
８・・・フォトレジスト
９・・・素子間分離用ポリシリコンの酸化３４０゜１０
・・・ソースとドレーン
１１・・・層間５ｉＯ１
１２・・・Ａｆｉ電極
特許出願人 日本電信電話株式会社
代理人 弁理出玉１久五部（外２名）
第 １ 図
２′： アイランド ４； ゲート電極ｊｌＮ２
図1... Insulating substrate 2... Polysilicon etc. S (film (substrate Si film) 2'...
・Separated Si film 2'...overlay on the first StH and semi-overlap 9 Si film 3.
...Gate oxide film 4...Gate electrode (material) 5...Base sto, g 6゛...Si nitride film 7...Mask Eji02 film 8...Photoresist 9...Isolation between elements Oxidation of polysilicon for 340°10
... Source and drain 11 ... Interlayer 5iO1 12 ... Afi electrode patent applicant Nippon Telegraph and Telephone Corporation representative Patent attorney 1 Kugobe (2 others) 1st Figure 2': Island 4; Gate Electrode jlN2
figure
Claims (3)
と、 （ロ）前記Ｓｉ膜を選択除去し、アイランド状に素子形
成領域を形成する工程と、 （ハ）前記、素子形成領域がアイランド状に分離された
表面に第２のＳｉ膜を全面に堆積する工程と、 （ニ）次に第２のＳｉ膜を完全に酸化させ、素子形成領
域のＳｉアイランドを酸化物内に埋め込んだ構造の素子
間分離領域を形成する工程と、 （ホ）次に、Ｓｉアイランド上の酸化物を選択除去する
工程と、 （ヘ）前記Ｓｉアイランド上にＭＯＳ構造半導体装置の
ゲートと絶縁膜を成膜させる工程と （ト）前記ゲート絶縁膜上にゲート電極を形成する工程
と、 を含むことを特徴とする薄膜型ＭＯＳ構造半導体装置の
製造法。(1) (A) A step of forming a first Si film on an insulating substrate; (B) A step of selectively removing the Si film to form an island-shaped element formation region; (C) A step of forming an element formation region on the insulating substrate A step of depositing a second Si film over the entire surface of the surface where the formation region is separated into islands; (iv) Next, the second Si film is completely oxidized, and the Si islands in the element formation region are covered with oxide. (e) Next, a step of selectively removing the oxide on the Si island; and (f) forming an isolation region with a gate of a MOS structure semiconductor device on the Si island. A method for manufacturing a thin-film MOS structure semiconductor device, comprising the steps of: (g) forming a film on the gate insulating film; and (g) forming a gate electrode on the gate insulating film.
酸化物を選択除去する工程がフォトリソグラフィ技術に
よるエッチング法を用いることを特徴とする薄膜型ＭＯ
Ｓ構造半導体装置の製造法。(2) A thin film type MO characterized in that the step of selectively removing the oxide on the Si island according to claim 1 uses an etching method using photolithography technology.
A method for manufacturing an S-structure semiconductor device.
酸化物を選択除去する工程がエッチバック法を用いるこ
とを特徴とする薄膜型ＭＯＳ構造半導体装置の製造法。(3) A method for manufacturing a thin-film MOS structure semiconductor device, wherein the step of selectively removing the oxide on the Si island according to claim 1 uses an etch-back method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6444986A JPH0620138B2 (en) | 1986-03-22 | 1986-03-22 | Method of manufacturing thin film MOS structure semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6444986A JPH0620138B2 (en) | 1986-03-22 | 1986-03-22 | Method of manufacturing thin film MOS structure semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62219961A true JPS62219961A (en) | 1987-09-28 |
| JPH0620138B2 JPH0620138B2 (en) | 1994-03-16 |
Family
ID=13258572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6444986A Expired - Lifetime JPH0620138B2 (en) | 1986-03-22 | 1986-03-22 | Method of manufacturing thin film MOS structure semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620138B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01295463A (en) * | 1988-05-24 | 1989-11-29 | Nippon Soken Inc | Thin film semiconductor element and manufacture thereof |
| JPH0766424A (en) * | 1993-08-20 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JP2009170794A (en) * | 2008-01-18 | 2009-07-30 | Advanced Lcd Technologies Development Center Co Ltd | Method of manufacturing thin film semiconductor device |
-
1986
- 1986-03-22 JP JP6444986A patent/JPH0620138B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01295463A (en) * | 1988-05-24 | 1989-11-29 | Nippon Soken Inc | Thin film semiconductor element and manufacture thereof |
| JPH0766424A (en) * | 1993-08-20 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6010924A (en) * | 1993-08-20 | 2000-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating a thin film transistor |
| US6841432B1 (en) | 1993-08-20 | 2005-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
| US7354811B2 (en) | 1993-08-20 | 2008-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
| US7585715B2 (en) | 1993-08-20 | 2009-09-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
| JP2009170794A (en) * | 2008-01-18 | 2009-07-30 | Advanced Lcd Technologies Development Center Co Ltd | Method of manufacturing thin film semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0620138B2 (en) | 1994-03-16 |
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