JPS62216389A - Manufacture of semiconductor light emitting device - Google Patents
Manufacture of semiconductor light emitting deviceInfo
- Publication number
- JPS62216389A JPS62216389A JP61059722A JP5972286A JPS62216389A JP S62216389 A JPS62216389 A JP S62216389A JP 61059722 A JP61059722 A JP 61059722A JP 5972286 A JP5972286 A JP 5972286A JP S62216389 A JPS62216389 A JP S62216389A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- emitting device
- semiconductor light
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 20
- 150000001875 compounds Chemical class 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 8
- -1 indium phosphorus compound Chemical class 0.000 claims 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 45
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000029052 metamorphosis Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、埋め込み構造の半導体発光装置の活性領域
をストライプ状に成形するに際して、半導体層の組成に
よる選択的異方性エツチング処理と、非選択的等方性エ
ツチング処理とを実施することにより、
良好な制御性を確保して、半導体発光装置の特性を向上
するようにしたものである。[Detailed Description of the Invention] [Summary] The present invention utilizes a selective anisotropic etching process depending on the composition of a semiconductor layer and a non-selective isotropic etching process when forming an active region of a semiconductor light emitting device with a buried structure into a stripe shape. By performing a chemical etching process, good controllability is ensured and the characteristics of the semiconductor light emitting device are improved.
本発明は半導体発光装置の製造方法にかかり、特に埋め
込み構造の半導体発光装置のストライプ領域と埋め込み
層との界面における漏れ電流等の問題を抑止して、閾値
電流の低減、効率の向上環を実現する製造方法の改善に
関する。The present invention relates to a method for manufacturing a semiconductor light emitting device, and in particular, suppresses problems such as leakage current at the interface between the striped region and the buried layer of a semiconductor light emitting device with a buried structure, thereby reducing threshold current and improving efficiency. This invention relates to improvements in manufacturing methods.
光を情報信号の媒体とする光通信その他のシステムにお
いて、光信号を発生ずる光源として半導体発光装置が撓
めて重要な役剖を果たし７（いる。In optical communications and other systems that use light as a medium for information signals, semiconductor light emitting devices play an important role by bending as light sources that generate optical signals.
従ってこれらのシステムの高度化と多様化を進めるため
に、半導体発光装置特にレーデに−）い（閾値電流、効
率などの特性の一層の向１−が要望されている。Therefore, in order to advance the sophistication and diversification of these systems, semiconductor light emitting devices, especially LEDs, are required to have even better characteristics (threshold current, efficiency, etc.).
例えば光通信の石英系ファイバによる伝送に適する波長
１．３〜１．６μｍ程度の帯域の半導体レーザとして、
第２図に模式側断面図を示すインジウム燐／インジウム
ガリウＪ、砒素ｇ（ＩｎＰ／ １ｎＧ８八ｓＰ）系ＢＨ
（Ｂｕｒｉｅｄ ｌ！ｅｔｅｒｏｓＬｒｕｃｔｕｒｅ）
レーザが知ＣＩれている・分布帰還形１ｎＰ／ １ｎＧ
ａＡｓＰ系１１１ル−ザの゛１′、導体基体は、例えば
ｎ型１ｎＰ基机２１１−に回折４８ｒ（本断面図には周
期構造が現れない）を形成し３、二の基板面上にエピタ
キシャル成長したｎ型１ｎＧａＡｓＰ 導波層２２、Ｉ
ｎＧａＡｓＰ活性層２３、ｐ型１ｎｌ’閉し込め層２４
及びｐ型１ｎＧａＡｓＰコンタクト層２５からなるー・
テロ接合積層構造をメサエッチングしてストライプ領域
域を形成し、このエツチングした領域に埋め込め成長し
たｐ型１ｎＰ電流狭窄層２７及びｎ型１ｎＰブロック層
２８により、レーザ光の横モードを制御する屈折率ガイ
ディングと電流狭窄を行っ°ζいる。For example, as a semiconductor laser with a wavelength band of about 1.3 to 1.6 μm, which is suitable for transmission using a silica fiber for optical communication,
Indium phosphorus/indium galliu J, arsenic g (InP/1nG88sP) system BH whose schematic side sectional view is shown in Figure 2
(Buried l! eteros Architecture)
The laser is known as CI/distributed feedback type 1nP/1nG
The conductor substrate 1' of the aAsP-based 111 router is, for example, formed with a diffraction 48r (periodic structure does not appear in this cross-sectional view) on the n-type 1nP substrate 211-, and epitaxially grown on the substrate surface of 3 and 2. n-type 1nGaAsP waveguide layer 22, I
nGaAsP active layer 23, p-type 1nl' confinement layer 24
and a p-type 1nGaAsP contact layer 25.
The telojunction stacked structure is mesa-etched to form a stripe region, and the p-type 1nP current confinement layer 27 and n-type 1nP blocking layer 28 grown by filling the etched region provide a refractive index that controls the transverse mode of the laser beam. Guiding and current constriction are performed.
なお２９は絶縁膜、３０はｎ側電極、３１はｎ側電極で
ある。Note that 29 is an insulating film, 30 is an n-side electrode, and 31 is an n-side electrode.
本従来例において、半導体層のエピタキシャル成長は半
導体基板２１の（１００）面上に行い、かつストライプ
領域の長さ方向を（０１１）方向としζいる。In this conventional example, the epitaxial growth of the semiconductor layer is performed on the (100) plane of the semiconductor substrate 21, and the length direction of the stripe region is the (011) direction.
これはこの結晶方向にマスクを設け、臭素（Ｂｒ） −
メタノール（ＣＩ＋３０１１）溶液等によりメサ形にエ
ツチングを行えば、図示の如＜ （１１＋）Ａ面がエツ
チング面に現れて活性層２３近傍の幅が最も狭くなる断
面形状となり、レーザの横モード制御のために重要であ
る活性層２３の幅の制御が容易となるごとによる。This provides a mask in this crystal direction and bromine (Br) −
If etching is performed in a mesa shape using a methanol (CI+3011) solution, etc., the <(11+)A plane appears on the etched surface as shown in the figure, resulting in a cross-sectional shape in which the width near the active layer 23 is the narrowest, which is useful for laser transverse mode control. This is because the width of the active layer 23, which is important for this purpose, can be easily controlled.
上述のメサ形ストライプ領域を形成する異方性エツチン
グ方法ではメサ側面に（ＩＩＩ）Ａ面が現れ、埋め込み
成長に際してはこの（ＩＩＩ）Ａ面」−に、前記ｐ型１
ｎＰ電流狭窄層２７及びｎ型１ｎＰブロック層２Ｂを例
えば液相エビタ、１−ンヤル成長方法により成１くさセ
ることとなる。In the above-mentioned anisotropic etching method for forming the mesa-shaped stripe region, the (III)A plane appears on the side surface of the mesa, and during buried growth, the p-type 1
The nP current confinement layer 27 and the n-type 1nP block layer 2B are grown using, for example, a liquid phase Evita or 1-N-Y growth method.
゛ 然るにこの（１１１）Ａ面はｌｎＱの１１１族
川ｌｒ−で構成される面であり、エツチング処理の際に
ＩＡＩ囲の酸素（０，）と化合し汚染を受は易いこと、
埋め込めエピタキシャル成長工程において熱変成を受は
易いこと、他の面に比較して成長が遅いことなどの問題
がある。なおこの熱変成により闇値電流の増大、効率の
低下が現れるが、これはストライプ領域と埋め込み層と
の界面に過剰のＩｎによる導電経路が形成されることに
よると考えられる。゛However, this (111) A surface is a surface composed of lr- of the 111 group of lnQ, and is easily susceptible to contamination by combining with oxygen (0,) surrounding IAI during the etching process.
In the buried epitaxial growth process, there are problems such as easy thermal transformation and slow growth compared to other surfaces. Note that this thermal metamorphosis causes an increase in dark value current and a decrease in efficiency, but this is thought to be due to the formation of a conductive path by excess In at the interface between the striped region and the buried layer.
この問題に対して、活性層をメサの最もくびれた位置或
いはその下に置き、活性層側面は（ｉｌ１）へ面から外
す製造方法が試みられているが、この場合にも上側の閉
じ込め層側面には（ＩＩＩ）Ａ面が現ねるのみならず、
この活性層の位置制御は安定性が乏しい。To solve this problem, a manufacturing method has been attempted in which the active layer is placed at the narrowest position of the mesa or below it, and the side surface of the active layer is removed from the plane (il1), but in this case also, the side surface of the upper confinement layer Not only does side (III) A appear in
This position control of the active layer has poor stability.
上述の如き現状から、メサ形ストライブ領域の断面形状
の制御性を確保して前記問題点を解決する製造方法が強
く要望されている。Under the current situation as described above, there is a strong demand for a manufacturing method that solves the above problems by ensuring controllability of the cross-sectional shape of the mesa-shaped strip region.
前記問題点は、化合物半導体基板の（１００）面」二に
、２元化合物半導体層と混晶化合物半導体層とからなる
ヘテロ接合構造を形成し、
該２元化合物半導体層と該混晶化合物半導体層とに順次
選択的異方性エツチング処理を行って、長辺が［０１１
）方向のストライプ状をなずメサ領域を形成し、
更に非選択的等方性エツチング処理を行って該メサ領域
を所要の形状に成形し、
次いで該メサ領域を埋め込む半導体層を成長する本発明
による半導体発光装置の製造方法により解決される。The problem is that a heterojunction structure consisting of a binary compound semiconductor layer and a mixed crystal compound semiconductor layer is formed on the (100) plane of a compound semiconductor substrate, and the binary compound semiconductor layer and the mixed crystal compound semiconductor The layers are sequentially subjected to selective anisotropic etching treatment so that the long sides are [011
In the present invention, a mesa region is formed in a stripe shape in the ) direction, the mesa region is further formed into a desired shape by performing a non-selective isotropic etching process, and then a semiconductor layer is grown to fill the mesa region. The problem is solved by a method of manufacturing a semiconductor light emitting device according to the present invention.
本発明の半導体発光装置の製造方法では、化合物半導体
基板の（１００）面上のへテロ接合構造の半導体層をス
トライプ状のメサ領域に成形するに際し、まず２元化合
物層と混晶化層′１シＪ層との伺相が１方のみに選択的
に作用する異方性エツチング法により、長辺が（０１１
）ソノ向のストライプ状を八ずメサ領域を良好な制御性
をもって形成し、更に非選択的等方性エツチング処理を
行って、メサ領域を結晶面が表出しない所要の形状、寸
法とする。In the method for manufacturing a semiconductor light emitting device of the present invention, when forming a semiconductor layer having a heterojunction structure on the (100) plane of a compound semiconductor substrate into a striped mesa region, first a binary compound layer and a mixed crystal layer ' The long side is (011
) A mesa region having a striped shape in the sono direction is formed with good controllability, and then a non-selective isotropic etching process is performed to give the mesa region a required shape and size in which no crystal plane is exposed.
この本発明の製造方法によれば、活１７１領域の形状、
寸法の制御性は従来方法以」二に良好であり、かつ（１
１１）へ面が除去されるために先に述べた問題点が解決
され、特性の良好な半導体発光装置を得ることができる
。According to the manufacturing method of the present invention, the shape of the active 171 region,
The controllability of dimensions is better than the conventional method, and (1)
11) Since the surface is removed, the above-mentioned problems are solved, and a semiconductor light emitting device with good characteristics can be obtained.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図ｆａｌ〜ｆｄ＋は本発明の実施例を示すＬ稈順模
式側断面図である。FIG. 1 fal to fd+ are schematic side sectional views in the order of L culm showing an embodiment of the present invention.
第１図＋ａｌ参照： ｎ型１ｎＰ基板１の（１００）而
１゜で（０１１）方向（紙面に垂直方向）に例えば周期
Δ！３０．２μｍの回折格子を形成し、この面」二に厚
さ例えば０．１５声、ノンドープでルミネセンスビーク
波長１．２μｍの１ｎＧａＡｓＰ導波層２、厚さ例えば
０．１２μｍ。Refer to Figure 1 + al: For example, the period Δ! of the n-type 1nP substrate 1 is (100) at 1° in the (011) direction (perpendicular to the plane of the paper). A 30.2 μm diffraction grating is formed on this surface, and a 1nGaAsP waveguide layer 2, undoped and having a luminescence peak wavelength of 1.2 μm, has a thickness of, for example, 0.15 μm.
ノンドープでルミネセンスピーク波長１．３μｍの１ｎ
ＧａＡｓＰ活性層３、厚さ例えば１．５μｍ、キャリア
濃度７×１０１７ｃｆｆＩ−３程度のｐ型１ｎＰ閉じ込
め層４、厚さ例えば０．５μｍ、キャリア濃度］ ＸＩ
Ｏ”ｃｍ−３程度のｐ型１ｎＧａＡｓＰコンタクト層５
を順次エピタキシャル成長する。Non-doped 1n with a luminescence peak wavelength of 1.3μm
GaAsP active layer 3, thickness, e.g., 1.5 μm, carrier concentration of about 7×10 17 cffI-3, p-type 1nP confinement layer 4, thickness, e.g., 0.5 μm, carrier concentration] XI
P-type 1nGaAsP contact layer 5 of about O"cm-3
are sequentially grown epitaxially.
ストライプ領域形成のためのマスク６を、例えば二酸化
シリコン（ＳｉＯ□）、窒化シリコン（ＳｉＮ、）、酸
化アルミニウム（＾１Ｊ３）等によって、この半導体基
体面上（Ｏｌ１）方向に、例えば幅２．５〜３−１厚さ
１００面程度に形成する。A mask 6 for forming a stripe region is made of, for example, silicon dioxide (SiO□), silicon nitride (SiN, ), aluminum oxide (^1J3), etc., in the direction of the semiconductor substrate surface (Ol1), and has a width of, for example, 2.5 mm. ~3-1 Form to a thickness of about 100 sides.
第１図（ｂｌ参照： この半導体基体にストライプ領域
を形成するための第１のエツチング処理として、ＩｎＧ
ａＡｓＰからなるコンタクト層５、活性層３及び導波層
２は硝酸（ＩＩＮＯ３）で、ＩｎＰからなるｐ型閉じ込
め層４は臭化水素酸（ＩＩＢｒ）又は塩酸（ＩＩＣＩ）
で、順次それぞれ選択的にエツチングする。FIG. 1 (see BL: InG
The contact layer 5, active layer 3, and waveguide layer 2 made of aAsP are made of nitric acid (IINO3), and the p-type confinement layer 4 made of InP is made of hydrobromic acid (IIBr) or hydrochloric acid (IICI).
Then, each layer is selectively etched in turn.
この第１のエツチング処理は異方性で、メサ断面はＩｎ
ＧａＡｓＰ層５．３．２では（ＩＩＩ）Ａ面、ＩｎＰｌ
ｉ４では（ＩＩＩ）８面が側面に現、１′する図示の！
Ｉｌｌき形状となる。This first etching process is anisotropic and the mesa cross section is In
In GaAsP layer 5.3.2, (III) A plane, InPl
In i4, (III) 8 sides appear on the side, and 1' as shown in the figure!
The shape becomes Ill.
第１図ｔＣ）参照二 次いで第２のエツチング処理を行
う。この処理は非選択付かつ等方性で勺イ１−エツチン
グが比較的に大きいエツチング方υ１、例えばｌｌＢｒ
と過酸化水素水（ｌｈｏ、ｔ）との１（合液によるウェ
ットエツチングなどによる。この処理により（１１１）
Ａ面、（１１１）Ｉ（面が現れない図示の如きメサ断面
形状となる。See Figure 1 tC) 2. Next, a second etching process is performed. This process is performed using a non-selective and isotropic etching method υ1 where the etching is relatively large, such as llBr.
and hydrogen peroxide solution (lho, t) (by wet etching with a mixed solution. By this treatment, (111)
A-plane, (111)I (the mesa cross-sectional shape as shown in the figure does not appear).
第１図（ｄｌ参照： この半導体基体に、ｊｖさ例えば
１．５ｐｍ、キャリア濃度１ ×１０１１０１Ｂａ程度
のｐ型ＩｎＰ電流狭窄層７、厚さ例えば１．５μｌ、キ
ャリア濃度７ ＸＩＱ”ｃｍ−’程度のｎ型１ｎＰ電流
ブロック層８を順次埋め込み成長する。FIG. 1 (See dl: On this semiconductor substrate, a p-type InP current confinement layer 7 with a jv size of, for example, 1.5 pm and a carrier concentration of about 1 × 101101 Ba, a thickness of, for example, 1.5 μl, and a carrier concentration of about 7 An n-type 1nP current blocking layer 8 is sequentially buried and grown.
この成長は通常液相エピタキシャル成長法により、かつ
成長直前にＩｎ又は成長開始温度より低い飽和温度を持
つＩｎＰ溶液を用いて、溶液溶解のための加熱により劣
化した半導体基体の表層部分をメルトハックすることが
望ましい。本実施例ではこのメルトバンク後の活性層３
０幅を例えば約１μｍとしている。This growth is usually carried out by liquid phase epitaxial growth, and immediately before the growth, an InP solution having a saturation temperature lower than the growth initiation temperature is used to melt-hack the surface layer of the semiconductor substrate, which has deteriorated due to heating to dissolve the solution. desirable. In this embodiment, the active layer 3 after this melt bank is
The zero width is, for example, approximately 1 μm.
次いでマスク６を除去して、例えばＳｉｎ、絶縁膜９、
ｐ側電極１０及びｎ側電極１１を形成し、チップ分割等
のプロセスを経て本実施例の素子が完成する。Next, the mask 6 is removed and, for example, a Sin film, an insulating film 9,
A p-side electrode 10 and an n-side electrode 11 are formed, and the device of this example is completed through processes such as chip division.
本実施例では、闇値電流２０ｍＡ以下、定格動作状態に
おける外部微分効率２０％程度が得られ、これに相当す
る前記従来例では、例えば闇値電流約２０〜３０ｍＡ、
外部微分効率１５％程度であるのに比較して明らかな向
」二が実証されている。In this embodiment, a dark value current of 20 mA or less and an external differential efficiency of about 20% in the rated operating state are obtained.
Although the external differential efficiency is about 15%, a clear improvement has been demonstrated.
以上説明した如く本発明によれば、旧ル−ザのストライ
ブ領域を良好な制御性をもって（ＩＩＩ）へ面を残すこ
となくメサエツチングすることが可能となり、半導体発
光装置の闇値電流、効率などの特性が向上し、その結果
出力の増大、使用温度範囲の拡大等も可能となり、光応
用システムなどの進展に寄与することができる。As explained above, according to the present invention, it is possible to perform mesa etching on the stripe region of the old router with good controllability without leaving a surface (III), thereby improving dark value current, efficiency, etc. of semiconductor light emitting devices. As a result, it becomes possible to increase output and expand the operating temperature range, contributing to the advancement of optical application systems.
第１図ｆａ）〜＋ｄｌは本発明の実施例の■稈順模式側
断面図、
第２図は従来例の模式側断面図である。
図において、
１はｎ型１ｎＰ基板、 ２はＩｎＧａＡｓＰ ’ｉｌｌ
波層、３はＩｎＧａＡｓＰ活性層、
４はｐ型ＴｎＰ閉じ込め層、
５はｐ型１ｎＧａＡｓＰコンタクト層、６はマスク、
７はｐ型１ｎＰ電流狭窄層、８はｎ型１ｎＰ電流
ブロック層、
９は絶縁膜、 １０はｐ側電極、１１はｎ側電極
を示す。FIG. 1 fa) to +dl are schematic side sectional views of the embodiment of the present invention in culm order, and FIG. 2 is a schematic side sectional view of the conventional example. In the figure, 1 is an n-type 1nP substrate, 2 is an InGaAsP 'ill
wave layer, 3 is an InGaAsP active layer, 4 is a p-type TnP confinement layer, 5 is a p-type 1nGaAsP contact layer, 6 is a mask,
7 is a p-type 1nP current confinement layer, 8 is an n-type 1nP current blocking layer, 9 is an insulating film, 10 is a p-side electrode, and 11 is an n-side electrode.
Claims (1)
半導体層と混晶化合物半導体層とからなるヘテロ接合構
造を形成し、 該２元化合物半導体層と該混晶化合物半導体層とに順次
選択的異方性エッチング処理を行って、長辺が〔０１１
〕方向のストライプ状をなすメサ領域を形成し、 更に非選択的等方性エッチング処理を行って該メサ領域
を所要の形状に成形し、 次いで該メサ領域を埋め込む半導体層を成長することを
特徴とする半導体発光装置の製造方法。 ２）前記２元化合物半導体がインジウム燐化合物、前記
混晶化合物半導体がインジウムガリウム砒素燐化合物又
はインジウムガリウム砒素化合物であることを特徴とす
る特許請求の範囲第１項記載の半導体発光装置の製造方
法。[Claims] 1) A heterojunction structure consisting of a binary compound semiconductor layer and a mixed crystal compound semiconductor layer is formed on the (100) plane of a compound semiconductor substrate, and the binary compound semiconductor layer and the mixed crystal A selective anisotropic etching process is sequentially performed on the compound semiconductor layer so that the long sides are [011
] forming a striped mesa region in the direction, further performing a non-selective isotropic etching process to shape the mesa region into a desired shape, and then growing a semiconductor layer to bury the mesa region. A method for manufacturing a semiconductor light emitting device. 2) The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the binary compound semiconductor is an indium phosphorus compound, and the mixed crystal compound semiconductor is an indium gallium arsenide phosphorus compound or an indium gallium arsenide compound. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5972286A JPH07105550B2 (en) | 1986-03-18 | 1986-03-18 | Method for manufacturing semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5972286A JPH07105550B2 (en) | 1986-03-18 | 1986-03-18 | Method for manufacturing semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216389A true JPS62216389A (en) | 1987-09-22 |
| JPH07105550B2 JPH07105550B2 (en) | 1995-11-13 |
Family
ID=13121374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5972286A Expired - Lifetime JPH07105550B2 (en) | 1986-03-18 | 1986-03-18 | Method for manufacturing semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105550B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001144108A (en) * | 1999-11-10 | 2001-05-25 | Furukawa Electric Co Ltd:The | Manufacturing method of field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114477A (en) * | 1981-12-26 | 1983-07-07 | Fujitsu Ltd | Semiconductor light emitting device |
| JPS59152682A (en) * | 1983-02-21 | 1984-08-31 | Nippon Telegr & Teleph Corp <Ntt> | Distributed reflection type semiconductor laser |
| JPS61220489A (en) * | 1985-03-27 | 1986-09-30 | Toshiba Corp | Manufacture of semiconductor laser |
-
1986
- 1986-03-18 JP JP5972286A patent/JPH07105550B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114477A (en) * | 1981-12-26 | 1983-07-07 | Fujitsu Ltd | Semiconductor light emitting device |
| JPS59152682A (en) * | 1983-02-21 | 1984-08-31 | Nippon Telegr & Teleph Corp <Ntt> | Distributed reflection type semiconductor laser |
| JPS61220489A (en) * | 1985-03-27 | 1986-09-30 | Toshiba Corp | Manufacture of semiconductor laser |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001144108A (en) * | 1999-11-10 | 2001-05-25 | Furukawa Electric Co Ltd:The | Manufacturing method of field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07105550B2 (en) | 1995-11-13 |
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