JPS62213173A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPS62213173A
JPS62213173A JP5462486A JP5462486A JPS62213173A JP S62213173 A JPS62213173 A JP S62213173A JP 5462486 A JP5462486 A JP 5462486A JP 5462486 A JP5462486 A JP 5462486A JP S62213173 A JPS62213173 A JP S62213173A
Authority
JP
Japan
Prior art keywords
layer
gate
source
electrode
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5462486A
Other languages
Japanese (ja)
Other versions
JP2588170B2 (en
Inventor
Toshiyuki Usagawa
利幸 宇佐川
Hidekazu Okudaira
奥平　秀和
Shinichiro Takatani
信一郎 高谷
Masayoshi Kobayashi
正義 小林
Yoshinori Imamura
今村　慶憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61054624A priority Critical patent/JP2588170B2/en
Priority to DE19873706274 priority patent/DE3706274A1/en
Publication of JPS62213173A publication Critical patent/JPS62213173A/en
Priority to US07/340,471 priority patent/US5181087A/en
Priority to US07/998,856 priority patent/US5373191A/en
Application granted granted Critical
Publication of JP2588170B2 publication Critical patent/JP2588170B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66924—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To form a distance between a source and a gate with excellent controllability in 0.15mum or less by shaping a source or drain electrode and a gate electrode in a self-alignment manner. CONSTITUTION:A P<-> layer 11, an N<-> type undoped layer 12, an N-type layer 13 containing Si and an undoped N<-> type layer 18 are grown on a semi- insulating GaAs substrate 100 in succession through MBE, an undoped N<-> type layer 19 and an N<+> Ge layer 2 containing As are grown, and an Al layer 10 is formed. An element between transistors is isolated, SiO2 20 is shaped, photoresist 40 processing is conducted, SiO2 20 is removed through dry etching, using the photoresist 40 as a mask, and a taper is formed through wet etching. The source electrode 10 and the N<-> Ge layer 2 are removed selectively through dry etching, and SiN 21, 22 are applied through a photo-CVD method. SiN 22, 41 are removed, leaving the side wall 21 through an anisotropic dry etching method, and Al is deposited as a gate metal 30, thus forming an enhancement type FET through lift-off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、広い意味の電界効果型トランジスタの高性能
化に係り、特に、ソースドレイン電極とゲート電極形成
に好適な半導体装置とその製造方法に関するものである
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to improving the performance of field-effect transistors in a broad sense, and particularly relates to a semiconductor device suitable for forming source-drain electrodes and gate electrodes and a method for manufacturing the same. It is related to.

〔従来の技術〕[Conventional technology]

近年、ＭＢＥ　（分子線エピタキシ）技術。 In recent years, MBE (molecular beam epitaxy) technology.

ＭＯＣＶＤ　（有機金属熱分解法）等の超高精度の結晶
成長技術の発達により、ひ化ガリウム（ＧａＡｓ）／ア
ルミニウムひ化ガリウム（ＡＱ　Ｇ　ａ　Ａ　ｓ　）を
利用した超高速デバイス（例えば特開昭５５−１３２０
７４）が実現されつつある。Ｇ　ａ　Ａ　ｓ／　ＭＬ　
Ｇ　ａ　Ａ　ｓには良好な絶縁材料がみつけられていな
いために、金属と化合物半導体とのショットキー接合が
各種の電界効果型トランジスタ（ＦＥＴ）のゲート構造
に使われている。With the development of ultra-high-precision crystal growth techniques such as MOCVD (metal-organic pyrolysis), ultra-high-speed devices using gallium arsenide (GaAs)/aluminum gallium arsenide (AQ GaAs) (for example, 55-1320
74) is being realized. GaAs/ML
Since good insulating materials have not been found for GaAs, Schottky junctions between metals and compound semiconductors are used in gate structures of various field effect transistors (FETs).

例えば第８図に選択ドープヘテロ接合型ＦＥＴの断面図
を示す。図において、１００は半絶縁性ＧａＡｓ基板、
１１はアンドープＧａＡｓ、１２はスペーサと呼ばれる
アンドープ（不純物を故意には含まず、結果的に１０”
ａｍ−”程度のｎ一層になることが多い）ＡｌｌＧａＡ
ｓ層で膜厚をｅとすると通常６０人程度である。　１３
はｎ型Ａｌｌ　Ｇ　ａ　Ａ　ｓ層で、１４はｎ型ＧａＡ
ｓ層である。Ａｌｌ　Ｇ　ａ　Ａ　ｓ層１２．１３の膜
厚合計をｄとすると、ｄは通常５００人程程度ある。ま
た、３１はエンハンスメント型ＦＥＴ　（閾値電圧ｖｔ
ｈ〜０．ＩＶ）のゲート金属であり、３０はデプレショ
ン型ＦＥＴ（閾値電圧Ｖｔｈ〜０．８Ｖ　＋、ゲート電
圧Ｖｏ＝　ＯＶでチャネルが開いている）のゲート金属
である。For example, FIG. 8 shows a cross-sectional view of a selectively doped heterojunction FET. In the figure, 100 is a semi-insulating GaAs substrate;
11 is undoped GaAs, and 12 is an undoped spacer called a spacer (no impurity is intentionally included, resulting in 10"
(Often a single layer of n of the order of am-”) AllGaA
If the thickness of the s layer is e, the number of participants is usually about 60. 13
is an n-type All Ga As layer, and 14 is an n-type GaA layer.
It is the s layer. Letting d be the total thickness of the All Ga As layers 12 and 13, d is usually about 500. Further, 31 is an enhancement type FET (threshold voltage vt
h~0. IV), and 30 is the gate metal of a depletion type FET (threshold voltage Vth ~ 0.8 V +, channel is open at gate voltage Vo = OV).

簡単な計算からｎ型Ａａ　Ｇ　ａ　Ａ　ｓ層のドーピン
グレベルをＮＯとすると、閾値電圧Ｖｔｈは と主要項は書きくだすことができる。ここでφａｎはゲ
ートメタルとＡｆＬ　Ｇ　ａ　Ａ　ｓとのショットキー
バリア高さ、ΔＥｃはＧ　ａ　Ａ　ｓ　１１とＡｌｌａ
Ａｓ層２との伝導帯バンド端の不連続の大きさを表わし
、ｑは単位電荷、εはＡｌｌ　Ｇ　ａ　Ａ　ｓの誘電率
である。このようなＦＥＴを高性能化する場合、ソース
３２．３４とゲート３０．３１間の間隙の寄生抵抗Ｒ１
を低減することが最大の課題である。上記寄生抵抗Ｒｓ
ｓは、一般に と書き表わされる。ただしり。はソース・ゲート間距離
、Ｗはトランジスタ幅、γ。はソース電極の接触抵抗、
ρ５はソース・ゲート間部分のキャリアシート抵抗であ
る。光りソグラフィあるいは電子線リングラフィを用い
て通常形成できる最小のＬ＊、は０．５〜０．８μｍレ
ベルである。シート抵抗ρ、は１にΩ／ロ〜１００Ω／
ロ程度である。このようにシート抵抗ρ９がきわめて大
きい（Ｓｉ−ＭＯＳＦＥＴでは１〜５Ω／口程度）のが
、化合物半導体を用いるＦＥＴの場合の特徴である。こ
れは主に、化合物半導体の場合、キャリア密度の上限が
２　Ｘ　１０”　ｃｓ−３と低いことが主な原因であっ
た。一方、従来の代表的な低雑音（Ｌｏｗ　ｎｏｉｓｅ
）高周波用ＧａＡｓＭ　Ｅ　Ｓ　Ｆ　Ｅ　Ｔ　（例えば
、アイ・イー・イー・イー、　Ｅ　Ｄ２７　（１９８Ｇ
）、ｐ　１０２９参照）の断面図を第９図（ａ）、（ｂ
）に示す、第９図（ａ）において、９はｎ型Ｇ　ａ　Ａ
　ｓ能動層、１５はｎ＋（〜２　ＸＩＯ”ａｍ−”）Ｇ
ａＡｓ層で、　３０００人〜４０００人程度程度スエッ
チングによりゲート電極３０が形成されている。３２．
３３はそれぞれソース、ドレイン電極を示している。こ
の場合も、ｎ＋層は厚く形成されているが、ソース、ゲ
ート間のシート抵抗ρ１はそれぞれ１００Ω／口程度で
ある。このような事情は　ｎ　＋半導体層１５とゲート
メタル３０とを絶縁膜側壁で分離した第９図（ｂ）の構
造においても同様である。From a simple calculation, if the doping level of the n-type AaGaAs layer is NO, the main term can be written as the threshold voltage Vth. Here, φan is the Schottky barrier height between the gate metal and AfL Ga As, and ΔEc is Ga As 11 and Alla
It represents the magnitude of the discontinuity of the conduction band edge with the As layer 2, q is the unit charge, and ε is the dielectric constant of All Ga As. When improving the performance of such a FET, the parasitic resistance R1 in the gap between the source 32.34 and the gate 30.31
The biggest challenge is to reduce this. The above parasitic resistance Rs
s is generally written as. However. is the source-gate distance, W is the transistor width, and γ. is the contact resistance of the source electrode,
ρ5 is the carrier sheet resistance between the source and gate. The minimum L* that can normally be formed using photolithography or electron beam lithography is at the level of 0.5 to 0.8 μm. Sheet resistance ρ is 1 to Ω/ro to 100Ω/
It is about B. A characteristic feature of FETs using compound semiconductors is that the sheet resistance ρ9 is extremely large (approximately 1 to 5 Ω/port for Si-MOSFETs). This is mainly due to the fact that the upper limit of carrier density in compound semiconductors is as low as 2
) High frequency GaAsM E S F E T (For example, IEE, E D27 (198G
), p. 1029) are shown in FIGS. 9(a) and 9(b).
), in FIG. 9(a), 9 is n-type Ga A
s active layer, 15 is n+(~2XIO"am-")G
The gate electrode 30 is formed of an aAs layer by etching the material by about 3,000 to 4,000 steps. 32.
Reference numerals 33 indicate source and drain electrodes, respectively. In this case as well, although the n+ layer is formed to be thick, the sheet resistance ρ1 between the source and the gate is about 100Ω/gate, respectively. This situation also applies to the structure shown in FIG. 9(b) in which the n + semiconductor layer 15 and the gate metal 30 are separated by the side walls of the insulating film.

一方、電極の接触抵抗γ。は０．２Ω閣程度であり、ソ
ース、ドレイン電極金属が接するｎ”ＧａＡｓ層のドー
ピングレベルが２Ｘ１０”Ｃ！ｌ−’であることが下限
を与えていた。このようにρ８を数０７口以下にし、ま
たはγ。を０．０２ΩＩ以下にすれば、飛躍的な性能向
上を期待できる。On the other hand, the contact resistance γ of the electrode. is about 0.2Ω, and the doping level of the n"GaAs layer where the source and drain electrode metals are in contact is 2X10"C! l-' gave a lower limit. In this way, ρ8 is reduced to several 07 units or less, or γ. If it is set to 0.02ΩI or less, a dramatic improvement in performance can be expected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、ソース、ゲート間距離り。 In the above conventional technology, the distance between the source and gate is small.

が０．５μ醜以上離れてソース、ゲート間の間隔を形成
する半導体のシート抵抗が１００Ω／口程度であること
が、寄生抵抗を大きくしている主な原因であった。本発
明の目的は、ソース（またはドレイン）電極とゲート電
極とを自己整合的に形成することによって、ソース、ゲ
ート間距離Ｌ８．を０．１５μ■以下に制御性よく形成
し、ソース電極が直接接触する半導体を１０”ａｍ−’
レベルの高濃度に形成することで、電極接触抵抗γＣを
０．０２Ω叫以下にすることである。The main reason for the large parasitic resistance is that the sheet resistance of the semiconductor that forms the gap between the source and gate is about 100Ω/hole, with the source and gate separated by more than 0.5μ. An object of the present invention is to form a source (or drain) electrode and a gate electrode in a self-aligned manner so that the distance between the source and the gate is L8. 0.15μ■ or less with good controllability, and the semiconductor with which the source electrode is in direct contact is 10"am-'
The purpose is to reduce the electrode contact resistance γC to 0.02Ω or less by forming the electrode at a high concentration.

〔問題点を解決するための手段〕[Means for solving problems]

本発明における広い意味での電界効果型トランジスタの
断面構造を第７図（ａ）および（ｂ）に示す、トランジ
スタの能動層あるいはそれに準じる層１に、寄生抵抗を
低減するための高濃度（大略２　Ｘ　１０”　ａｓ−”
以上約１０”ａｍ−３まで）半導体層２が形成され、さ
らにソース、ドレイン金属１０が形成される。このとき
、上記ソース・ドレイン金属に対して、自己整合的にリ
フトオフプロセスを用いてゲート電極金属３０を形成す
ることで、上記目的を達成することができる。すなわち
、リフトオフ用絶縁物２０１例えばＣＶＤ　　Ｓｉｎ、
を全面に形成後、ゲート電極を形成するためのホトレジ
スト４０の工程を施し、ドライエツチングあるいは化学
エツチングを用い絶縁物２０、ソース・ドレイン金属１
０．高濃度半導体層２を選択的に除去し、ゲート金属が
接触する半導体層１を露出させる。つぎに光ＣＶＤ法等
の低温プロセス（ホトレジスト４０に大きな変形等の影
響を与えなければよい）を用いて、絶縁物２１および２
２を塗布する。この場合、ゲート金属を形成するりセス
空間４０の側壁に、絶縁物２１．２２を形成することが
ポイントである。つぎにドライエツチング等の方法で、
ゲートリセス部分の底４１の絶縁物２１．ホトレジスト
上の絶縁物４２を取除き、エツチング残渣を除去したの
ち、ゲート金属３０を全面に蒸着しリフトオフした。こ
のとき、リフトオフのためのスペーサはホトレジスト４
０と、スペーサ絶縁膜２０である。すなわち１本発明の
特徴は、ソース、ドレイン金属１０およびゲートホトレ
ジスト４０に対して、側壁絶縁膜２１．２２を低温プロ
セスで形成後、エツチングで側壁２１を残したままゲー
ト金属を蒸着し、リフトオフによりゲートを形成するこ
とにある。The cross-sectional structure of a field-effect transistor in a broad sense according to the present invention is shown in FIGS. 2 x 10"as-"
A semiconductor layer 2 (up to about 10" am-3) is formed, and a source/drain metal 10 is further formed. At this time, a gate electrode is formed using a lift-off process in a self-aligned manner with respect to the source/drain metal. The above object can be achieved by forming the metal 30. That is, the lift-off insulator 201 is made of, for example, CVD Sin,
After forming the photoresist 40 on the entire surface, a photoresist 40 is applied to form the gate electrode, and then the insulator 20 and source/drain metal 1 are etched using dry etching or chemical etching.
0. High concentration semiconductor layer 2 is selectively removed to expose semiconductor layer 1 with which the gate metal contacts. Next, the insulators 21 and 2 are processed using a low-temperature process such as photo-CVD (which does not have to cause large deformation or other effects on the photoresist 40).
Apply 2. In this case, the key point is to form the insulators 21 and 22 on the side walls of the recess space 40 where the gate metal is formed. Next, using methods such as dry etching,
Insulator 21 at the bottom 41 of the gate recess. After removing the insulator 42 on the photoresist and removing etching residue, a gate metal 30 was deposited on the entire surface and lifted off. At this time, the spacer for lift-off is photoresist 4
0 and a spacer insulating film 20. That is, one feature of the present invention is that after sidewall insulating films 21 and 22 are formed on the source and drain metals 10 and gate photoresist 40 by a low-temperature process, the gate metal is deposited by etching while leaving the sidewalls 21, and then the gate metal is deposited by lift-off. The purpose is to form a gate.

ソース（ドレイン）金属１０とゲート金属３０との分離
方法は、１回のゲートホトレジスト工程と。The source (drain) metal 10 and gate metal 30 are separated by one gate photoresist process.

低温絶縁膜形成方法を使う以外にも別の作成方法も可能
である。最終的な仕上り形状が第７図（ｂ）のように、
ソース（ドレイン）金属１０ゲート金属３０が側壁絶縁
膜２１を介して分離されていることが肝要である。In addition to using the low-temperature insulating film formation method, other manufacturing methods are also possible. The final finished shape is as shown in Figure 7(b),
It is important that the source (drain) metal 10 and the gate metal 30 are separated via the sidewall insulating film 21.

上記のように極限にまでソース、ゲート間隔を縮めてい
る構造は、従来構造（第８図および第９図）とは本質的
に異っているといえる。従来方法ではソース、ゲート間
距離り。を自己整合的に。It can be said that the structure in which the distance between the source and gate is reduced to the limit as described above is essentially different from the conventional structure (FIGS. 8 and 9). In the conventional method, the distance between the source and gate is small. in a self-consistent manner.

あるいはマスク合わせで形成しても、０．５μｍレベル
のＬ８が下限であった。上記のような構造が可能になっ
たのは、室温程度でカバレッジがよく形成可能な低温絶
縁物形成方法が可能になったからである。Alternatively, even if it is formed by mask alignment, the lower limit is L8 at the 0.5 μm level. The structure described above has become possible because a low-temperature insulator formation method that allows formation of good coverage at about room temperature has become possible.

〔作用〕 上記のように自己整合型側壁絶縁物形成によるソース、
ゲート電極形成により、ソース１０、ゲート３０間の距
離Ｌ０を０．１５μｍ以下にでき、ソース電極金属１０
が高濃度層２に接続しているため、接触抵抗γ。を０．
０２Ω１以下にできるようになった。[Operation] As described above, the source is formed by forming a self-aligned sidewall insulator.
By forming the gate electrode, the distance L0 between the source 10 and the gate 30 can be made 0.15 μm or less, and the source electrode metal 10
is connected to the high concentration layer 2, so the contact resistance γ. 0.
It is now possible to reduce the resistance to 02Ω1 or less.

また、側壁絶縁物２１は、ソース金属１０とゲート金属
３０を分離するために存在しているので、第７図（ｂ）
の状態でホトレジスト４０を除去後、絶縁物２１を取除
いてもよい。この場合は、その後にパッシベーション膜
を形成する必要がある。Furthermore, since the sidewall insulator 21 exists to separate the source metal 10 and the gate metal 30, as shown in FIG.
After removing the photoresist 40 in this state, the insulator 21 may be removed. In this case, it is necessary to form a passivation film after that.

光ＣＶＤの極めて低いデポジション速度（〜３０人／ｎ
＋ｉｎ）を利用すると、非常に良好な制御性でＬｓ、を
制御することが可能である。Extremely low deposition speed of photoCVD (~30 people/n
+in), it is possible to control Ls with very good controllability.

〔実施例〕〔Example〕

つぎに本発明の実施例を図面とともに説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）〜（ｃ）は本発明による半導体装置とその
製造方法の第１実施例を示す図で、２次元電子ガスをチ
ャンネル層に用いるいわゆる選択ドープヘテロ接合構造
ＦＥＴの製造工程を示す断面図、。FIGS. 1(a) to 1(c) are diagrams showing a first embodiment of a semiconductor device and its manufacturing method according to the present invention, and show the manufacturing process of a so-called selectively doped heterojunction structure FET using a two-dimensional electron gas in the channel layer. Cross section.

第２図（ａ）および（ｂ）は本発明の第２実施例を示す
製造工程を示す断面図、第３図は本発明の第３実施例を
示す断面図、第４図は本発明の第４実施例を示す断面図
、第５図（ａ）および（ｂ）は本発明の第５実施例の製
造工程を示す断面図。FIGS. 2(a) and (b) are cross-sectional views showing the manufacturing process of a second embodiment of the present invention, FIG. 3 is a cross-sectional view of a third embodiment of the present invention, and FIG. FIGS. 5(a) and 5(b) are sectional views showing the manufacturing process of the fifth embodiment of the present invention; FIGS.

第６図（ａ）〜（ｃ）は本発明の第６実施例の製造工程
を示す図、第１０図（ａ）〜（Ｑ）は本発明の第７実施
例の製造工程を示す図である。FIGS. 6(a) to (c) are diagrams showing the manufacturing process of the sixth embodiment of the present invention, and FIGS. 10(a) to (Q) are diagrams showing the manufacturing process of the seventh embodiment of the invention. be.

第１実施例 第１図（ａ）において、半絶縁性Ｇ　ａ　Ａ　ｓ基板１
００上にＭＢＥ　（分子線エピタキシ）法を用いて、ｐ
−（〜５　ＸＩＯ”Ｑｌ−３）　ＧａＡｓ層１１を１μ
ｍ成長させる。つづいてｎ−型アンドープＡｊｌｘ　Ｇ
　ａｌ−ｘ　Ａ　ｓ　（通常Ｘは０．３以上に選ばれて
いる）層１２を６０人成長させた。つぎにＳＬをｎ型不
純物として２Ｘ１０”ａＩ””含むｎ型Ａｌｌ　ｙ　Ｇ
　ａｔ　−）’　Ａ　Ｓ　（通常ｙは０．０５から０．
２５の範囲で使われている）層１３を１５０人成長させ
、セパレーション層としてアンドープｎ−型ＭｚＧａ１
−ｚＡｓ　（通常２は０．３程度で用いている）層１８
を１００人成長させた。さらに、アンドープｎ−型Ｇ　
ａ　Ａ　ｓ層１９を１００人成長させ、Ａｓを２Ｘ１０
”ロー３含有するｎ”Ｇｅ層２を３００人成長させ、超
高真空中を別室に移動させ、Ａ１層１０を３０００人形
成した。First Embodiment In FIG. 1(a), a semi-insulating GaAs substrate 1
00 using the MBE (molecular beam epitaxy) method, p
-(~5 XIO"Ql-3) GaAs layer 11 is 1μ
m grow. Next, n-type undoped Ajlx G
The layer 12 of al-x A s (usually X is selected to be 0.3 or more) was grown by 60 people. Next, an n-type Ally G containing 2X10"aI"" SL as an n-type impurity
at -)' A S (usually y is 0.05 to 0.
150 layers (used in the range of 25) were grown, and undoped n-type MzGa1 was used as a separation layer.
-zAs (usually 2 is used at about 0.3) layer 18
grew by 100 people. Furthermore, undoped n-type G
a Grow 100 s layers 19 and grow 2x10 As
The "n" Ge layer 2 containing Rho 3 was grown by 300 people, moved to a separate room in an ultra-high vacuum, and the A1 layer 10 was formed by 3000 people.

つぎにトランジスタ間の素子分離をエツチングで行い、
ゲート金属リフトオフスペーサとして、ＣＶＤ　　Ｓｉ
ｎ、２０を４０００人形成した。さらにゲートホトレジ
スト４０加工を行ったのち、ホトレジスト４０をマスク
としてドライエツチングによりＳｉ０．２０を除去した
のち、ウェットエツチングで逆台形状のテーバをつけリ
フトオフしやすくする。Next, the elements between the transistors are separated by etching.
CVD Si as gate metal lift-off spacer
n, 20 was formed by 4,000 people. Furthermore, after processing the gate photoresist 40, using the photoresist 40 as a mask, Si0.20 is removed by dry etching, and then an inverted trapezoidal taper is formed by wet etching to facilitate lift-off.

つぎにドライエツチングを用いて、ソース電極１０、ｎ
−Ｇｅ層２を選択的にエツチング除去する。その後化学
処理によってエツチング残渣を取除く。室温で光ＣＶＤ
法を用い５ｉＮ２１．２２を１０００人被着大破た。こ
の場合、絶縁物２１．２２はＳｉＮに限る必要はなく、
Ｓｉｏ、、アモルファスＳｉ等でもよい。また、Ｅ　Ｃ
Ｒ（Ｅｌｅｃｔｒｏｎ　Ｃｙｃｌｏｔｒｏｎ　Ｒｅ５ｏ
−ｎａｎｃｅ）プラズマＣＶＤ法を用いて形成してもよ
い。Next, using dry etching, the source electrodes 10, n
- selectively etching away the Ge layer 2; Etching residues are then removed by chemical treatment. PhotoCVD at room temperature
5iN21.22 was damaged by 1000 people using the method. In this case, the insulators 21 and 22 do not need to be limited to SiN,
Sio, amorphous Si, etc. may be used. Also, E C
R(Electron Cyclotron Re5o
-nance) may be formed using a plasma CVD method.

つぎに異方性ドライエツチング法を用いて側壁絶縁物２
１を残したまま、５ｉＮ２２および４１を除去し、ゲー
ト金属３０（第１図（ｃ）参照）として晟を６０００人
真空蒸着し、リフトオフする。このとき、デバイス設計
上、閾値電圧Ｖｔｈは−０，８Ｖであった。つぎにエン
ハンスメント型ＦＥＴを形成するため、同様のホトレジ
スト工程とエツチング工程を行う、前者との違いはＣＣ
ｎｚ　Ｆ　ｘ　／　Ｈｅ混合ガスＲＩＥ　（反応性イオ
ンエツチング）によりアンドープＧａＡｓ層１９も選択
的にエツチングすることである。上記のようにしてＶｔ
ｈ〜０．１ｖのエンハンスメントＦＥＴを得た。このと
きのゲート金属３１はデプレション型の時と同様に荊で
あった（第１図（Ｃ））。また、ソース、ドレイン電極
を通常のように形成するには、ホトレジスト工程を経て
選択的にＳｉｎ、２０を除去し、ソース金属１０に接続
形成すればよい。本実施例ではソース金属１０として晟
を用いた例を示したが、Ａｕ、Ｐｔ、Ｍｏ等のドライエ
ツチング加工が可能な金属で、高濃度層２とオーミック
接続できる金属であれば何でもよい。Next, the side wall insulator 2 is etched using an anisotropic dry etching method.
5iN 22 and 41 are removed while leaving 1, 6,000 layers of aluminum are vacuum-deposited as gate metal 30 (see FIG. 1(c)), and lift-off is performed. At this time, the threshold voltage Vth was −0.8 V due to device design. Next, to form an enhancement type FET, a similar photoresist process and etching process are performed.The difference from the former is CC.
The undoped GaAs layer 19 is also selectively etched by nz F x /He mixed gas RIE (reactive ion etching). As above, Vt
An enhancement FET of h~0.1v was obtained. The gate metal 31 at this time was a thorn as in the depression type (FIG. 1(C)). Further, in order to form the source and drain electrodes in the usual manner, it is sufficient to selectively remove the Sin 20 through a photoresist process and form them connected to the source metal 10. In this embodiment, an example is shown in which aluminum is used as the source metal 10, but any metal such as Au, Pt, Mo, etc. that can be subjected to dry etching process and that can be ohmically connected to the high concentration layer 2 may be used.

また、高濃度層２としてｎ”Ｇｅを例示したが、これは
必ずしも必要としない、ソース金属１ｏと能動層１８．
１９．１３．１２とオーミック接触するためのバリア半
導体の役割をするものであれば何でもよい。Further, although n''Ge is illustrated as an example of the high concentration layer 2, this is not necessarily necessary, and the source metal 1o and the active layer 18.
Any material may be used as long as it acts as a barrier semiconductor for making ohmic contact with 19.13.12.

第２実施例 第２図（ａ）、（ｂ）に示す第２実施例は、低雑音超高
周波ＧａＡｓＭ　Ｅ　Ｓ　Ｆ　Ｅ　Ｔに本発明を適用し
たものである。半絶縁性ＧａＡｓ基板１００上にＭＯＭ
ＢＥ　（ガスソース化されたＭＢＥ）を用いてアンドー
プＧ　ａ　Ａ　ｓ　１１を１ｐｍ、ＧａＡｓ／ＡｊＬＧ
ａＡｓ超格子バッファ層８，９を５０００人、さらにア
ンドープＡＱｘＧａｘ−ｘＡｓ　（ｘ　〜０．３）　１
ｇを１０００人、さらにｎ型ＧａＡｓ（ドーピングレベ
ル５　ＸＩＯ′７３−”）　　１’を５００人形成した
。つぎに高濃度（２Ｘ１０”ｃｎ−’Ａｓを含有する）
ｎ”Ｇｅ２’を形成し、さらにＴｉ／ＰｔＡｕ１Ｏを３
０００人形成しソース−ゲート容量Ｃ８ｓのフリンジン
グ容量を小さくするための絶縁膜ＣＶＤ５ｉＯ□２０を
形成した。つぎにゲートφ のホトソグラフィを行いドライエツチングを用いて、Ｓ
ｉ０．２０．Ｔｉ／Ｐｔ／Ａｕ１Ｏ１ｎ”Ｇｅ２’の各
層をドライエツチングで除去した。続いてゲートリセス
部分を第２図（ａ）に示すように通常のＣＶＤ法による
ｓｉ、Ｎ、２ａで被着させ、ドライエツチングによりゲ
ート底部と表面平坦部のＳｉ、Ｎ、２３を除去し、ゲー
ト金属としてＭｏ／Ａｕを８０００人真空蒸着しドライ
エツチング加工を用いてゲート電極を第２図（ｂ）に示
すように形成した。上記ＦＥＴは試作の結果、ソース、
ゲート間距離Ｌｓ、は０．１５μｍに、オーミック接触
抵抗γ。は０．０２Ω擲にまで低減できた。Second Embodiment The second embodiment shown in FIGS. 2(a) and 2(b) is an application of the present invention to a low-noise ultra-high frequency GaAs MESFET. MOM on semi-insulating GaAs substrate 100
Using BE (gas sourced MBE), undoped GaAs 11 was deposited at 1 pm, GaAs/AjLG
5000 layers of aAs superlattice buffer layers 8 and 9, and further undoped AQxGax-xAs (x ~ 0.3) 1
1000 g, and further 500 n-type GaAs (doping level 5
n"Ge2' and further Ti/PtAu1O 3
An insulating film CVD5iO□20 was formed to reduce the fringing capacitance of the source-gate capacitance C8s. Next, photolithography of the gate φ is performed, and dry etching is used to process the S
i0.20. Each layer of Ti/Pt/Au1O1n"Ge2' was removed by dry etching. Subsequently, the gate recess portion was coated with Si, N, and 2A by the usual CVD method as shown in FIG. 2(a), and the layers were removed by dry etching. Si, N, and 23 on the bottom and flat surface of the gate were removed, Mo/Au was vacuum-deposited as a gate metal by 8,000 vacuum evaporators, and a gate electrode was formed using dry etching as shown in FIG. 2(b). The above FET is the result of trial production, source,
The distance Ls between the gates is 0.15 μm, and the ohmic contact resistance γ. could be reduced to 0.02Ω.

第３実施例 第３図に示す第３実施例は、Ｐチャンネル選択ドープヘ
テロ接合型ＦＥＴに本発明を適用したものである。ＭＯ
−ＭＢＥを用いて半絶縁性Ｇ　ａ　Ａ　ｓ基板１００上
にｎ−（〜１０′４ｃｎ−”以下のドーピングレベル）
ＧａＡｓ層１１′を１μｍ成長させ、Ｂｅを２　Ｘ　１
０”　ａａ−”含有するＭ、Ｇａ、−ｙＡｓ　（ｙ−０
，４程度）６０を５００人形成し、はう素（Ｂ）を２Ｘ
１０”■−３含有するｐ”Ｇｅ層６１を３０００人、さ
らに別の超高真空室でＴｉ層６２を３０００人、スペー
サ用のＳｉ０２層２０を４０００人形成した（第３図）
。Third Embodiment The third embodiment shown in FIG. 3 is an example in which the present invention is applied to a P-channel selectively doped heterojunction FET. M.O.
- doping level of n- (~10'4cn-" or less) on semi-insulating GaAs substrate 100 using MBE.
A GaAs layer 11' is grown to a thickness of 1 μm, and Be is 2×1
M, Ga, -yAs (y-0
, 4) Form 500 60 and 2X
A p"Ge layer 61 containing 10"■-3 was formed by 3000 people, a Ti layer 62 was formed by 3000 people in another ultra-high vacuum chamber, and a Si02 layer 20 for a spacer was formed by 4000 people (Figure 3).
.

その後第２実施例と同様のプロセスを経て、ゲート金属
としてＭｏ／Ａｕを用い、ｐ型層６０にショットキ接続
を行った。Thereafter, through the same process as in the second embodiment, a Schottky connection was made to the p-type layer 60 using Mo/Au as the gate metal.

第４実施例 本発明を相補型選択ドープヘテロ接合型ＦＥＴに適用し
た場合の例を第４図に示す、第１実施例と同様の方法で
ｎチャンネルＦＥＴ　（第４図Ａ）を形成したのち１選
択エピタキシャル成長法を用いて、２次元正孔ガスを担
体とするＦＥＴを同図Ｂのように形成する。上記第３実
施例とは異なり正孔移動度をよくするために、ｎ−Ｍｘ
Ｇａｌ−ｘＡｓ層１２を３０人挿入している。またショ
ットキ接合の耐圧をもたせるために、アンドープｕ、Ｇ
ａ１−．Ａｓ層１８を１５０人形成している。ｎチャン
ネル／ｐチャンネル両方とも、ソース・ドレイン金属１
０および６２とゲート金属３０および３０’を接触させ
ないように、光ＣＶＤによりＳｉＮ層２１をリセス部分
に形成している。Fourth Embodiment An example in which the present invention is applied to a complementary selectively doped heterojunction FET is shown in FIG. 4. After forming an n-channel FET (FIG. 4A) in the same manner as in the first embodiment, Using a selective epitaxial growth method, an FET using a two-dimensional hole gas as a carrier is formed as shown in FIG. Unlike the third embodiment, in order to improve hole mobility, n-Mx
Thirty Gal-xAs layers 12 are inserted. In addition, in order to increase the breakdown voltage of the Schottky junction, undoped u, G
a1-. 150 people form the As layer 18. Source/drain metal 1 for both n-channel/p-channel
The SiN layer 21 is formed in the recessed portion by photo-CVD so as not to contact the gate metals 30 and 30' with the gate metals 30 and 30'.

第５実施例 高濃度半導体層としてｎ”ＧａＡｓ層を用いた場合の第
５実施例を第５（ａ）、（ｂ）に示す。半絶縁性ＧａＡ
ｓ基板１００上にＭＯＣＶＤを用いてｏ２ドープＧ　ａ
　Ａ　ｓ層１１（半絶縁性）を１μｍ形成し、さらに４
Ｘ１０１７ａｍ−”のＳｉドープＧ　ａ　Ａ　ｓ層１′
を７００人形成、２Ｘ１０”Ｃ１０−３のＳｉドープＧ
ａＡｓ層２′を３０００人形成したにち、真空蒸着法を
用いてＡｕＧｅ／　Ｎｉ／　Ａｕｔｏ’を第５図（ａ）
のように被着させる。その後、メサエッチングにより素
子間分離を行い、第１実施例と同様にしてゲート電極３
０’をＭ　ｏ　／　Ａ　ｕを用いて第５図（ｂ）のよう
に形成した。Fifth Example A fifth example in which an n'' GaAs layer is used as the highly doped semiconductor layer is shown in FIGS. 5(a) and 5(b).Semi-insulating GaAs
O2 doped Ga is formed on the s substrate 100 using MOCVD.
A 1 μm thick As layer 11 (semi-insulating) is formed, and 4
X1017am-” Si-doped GaAs layer 1'
Formed 700 people, 2X10"C10-3 Si-doped G
After forming 3,000 layers of aAs layer 2', AuGe/Ni/Auto' was deposited using vacuum evaporation method as shown in Fig. 5(a).
Apply it like this. Thereafter, device isolation is performed by mesa etching, and the gate electrode 3 is removed in the same manner as in the first embodiment.
0' was formed using Mo/Au as shown in FIG. 5(b).

第６実施例 本発明の電極形成方法をＨＢ　Ｔ　（Ｈｅｔｅｒｏ−ｊ
ｕｎｃｔｉｏｎ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏ
ｒ）のベース電極形成に適用した場合の例を、第６図（
ａ）、（ｂ）、（ｃ）に示す、半絶縁性Ｇ　ａ　Ａ　ｓ
基板１００上にＭＢＥ法を用いてＳｉを４　Ｘ　１０”
　ａｉ−”含有するｎ　”　Ｇ　ａ　Ａ　ｓ層１０１を
５０００人形成し、ＳＬを５　Ｘ　１０１０１４ａ”含
有するｎ−ＧａＡｓ１０２を４０００人、Ｂｅを２　Ｘ
　１０”　ｃｍ−’含有するｐ型ＧａＡｓ１０３　（ベ
ース層）を２０００人、ＳＬを２　Ｘ　１０１７ｃｘｎ
−’含有するｎ型ＡＩＩＸ　Ｇ　ａｚ　−Ｘ　Ａ　Ｓ　
（Ｘ　〜０．３）　１０４を４０００人、Ｓｉを５Ｘ１
０”ａｍ−’含有するｎ型Ｇ　ａ　Ａ　５１０５を４０
００人形成した。その後、ＣＶＤ　　Ｓｉｎ、膜２００
を第６図（ａ）のように被着させた。つぎに、ベース電
極形成部分だけの実施工程を第６図（ｂ）および（Ｑ）
に示す。エミッタ電極は通常行われている方法を用いて
形成し、コレクタ電極形成はベース電極形成と類似の方
法で形成できる。ベース電極形成のためのホトレジスト
２０１を１．１４被着し加工したのち、異方性ドライエ
ツチングと化学エツチングとを用いて、Ｓｉｎ、２００
、ｎ型ＧａＡｓ１０４、ｎ型ＡｕＧａＡｓ１０３を除去
した。基板温度１２０℃で光ＣＶＤ法を用いＳｉＮ膜２
０３および２０４を第６図（ｂ）に示すように２０００
人形成した。Sixth Example The electrode forming method of the present invention was applied to HBT (Hetero-j
unction Bipolar Transistor
An example of application to the base electrode formation of r) is shown in Figure 6 (
Semi-insulating Ga As shown in a), (b), and (c)
4 x 10” Si is deposited on the substrate 100 using the MBE method.
5,000 layers of n-GaAs layer 101 containing SL, 4,000 layers of n-GaAs 102 containing SL, and 2× Be.
2000 p-type GaAs103 (base layer) containing 10"cm-', 2 x 1017cxn SL
-'containing n-type AIIX G az -X A S
(X ~0.3) 104 for 4000 people, Si for 5X1
40% of n-type Ga A 5105 containing 0"am-'
00 people formed. After that, CVD Sin, film 200
was applied as shown in FIG. 6(a). Next, the implementation process of only the base electrode forming part is shown in Fig. 6(b) and (Q).
Shown below. The emitter electrode can be formed using a commonly used method, and the collector electrode can be formed using a method similar to that for forming the base electrode. After 1.14 coats of photoresist 201 for forming the base electrode and processing, anisotropic dry etching and chemical etching were used to form a 200mm photoresist.
, n-type GaAs 104, and n-type AuGaAs 103 were removed. SiN film 2 was formed using the photo-CVD method at a substrate temperature of 120°C.
03 and 204 as shown in Figure 6(b).
Formed a person.

つづいて異方性ドライエツチングにより側壁に形成され
た光ＣＶＤのＳｉＮ膜２０４を残し、その他の部分を削
除し、さらにベース電極金属２０５を蒸着し、第６図（
ｃ）のようにリフトオフした。上記ベース電極金属とし
てはＡｕ　　Ｚｎ合金を用いた。Next, the photo-CVD SiN film 204 formed on the side wall by anisotropic dry etching is left, the other parts are removed, and the base electrode metal 205 is deposited, as shown in FIG.
Lift-off was performed as in c). An AuZn alloy was used as the base electrode metal.

アロイ温度４５０℃２分間の条件でオーミック電極とし
た。An ohmic electrode was formed under the conditions that the alloy temperature was 450° C. for 2 minutes.

上記のように、側壁に残した光ＣＶＤの５ｉＮ２０４は
電気的絶縁性に劣るため、電極形成後、１／１００に薄
めたふっ酸を用いて除去し、改めてプラズマＣＶＤ等を
用い、新しいパッシベーション膜を形成してもよい。ま
た、本発明の場合、形成電極と絶縁膜で電気的に分離さ
れた半導体層との間隙をすべて絶縁物で埋めると、寄生
容量が大きくなるという問題が生じる。したがって、形
成電極と側壁絶縁膜との間を隙間で構成すると、寄生容
量の増加を抑えることができる。As mentioned above, the photo-CVD 5iN204 left on the side wall has poor electrical insulation, so after electrode formation, it is removed using hydrofluoric acid diluted to 1/100, and then a new passivation film is formed using plasma CVD, etc. may be formed. Furthermore, in the case of the present invention, if all the gaps between the forming electrode and the semiconductor layer electrically separated by the insulating film are filled with an insulating material, a problem arises in that parasitic capacitance increases. Therefore, if a gap is formed between the formed electrode and the sidewall insulating film, an increase in parasitic capacitance can be suppressed.

第７実施例 イオン注入法によるＧａＡｓＭ　Ｅ　Ｓ　Ｆ　Ｅ　Ｔ作
成に、本発明を用いた実施例を第１０図に示す。ｎ型Ｇ
ａＡｓ領域７１．ｎ＋ソース・ドレイン領域７０、ソー
ス・ドレイン電極３２．３３、スペーサ絶縁膜７２を形
成後。Seventh Embodiment FIG. 10 shows an embodiment in which the present invention was used to fabricate a GaAsM ESFET by ion implantation. n-type G
aAs region 71. After forming the n+ source/drain region 70, source/drain electrodes 32, 33, and spacer insulating film 72.

ゲート形成のホトレジスト７３を第１０図（ａ）のよう
に形成する。つぎに１２０℃基板温度で光ＣＶＤにより
５ｉＮ２２を３０００人被着在世る。（第１０図（ｂ）
）。異方性ドライエツチング方法を用いて、本発明のよ
うに側壁絶縁膜２２を残してリフトオフによりゲート電
極３０を形成する。光ＣＶＤ膜は被着速度が遅い（２ｎ
ｍ／分〜１０ｎＩＩ／分）ため、側壁絶縁膜は非常に制
御性よく制御できる。A photoresist 73 for forming a gate is formed as shown in FIG. 10(a). Next, 3,000 layers of 5iN22 were deposited by photo-CVD at a substrate temperature of 120°C. (Figure 10(b)
). Using an anisotropic dry etching method, the gate electrode 30 is formed by lift-off, leaving the sidewall insulating film 22 as in the present invention. Photo-CVD film has a slow deposition speed (2n
m/min to 10 nII/min), the sidewall insulating film can be controlled with very good controllability.

本実施例の場合、第１０図（ａ）のゲートホトレジスト
の開口距離は０．８ｔ１ｍであり、側壁光ＣＶＤのＳｉ
Ｎの膜厚は３０００人であったから、できあがりのゲー
ト長（第１０図（Ｃ））は０．４４であった。In the case of this example, the opening distance of the gate photoresist in FIG. 10(a) is 0.8t1m, and the Si
Since the thickness of the N film was 3000, the finished gate length (FIG. 10(C)) was 0.44.

このように本発明は、サブミクロンＦＥＴの作成にも極
めて敵したプロセスということができる。Thus, the present invention can be said to be a process that is extremely suitable for manufacturing submicron FETs.

〔発明の効果〕〔Effect of the invention〕

上記のように本発明による半導体装置とその製造方法は
、少なくとも１種類の能動層もしくは電気的に活性な層
の下位に位置する能動層またはこれに準じる層に、電子
的に接続する１回のホトレジスト工程で形成された電極
金属が、上記少なくとも１種類の能動層もしくは電気的
に活性な層と、側壁絶縁物を介して分離形成されている
ことにより、第１の電極金属と第２の電極金属との間隔
０．１５．以下に極めて制御性よく制御でき、また、能
動層と電極金属との間に極めて高濃度のバリア半導体層
を挿入しているので、接触抵抗γ。とじては０．０２Ω
ａｍ以下とすることができた。このように本発明によれ
ば、ＦＥＴにおけるソース・ゲート間の抵抗を極限にま
で下げることができるので、トランジスタ性能の大幅な
向上を実現することができる。しかも光ＣＶＤ等による
室温〜１００℃の低温プロセスを用いたリセスゲートの
側壁形成が。As described above, the semiconductor device and the manufacturing method thereof according to the present invention provide a single step of electronically connecting at least one type of active layer or an active layer located below an electrically active layer, or a layer similar thereto. The electrode metal formed by the photoresist process is separated from the at least one type of active layer or electrically active layer via the sidewall insulator, so that the first electrode metal and the second electrode Distance from metal 0.15. The contact resistance γ can be controlled with extremely good controllability, and since a barrier semiconductor layer with an extremely high concentration is inserted between the active layer and the electrode metal, the contact resistance γ. 0.02Ω at the end
am or less. As described above, according to the present invention, the resistance between the source and gate of the FET can be lowered to the utmost limit, and therefore, the transistor performance can be significantly improved. Moreover, the side walls of the recessed gate can be formed using a low temperature process of room temperature to 100° C. using photo-CVD or the like.

１回のホトレジスト工程だけで済み、ゲートのオーバハ
ングによるフリンジング容量の問題は全くないという効
果が得られる。Only one photoresist process is required, and there is no problem of fringing capacitance due to gate overhang.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（Ｑ）は本発明による半導体装置の第１
実施例における製造工程を示す図、第２図（ａ）および
（ｂ）は本発明の第２実施例を示す製造工程図、第３図
は本発明の第３実施例を示す断面図、第４図は本発明の
第４実施例を示す断面図、第５図（ａ）および（ｂ）は
本発明の第５実施例の製造工程を示す断面図、第６図（
ａ）〜（ｃ）は本発明の第６実施例の製造工程を示す断
面図、第７図（ａ）および（ｂ）はそれぞれ本発明の詳
細な説明する断面図、第８図および第９図（ａ）、（ｂ
）は従来の電界効果トランジスタのソース・ゲートをそ
れぞれ説明するための図、第１０図（ａ）〜（ｃ）は本
発明の第７実施例を示す図である。 ２．２’、２’、６１・・・高濃度半導体層１０．６２
・・・ソース・ドレイン電極金属１２．１３．１８．１
９・・・能動層 ２１．２２．２３・・・側壁絶縁物 ３０．３０’　、　３１・・・リセスゲート金属代理人
弁理士　　中　村　純之助 才１　図 や２図 （Ｑ） ｔ３図 ？６顔 （ａ）　　　　　　　　　　（ｂ） （Ｃ） ？７図FIGS. 1(a) to (Q) show the first part of the semiconductor device according to the present invention.
2(a) and (b) are manufacturing process diagrams showing the second embodiment of the present invention. FIG. 3 is a sectional view showing the third embodiment of the present invention. 4 is a cross-sectional view showing the fourth embodiment of the present invention, FIGS. 5(a) and (b) are cross-sectional views showing the manufacturing process of the fifth embodiment of the present invention, and FIG.
a) to (c) are cross-sectional views showing the manufacturing process of the sixth embodiment of the present invention, FIGS. 7(a) and (b) are cross-sectional views explaining details of the present invention, and FIGS. 8 and 9. Figures (a), (b)
) are diagrams for explaining the source and gate of a conventional field effect transistor, respectively, and FIGS. 10(a) to (c) are diagrams showing a seventh embodiment of the present invention. 2.2', 2', 61...high concentration semiconductor layer 10.62
...Source/drain electrode metal 12.13.18.1
9...Active layer 21.22.23...Side wall insulator 30.30', 31...Recess gate metal agent Junnosuke Nakamura 1 Figure and 2 (Q) t3 diagram? 6 faces (a) (b) (C)? Figure 7

Claims (1)

【特許請求の範囲】 １、少なくとも１種類の能動層もしくは電気的に活性な
層の下位に位置する能動層またはこれに準じる層に、電
子的に接続する１回のホトレジスト工程で形成された電
極金属が、上記少なくとも１種類の能動層もしくは電気
的に活性な層と、側壁絶縁物を介して分離形成されてい
る半導体装置。 ２、上記電極金属は、上記能動層またはこれに準じる層
との間に、高濃度（２×１０＾１＾８ｃｍ＾３以上）の
半導体層が挿入されていることを特徴とする特許請求の
範囲第１項に記載した半導体装置。 ３、能動層またはこれに準じる層上に形成した第１の電
極金属あるいは高濃度半導体層に対し、１回の第２電極
形成のホトレジスト工程だけを行い、上記第１の電極金
属あるいは高濃度半導体層を選択的に除去したのち、光
ＣＶＤ等のホトレジストに大きな変形を加えない程度の
低温プロセスを用いて、側壁絶縁物を被着し、異方性エ
ッチング等でリセスされた上記側壁絶縁物を残してホト
レジスト上の絶縁物を除き、上記第２電極金属を蒸着リ
フトオフする工程を有する半導体装置の製造方法。[Claims] 1. An electrode formed in a single photoresist step that is electronically connected to at least one active layer or an active layer located below the electrically active layer, or a layer similar thereto; A semiconductor device in which a metal is formed separately from the at least one type of active layer or electrically active layer via a sidewall insulator. 2. A semiconductor layer with a high concentration (2×10^1^8 cm^3 or more) is inserted between the electrode metal and the active layer or a layer similar thereto. A semiconductor device described in scope 1. 3. Perform only one photoresist process for forming the second electrode on the first electrode metal or high concentration semiconductor layer formed on the active layer or a layer similar thereto, and remove the first electrode metal or high concentration semiconductor layer. After selectively removing the layer, a sidewall insulator is deposited using a low temperature process such as photo-CVD that does not significantly deform the photoresist, and the sidewall insulator is recessed by anisotropic etching or the like. A method for manufacturing a semiconductor device, comprising the step of removing the insulator on the photoresist and lifting off the second electrode metal by vapor deposition.
JP61054624A 1986-02-28 1986-03-14 Method for manufacturing semiconductor device Expired - Lifetime JP2588170B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP61054624A JP2588170B2 (en) 1986-03-14 1986-03-14 Method for manufacturing semiconductor device
DE19873706274 DE3706274A1 (en) 1986-02-28 1987-02-26 Semiconductor component and method of fabricating it
US07/340,471 US5181087A (en) 1986-02-28 1989-04-19 Semiconductor device and method of producing the same
US07/998,856 US5373191A (en) 1986-02-28 1992-12-30 Semiconductor device and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61054624A JP2588170B2 (en) 1986-03-14 1986-03-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62213173A true JPS62213173A (en) 1987-09-19
JP2588170B2 JP2588170B2 (en) 1997-03-05

Family

ID=12975897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61054624A Expired - Lifetime JP2588170B2 (en) 1986-02-28 1986-03-14 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2588170B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012775A (en) * 1983-07-02 1985-01-23 Agency Of Ind Science & Technol Field effect transistor
JPS60231368A (en) * 1984-05-01 1985-11-16 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS60251671A (en) * 1984-05-29 1985-12-12 Fujitsu Ltd Field-effect type transistor and manufacture thereof
JPS6124265A (en) * 1984-07-13 1986-02-01 Fujitsu Ltd Manufacture of semiconductor device
JPS6232661A (en) * 1985-08-05 1987-02-12 Nippon Telegr & Teleph Corp <Ntt> Manufacture of field effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012775A (en) * 1983-07-02 1985-01-23 Agency Of Ind Science & Technol Field effect transistor
JPS60231368A (en) * 1984-05-01 1985-11-16 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS60251671A (en) * 1984-05-29 1985-12-12 Fujitsu Ltd Field-effect type transistor and manufacture thereof
JPS6124265A (en) * 1984-07-13 1986-02-01 Fujitsu Ltd Manufacture of semiconductor device
JPS6232661A (en) * 1985-08-05 1987-02-12 Nippon Telegr & Teleph Corp <Ntt> Manufacture of field effect transistor

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