JPS62211935A - Formation of interconnection layer - Google Patents
Formation of interconnection layerInfo
- Publication number
- JPS62211935A JPS62211935A JP5531386A JP5531386A JPS62211935A JP S62211935 A JPS62211935 A JP S62211935A JP 5531386 A JP5531386 A JP 5531386A JP 5531386 A JP5531386 A JP 5531386A JP S62211935 A JPS62211935 A JP S62211935A
- Authority
- JP
- Japan
- Prior art keywords
- interconnection layer
- wiring layer
- substrate
- insulating film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 3
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 239000004411 aluminium Substances 0.000 abstract 2
- 235000011007 phosphoric acid Nutrition 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003353 gold alloy Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔４既要〕
配線層をパターン上面グした状態では、配線層のパター
ン上面の縁部には鋭利なる角が形成される。この状態で
バノシヘーション膜あるいは層間絶縁膜を積層すると、
Ａ１層にはストレスによるボイドを発生して配線層の信
転性を低下する。本発明では絶縁膜を積層する前にウニ
ッｉ・処理により角を丸めて改善を行った。DETAILED DESCRIPTION OF THE INVENTION [4 Already Required] When the wiring layer is placed on top of the pattern, sharp corners are formed at the edges of the wiring layer on the top surface of the pattern. If a banoshihesion film or interlayer insulation film is laminated in this state,
Voids are generated in the A1 layer due to stress, reducing the reliability of the wiring layer. In the present invention, an improvement was made by rounding the corners using a uni-treatment process before laminating the insulating film.
〔産業」−の利用分ｑ′、： ’１
本発明は、Ａｐ配線層を形成後、パッジ・・、−ンヨン
膜あるいは層間絶縁）漠の積層前の処理法に関する。[Industry] Utilization q',: '1 The present invention relates to a processing method after forming an Ap wiring layer and before forming a padding film or an interlayer insulation layer.
ＡＮ配線層の形成の終わった基板には、通常その上にＰ
ＳＧ膜または５ｊ３Ｎ４膜、あるいはＩ） ＳＧ膜と５
ｉ３Ｎ、膜の２層積層膜等の絶縁膜が被着される。以下
本発明では」二記配線層上の積層を絶縁膜と総称する。After the AN wiring layer has been formed, P is usually placed on the substrate.
SG film or 5j3N4 film, or I) SG film and 5
An insulating film, such as a two-layer stack of i3N, films, is deposited. Hereinafter, in the present invention, the laminated layer on the wiring layer 2 will be collectively referred to as an insulating film.
本発明は絶縁膜の被着前にウニソ１〜処理ブ１」セスを
加えて配線層のボイドの問題の対策を行った。In the present invention, the problem of voids in the wiring layer is solved by adding a 1 to 1 process process before depositing the insulating film.
△ｌ配線層の材料としては、純Ａβのみてなくコンタク
ト特性、スパイク、突起による絶縁破壊、断線等の不良
を防止するためＡβ合金が多く用いられている。As a material for the Δl wiring layer, not only pure Aβ but also an Aβ alloy is often used in order to improve contact characteristics and prevent defects such as dielectric breakdown and disconnection due to spikes and protrusions.
１〜３％Ｓｉ、４％以下のＣｕ、１％以ドのＵ’ ｉ
。1 to 3% Si, 4% or less Cu, 1% or more U' i
.
Ｗ、Ｍｏ等を含んだＡＡ金合金あるいはこれらの金属を
複数含んだ合金として用いられる。It is used as an AA gold alloy containing W, Mo, etc. or an alloy containing multiple of these metals.
これらのＡｐ金合金集積回路の構造、プロセス、使用条
件等により使い分けられている。These Ap gold alloy integrated circuits are used depending on the structure, process, usage conditions, etc.
配線層の形成は、上記の金属材料を真空蒸着、あるいは
スパツタリングにより基板−トに積層されリソグラフィ
工程に送られる。The wiring layer is formed by laminating the above-mentioned metal material on a substrate by vacuum evaporation or sputtering, and then sending it to a lithography process.
レジストを塗布して配線層パターンのレジストを残して
他の領域のレジストをパターンニング除去する。A resist is applied, and the resist in other areas is removed by patterning, leaving the resist in the wiring layer pattern.
１、・讐出せるＡｌ層をエツチングで除去し、最後に配
線層１−のレジスト膜を除去して配線層が形成される。1. The exposed Al layer is removed by etching, and finally the resist film of wiring layer 1- is removed to form a wiring layer.
」−記に述べた従来の技術による配線層の形成力法では
、パターンニングされた配線層の断面は理論的には第２
図の如き形状を示す。In the conventional wiring layer forming force method described in ``--, the cross section of the patterned wiring layer is theoretically
It shows the shape as shown in the figure.
前工程の終わった基板５の」二に形成された配線層１に
は、上面の縁部にシャープな角２が形成される。A sharp corner 2 is formed at the edge of the upper surface of the wiring layer 1 formed on the second side of the substrate 5 after the previous process.
その後の工程で配線層上に絶縁膜３が積層されると、絶
縁膜と配線層との間にストし・スが発イ］−するが、こ
のストレスは上記の配線層−１−■の縁部角に集中する
。When the insulating film 3 is laminated on the wiring layer in the subsequent process, stress is generated between the insulating film and the wiring layer. Concentrate on edge corners.
このため配線層の角が食われてボイド４ （点線で示す
）を発生し、実質的な配線層の断面積の減少を来たし、
断線等の不良の原因となる。As a result, the corners of the wiring layer are eaten away, creating voids 4 (indicated by dotted lines), resulting in a substantial reduction in the cross-sectional area of the wiring layer.
This may cause defects such as wire breakage.
上記問題点は、Ａ１あるいはＡβ合金よりなる配線層を
形成せる基板に、パッシベーション膜あるいは層間絶縁
膜等の絶縁膜を積層するに当たり、該配線層の上面の縁
部角をウェット処理により除去することよりなる本発明
の配線層の形成方法によって解決される。The above problem is that when laminating an insulating film such as a passivation film or an interlayer insulating film on a substrate on which a wiring layer made of A1 or Aβ alloy is formed, the edge corners of the upper surface of the wiring layer must be removed by wet processing. This problem is solved by the wiring layer forming method of the present invention.
本発明の方法は配線層上に絶縁膜を積層する前に、ウェ
ット処理することにより配線層のソヤープな角を除去し
て丸く滑らかにするもので、これにより絶縁膜よりのス
トレスが配線層の一部に集中するのを防止し、ボイドの
発生を無くずものである。In the method of the present invention, before laminating an insulating film on the wiring layer, wet processing is performed to remove sharp corners of the wiring layer and make the wiring layer round and smooth. It prevents the particles from concentrating on one part and eliminates the generation of voids.
本発明の配線層の縁部角を丸めるエツチング溶液は、硝
酸ＨＮ Ｏ３あるいは燐酸Ｈ、ＩＰ Ｏａ等の酸を含む
希釈溶液が用いられる。As the etching solution for rounding the edge corners of the wiring layer of the present invention, a dilute solution containing an acid such as nitric acid HN O3, phosphoric acid H, or IP Oa is used.
一例としてＨＮＯ３を用いる場合、水で約２０倍に希釈
した溶液を使用して約３０秒間基板をディップするごと
により、はぼ第１図（ａ＋→ｆｂｌの如く基板５」二に
形成された配線層１の上面の縁部角２は丸く除去される
。As an example, when using HNO3, by dipping the substrate for about 30 seconds using a solution diluted about 20 times with water, the wiring formed on the substrate 5''2 as shown in Figure 1 (a+→fbl) The edge corners 2 of the upper surface of layer 1 are rounded off.
以上に説明せるごとく本発明のウェット処理を配線層に
適用することにより、その後のパッシベーション膜ある
いは層間絶縁膜の積層に当たり、配線層に対する応力の
集中が阻止され、その結果ボイドの発生は著しく緩和さ
れて配線層の信頼性向」二に寄与する。As explained above, by applying the wet treatment of the present invention to the wiring layer, stress concentration on the wiring layer is prevented during the subsequent lamination of the passivation film or interlayer insulating film, and as a result, the occurrence of voids is significantly alleviated. This contributes to the reliability of the wiring layer.
第１図（ａｌ、 （ｂｌば本発明のウェット処理の１１
１後の配線層の断面形状を説明する図、
第２図は配線層のパターンニングにより形成される縁部
角の形状を説明する図、
を示す。
図面において、
１は配線層、
２は縁部角、
３ば絶縁膜、
４はボイド、
５は基板、
をそれぞれ示す。FIG. 1 (al, (bl) shows 11 of wet treatment of the present invention.
FIG. 2 is a diagram illustrating the cross-sectional shape of the wiring layer after patterning. FIG. 2 is a diagram illustrating the shape of the edge corner formed by patterning the wiring layer. In the drawings, 1 is a wiring layer, 2 is an edge corner, 3 is an insulating film, 4 is a void, and 5 is a substrate.
Claims (1)
る基板（５）にパッシベーション膜あるいは層間絶縁膜
等の絶縁膜（３）を積層するに当たり、該配線層の上面
の縁部角（２）をウェット処理により除去することを特
徴とする配線層の形成方法。When laminating an insulating film (3) such as a passivation film or an interlayer insulating film on a substrate (5) on which a wiring layer (1) made of Al or Al alloy is formed, the edge corner (2) of the upper surface of the wiring layer is A method for forming a wiring layer, characterized in that it is removed by wet processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5531386A JPS62211935A (en) | 1986-03-12 | 1986-03-12 | Formation of interconnection layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5531386A JPS62211935A (en) | 1986-03-12 | 1986-03-12 | Formation of interconnection layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62211935A true JPS62211935A (en) | 1987-09-17 |
Family
ID=12995067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5531386A Pending JPS62211935A (en) | 1986-03-12 | 1986-03-12 | Formation of interconnection layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62211935A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008004820A (en) * | 2006-06-23 | 2008-01-10 | Taiyo Ink Mfg Ltd | Printed circuit board and manufacturing method therefor |
| US8124226B2 (en) | 2006-09-12 | 2012-02-28 | Sri International | Flexible circuits |
| JP2013191711A (en) * | 2012-03-13 | 2013-09-26 | Sumitomo Metal Mining Co Ltd | Three-dimensional circuit board, method of manufacturing film-like circuit board, and method of manufacturing three-dimensional circuit board using the same |
| US8628818B1 (en) * | 2007-06-21 | 2014-01-14 | Sri International | Conductive pattern formation |
| US8895874B1 (en) | 2009-03-10 | 2014-11-25 | Averatek Corp. | Indium-less transparent metalized layers |
-
1986
- 1986-03-12 JP JP5531386A patent/JPS62211935A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008004820A (en) * | 2006-06-23 | 2008-01-10 | Taiyo Ink Mfg Ltd | Printed circuit board and manufacturing method therefor |
| JP4664242B2 (en) * | 2006-06-23 | 2011-04-06 | 太陽ホールディングス株式会社 | Printed wiring board and manufacturing method thereof |
| US8124226B2 (en) | 2006-09-12 | 2012-02-28 | Sri International | Flexible circuits |
| US8911608B1 (en) | 2006-09-12 | 2014-12-16 | Sri International | Flexible circuit formation |
| US8628818B1 (en) * | 2007-06-21 | 2014-01-14 | Sri International | Conductive pattern formation |
| US8895874B1 (en) | 2009-03-10 | 2014-11-25 | Averatek Corp. | Indium-less transparent metalized layers |
| JP2013191711A (en) * | 2012-03-13 | 2013-09-26 | Sumitomo Metal Mining Co Ltd | Three-dimensional circuit board, method of manufacturing film-like circuit board, and method of manufacturing three-dimensional circuit board using the same |
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