JPH0319222A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0319222A JPH0319222A JP15346089A JP15346089A JPH0319222A JP H0319222 A JPH0319222 A JP H0319222A JP 15346089 A JP15346089 A JP 15346089A JP 15346089 A JP15346089 A JP 15346089A JP H0319222 A JPH0319222 A JP H0319222A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- semiconductor device
- oxide film
- hydrofluoric acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- 239000010937 tungsten Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000013508 migration Methods 0.000 abstract description 2
- 230000005012 migration Effects 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 239000011733 molybdenum Substances 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 2
- 229910018520 Al—Si Inorganic materials 0.000 abstract 2
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はヴアイアホールのコンタクト形成に係る半導体
装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device relating to the formation of a contact via a via hole.
従来の技術
半導体装置の製造に訃いて多層配線が広く用いられてい
るが、アルミあるいはアｐミ合金の層間でコンタクトを
とる場合、下層の配線形成後のシンターあるいは層間絶
縁膜形成時あるいはウ゛アイアホーμをドライエッチに
よｂ形戒する際に、下層アノレミ配線上面に酸化アノレ
ミが或長する。同状態のす１で上層配線となるアノレミ
合金膜を被着した場合、上記の酸化アノレミが絶縁性を
有することから層間抵抗が増加し、良好なコンタクト形
成が不可能となる。従来、上記問題を解決するためには
上層のアルミ合金膜を被着する直前に、スパソタリング
装置内にかいて、希ガス雰囲気中で半導体基板に高周波
電力を印加し、希ガスプラズマイオンによるスパッタリ
ングによって上記表面酸化膜の除去を行なっている。Conventional technology Multi-layer wiring is widely used in the manufacture of semiconductor devices, but when making contact between layers of aluminum or aluminum alloy, sintering after forming the lower layer wiring, forming an interlayer insulating film, or wiping the wire holes is necessary. When the B-type is formed by dry etching, an oxidized anoremi is formed on the upper surface of the lower anoremi wiring. When an anoremi alloy film is deposited to form the upper layer wiring in the same state, the interlayer resistance increases because the oxidized anorem has insulating properties, making it impossible to form a good contact. Conventionally, in order to solve the above problem, immediately before depositing the upper aluminum alloy film, high frequency power was applied to the semiconductor substrate in a rare gas atmosphere in a spa sotering device, and sputtering with rare gas plasma ions was applied. The surface oxide film mentioned above is being removed.
発明が解決しようとする課題
しかしながら従来の方法によった場合、半導体基板に高
周波が印加されイオンが入射する事から、チャージアッ
プが発生しやすく、トランジスタのスレッシｇ／レド電
圧の移動など、半導体装置の特性劣化、ひいては歩留低
下を起こす要因となっている。Problems to be Solved by the Invention However, when using the conventional method, charge-up is likely to occur due to the application of high frequency waves to the semiconductor substrate and the incidence of ions, resulting in problems such as shifting of the threshold g/redo voltage of the transistor, etc. This is a factor that causes deterioration of the characteristics of the product and, ultimately, a decrease in yield.
課題を解決するための手段
上記問題を解決するために、本発明においては下層配線
を二層構造とし、上記のプラズマ中での高周波印加のか
わジにウエットエッチによる酸化膜除去工程を備えてい
る。Means for Solving the Problems In order to solve the above problems, in the present invention, the lower layer wiring has a two-layer structure, and an oxide film removal process by wet etching is provided in place of the high frequency application in the plasma. .
作 用
下層配線の上面にシリサイドを．用いる事により、以後
の層間絶縁膜形成時の配線上面の酸化膜或長が抑制され
るとともに、同材料の酸化物はアμミ酸化物と比較して
ウエットエッチングでの制御性が良好であるため、第二
の配線材料を被着する際にウエットエッチによる酸化膜
除去が容易になシ、かつ配線間のアノレミ原子の相互拡
散を防止する為、信頼性の高いコンタクトの形成が可能
となる。Silicide is applied to the upper surface of the lower layer wiring. By using this material, the length of the oxide film on the top surface of the wiring is suppressed during the subsequent formation of an interlayer insulating film, and the oxide of the same material has better controllability in wet etching compared to aluminum oxide. This makes it easy to remove the oxide film by wet etching when depositing the second wiring material, and prevents interdiffusion of anoremi atoms between wirings, making it possible to form highly reliable contacts. .
実施例 第１図は本発明の実施例を示す概略図である。Example FIG. 1 is a schematic diagram showing an embodiment of the present invention.
所定のゲート，キャパシタなどを形成した半導体装置基
板に、第一の配線・を例えばＡｌ−ＳｔをＯ．ａμｍの
厚さにヌパッタ法により被着した後に連続してモリブデ
ンシリタイトを０．１μｍの厚さに被着する。さらに所
定の配線パターンをフオリソグラフィーにより形成し、
第１図ａに示すようにドライエッチを施し第一の配線を
形戊する。熱処理の後にプラズマＣＶＤ法によう酸化膜
を０．６〜０．８μｍの厚さに形戒し層間絶縁膜とする
（第１図ｂ）。フォトレジストのパターニングドライエ
ッチによりバイアホールを形成した後（第１図Ｃ）に、
１０：１〜２０：１の緩衝フッ酸液にて２０秒程度ウエ
シトエッチし、上記シリサイド層の一部を除去した後に
、第１図ｄに示すように第二の配線となるＡｌ〜Ｓｔ膜
を被着する。A first wiring layer, for example, made of Al-St, is formed on a semiconductor device substrate on which predetermined gates, capacitors, etc. After depositing to a thickness of 1 μm by the Nupatta method, molybdenum silitite is continuously deposited to a thickness of 0.1 μm. Furthermore, a predetermined wiring pattern is formed by foliography,
As shown in FIG. 1a, dry etching is performed to form the first wiring. After the heat treatment, the oxide film is formed to a thickness of 0.6 to 0.8 μm using plasma CVD to form an interlayer insulating film (FIG. 1b). After forming via holes by patterning and dry etching the photoresist (Fig. 1C),
After removing a part of the silicide layer by etching with a buffered hydrofluoric acid solution of 10:1 to 20:1 for about 20 seconds, an Al to St film, which will become the second wiring, is etched as shown in Figure 1d. to adhere to.
発明の効果
以上説明した様に本発明によれば、従来法と比較してス
トレヌマイグレーションなどの信頼性が高く、特性劣化
のない半導体装置の製造が容易であシ、多大な効果が予
想される。Effects of the Invention As explained above, according to the present invention, compared to conventional methods, it is easy to manufacture semiconductor devices with high reliability such as strain migration and no deterioration of characteristics, and great effects are expected. Ru.
第１図は本発明の実施例を示す概略図である。
１・・・・・・半導体装置基板、２・・・・・・第一の
Ａｌ−Ｓｔ層、３・・・・・・第一のシリサイド層、４
・・・・・・酸化膜（層間絶縁膜）、５・・・・・・パ
イアホール、６・・・・・・第二〇Ａｌ−Ｓｉ０FIG. 1 is a schematic diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor device substrate, 2... First Al-St layer, 3... First silicide layer, 4
... Oxide film (interlayer insulating film), 5 ... Pier hole, 6 ... No. 20 Al-Si0
Claims (1)
はシリサイドから成る上層とアルミまたはアルミ合金か
ら成る下層で構成され、所定の層間絶縁膜を形成後にフ
ォトリソグラフィ及びエッチングによりバイアホールを
形成する工程を経て、第二のアルミあるいはアルミ合金
から成る配線層を形成する際に、緩衝フッ酸液により第
一の配線のタングステンあるいはシリサイド層の膜厚の
一部を除去した後に、上記第二の配線膜を被着する事を
特徴とする半導体装置の製造方法。In a semiconductor device, the first wiring layer is composed of an upper layer made of tungsten or silicide and a lower layer made of aluminum or aluminum alloy. When forming the second wiring layer made of aluminum or aluminum alloy, after removing part of the thickness of the tungsten or silicide layer of the first wiring with a buffered hydrofluoric acid solution, the second wiring film is applied. A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15346089A JPH0319222A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15346089A JPH0319222A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319222A true JPH0319222A (en) | 1991-01-28 |
Family
ID=15563044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15346089A Pending JPH0319222A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319222A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04307957A (en) * | 1991-04-05 | 1992-10-30 | Mitsubishi Electric Corp | Wiring connection structure of semiconductor device and manufacture thereof |
| JP2003527743A (en) * | 1999-10-18 | 2003-09-16 | インフィニオン テクノロジーズ ノース アメリカ コーポレイション | Self-aligned metal cap for interlayer metal connection |
-
1989
- 1989-06-15 JP JP15346089A patent/JPH0319222A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04307957A (en) * | 1991-04-05 | 1992-10-30 | Mitsubishi Electric Corp | Wiring connection structure of semiconductor device and manufacture thereof |
| JP2003527743A (en) * | 1999-10-18 | 2003-09-16 | インフィニオン テクノロジーズ ノース アメリカ コーポレイション | Self-aligned metal cap for interlayer metal connection |
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