JPS62209872A - Photoelectric conversion element - Google Patents
Photoelectric conversion elementInfo
- Publication number
- JPS62209872A JPS62209872A JP61053020A JP5302086A JPS62209872A JP S62209872 A JPS62209872 A JP S62209872A JP 61053020 A JP61053020 A JP 61053020A JP 5302086 A JP5302086 A JP 5302086A JP S62209872 A JPS62209872 A JP S62209872A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous semiconductor
- semiconductor layer
- electrode
- transparent conductive
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000002245 particle Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- -1 Roll Chemical compound 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
本発明は、透明絶縁性基板上に透明導電膜よりなる第一
の電極と、その電極上にＰＩＮまたはＰＮ接合を少なく
とも一つ有し、光の入射により光起電力を発生する非晶
質半導体層と、その半導体上に第二の電極（裏面電極）
を有する光電変換素子に関する。The present invention is an amorphous semiconductor that has a first electrode made of a transparent conductive film on a transparent insulating substrate, and at least one PIN or PN junction on the electrode, and that generates a photovoltaic force upon incidence of light. layer and a second electrode (back electrode) on top of the semiconductor
The present invention relates to a photoelectric conversion element having:
アモルファス・シリコンのような非晶質半導体を用いた
光電変換素子の従来技術の例を第２図に示す、平坦な表
面を有するガラス基板ｌの上にｌＴＯ，５ｎＯ１等の透
明導電膜２を電子ビーム蒸着法、または熱ＣＶＤ法で１
層または２層に形成することが知られている。この場合
、透明導電膜２の結晶粒を成長させることにより、その
表面に径が０．１〜０．５ｎ程度で深さ０．１〜０．４
−の凹凸を生ずる。
この透明導電膜の上部にＰＩＮ接合を有する非晶質半導
体層３のｐＨ！３１． ｌｌｌｌ３２． Ｎｌ！３３
を積層する。この時、透明導電膜２の表面の凹凸の深さ
が０、２ ｎ未満の場合には非晶質半導体層の表面の凹
凸が積層過程において緩和されるために、深さが浅くな
ってしまう、特に前記非晶質半導体層を０．５−以上に
厚く積層する場合には、凹凸の深さはＯ，ＯＳμ以下と
なってしまうため、裏面金属電極４との界面での十分な
散乱効果を期待することは出来ず、入射光を非晶質半導
体層３に十分に閉じこめることが出来ない。逆に、表面
凹凸の深さが０．２ｎ以上の場合には、透明導電膜２の
上に形成される非晶質半導体層３にピンホールの発生す
る可能性が増大すること、および透明導電膜２の表面の
凸部５の力学的強度が小さくなり、非晶質半導体層３堆
積時にこの部分で折れてしまい素子の信鯨性が損なわれ
ること、さらに表面凹凸深さの増大とともに透明導電膜
２の光吸収量が増大してしまうことなどの問題があり、
この種の充電変換素子の製造歩留りを太き（引下げてい
た。An example of a conventional photoelectric conversion element using an amorphous semiconductor such as amorphous silicon is shown in FIG. 2. A transparent conductive film 2 of lTO, 5nO1, etc. 1 by beam evaporation method or thermal CVD method
It is known to form a layer or two layers. In this case, by growing crystal grains of the transparent conductive film 2, a diameter of about 0.1 to 0.5 nm and a depth of 0.1 to 0.4 nm are formed on the surface.
-Produces unevenness. The pH of the amorphous semiconductor layer 3 having a PIN junction on the top of this transparent conductive film! 31. lllll32. Nl! 33
Laminate. At this time, if the depth of the unevenness on the surface of the transparent conductive film 2 is less than 0.2 n, the unevenness on the surface of the amorphous semiconductor layer will be relaxed during the lamination process, resulting in a shallow depth. In particular, when the amorphous semiconductor layer is laminated to a thickness of 0.5- or more, the depth of the unevenness is less than O,OSμ, so that a sufficient scattering effect at the interface with the back metal electrode 4 is required. Therefore, the incident light cannot be sufficiently confined in the amorphous semiconductor layer 3. Conversely, if the depth of the surface irregularities is 0.2n or more, the possibility of pinholes occurring in the amorphous semiconductor layer 3 formed on the transparent conductive film 2 increases, and the transparent conductive film 2 The mechanical strength of the convex portions 5 on the surface of the film 2 decreases, and the amorphous semiconductor layer 3 breaks at this portion during deposition, impairing the reliability of the device. Furthermore, as the depth of the surface irregularities increases, the transparent conductivity decreases. There are problems such as an increase in the amount of light absorbed by the film 2.
This has increased (reduced) the manufacturing yield of this type of charge conversion element.
【発明の目的］
本発明は、裏面電極の非晶質半導体層側の界面における
光散乱効果を利用してＰＩＮ接合あるいはＰＮ接合を有
する非晶質半導体層内部における光路長を増すことによ
り短絡電流を増大させるための非晶質半導体層と裏面電
極との界面の凹凸を、透明電極を形成する透明導電膜の
表面の凹凸によらないで形成して、製造歩留りを高くす
ることのできる光電変換素子を提供することを目的とす
る。
【発明の要点】
本発明は、裏面電極を形成する金属層の下層との界面が
透明電極と非晶質半導体層との界面より深い凹凸を有す
るようにするもので、そのような凹凸面は非晶質半導体
層の反基板側の表面を凹凸にすること、あるいは非晶質
半導体層の反基板側面を透明導電膜により被覆しその表
面を凹凸にすることにより得ることができ、基板上の第
一電極を形成する透明導電膜の表面を凹凸にする必要が
ないため、非晶質半導体層成膜時の第一電極表面の損傷
、ピンホールの発生あるいは透明導電膜の光吸収量の増
大が起こらず、上述の目的が達成される。Purpose of the Invention The present invention utilizes the light scattering effect at the interface on the amorphous semiconductor layer side of the back electrode to increase the optical path length inside the amorphous semiconductor layer having a PIN junction or PN junction, thereby reducing the short-circuit current. Photoelectric conversion that increases manufacturing yield by forming irregularities on the interface between the amorphous semiconductor layer and the back electrode without depending on the irregularities on the surface of the transparent conductive film forming the transparent electrode. The purpose is to provide an element. [Summary of the Invention] According to the present invention, the interface between the metal layer forming the back electrode and the lower layer has deeper unevenness than the interface between the transparent electrode and the amorphous semiconductor layer. This can be obtained by making the surface of the amorphous semiconductor layer on the side opposite to the substrate uneven, or by coating the side of the amorphous semiconductor layer opposite to the substrate with a transparent conductive film and making the surface uneven. Since there is no need to make the surface of the transparent conductive film that forms the first electrode uneven, damage to the first electrode surface, generation of pinholes, or increase in the amount of light absorption of the transparent conductive film occurs when forming the amorphous semiconductor layer. does not occur and the above objective is achieved.
以下図を引用して本発明の実施例について説明する。第
２図を含めて各図における共通部分には同一符号が付さ
れている。第１図においては、ガラス基［１上にＳｎｕ
ｇまたはＩＴＯなどを主成分とする透明導電膜２が１８
００〜２０００人の厚さに形成され、その透明導電膜上
にはＰ膜３１．■膜３２．Ｎ膜３３からなるＰＩＮ接合
（もしくはＮＩＰ接合）を有する■族元素に水素または
ふっ素などを添加した非晶質半導体１１５３を０．５〜
２．Ｏｎの厚さで積層し、その非晶質半導体層の最後に
形成されたＮ膜３３の表面をエツチング処理することに
より凹凸を生じせしめ、その後Ａｎ、Ａｇなどの高反射
性金属からなる裏面電極４および端子電極４１を蒸着ま
たはスパッタリング等によって形成する。前記凹凸の形
状は、ＮａＯＨ，Ｒｏｌｌ、ヒドラジン等を用いて形成
できるが、エツチングの条件により深さを０．０１〜１
．０＃１＃＊径を０．１〜１．５μ程度の範囲で制御す
ることが可能である。基板１から入射した光６が裏面電
極４との界面で反射される時に散乱を受ける度合（散乱
度）を、Ｎ膜３３表面の凹凸深さ０．３−において凹凸
径を変化させた場合に波長λの関数として表わした線図
を第６図に示す、この構成によれば、非晶質半導体層３
表面の凹凸の粗さを散乱させたい光の波長に合わせて変
化させることにより、ガラス基板１より入射した光６は
非晶質半導体層３と金属Ｔｉ極４の界面において散乱を
受けるため、垂直に入射方向に戻る光は減少し、さらに
散乱光のうち入射角の大きいものの大部分は、非晶質半
導体ＷＪ３と透明導電膜２及び透明導電膜２とガラス基
板１の間の界面で反射されるため、非晶質半導体層３内
部に入射した光がふたたびその非晶質半導体層から出て
い（までに進む距離が大きく増加し、非晶質半導体［３
内部における光の吸収量が増加し、その光電変換素子の
短絡電流を増大させることが可能となる。非晶質半導体
としてｔｒｒ −５ｉ：Ｈを用いた場合、ソーラシエミ
レータＡＭＩ、１００ＩＩＷ／−下で裏面の凹凸が存在
しない場合の短絡電流密度が１４ｍ＾／ｃｇｉであるの
に対して、凹凸が存在する場合には１６．５ｍＡ／−の
短絡電流を得ることが出来た。
第３図は本発明の別の実施例を示すもので、第１図のも
のと相違する点は、ＰＩＮ （またはＮＩＰ）接合を
持つ非晶質半導体Ｎ３を積層した後に、これをエツチン
グ処理することなく、その上にＳｎＯ＊＋ またはＩＴ
Ｏなどを主成分とする透明導電膜７を形成する。その際
にこの透明導電膜の結晶粒の成長を促進することにより
深さが０．０１〜０．７μ、径が０．１〜１．３−の凹
凸を生じさせることが出来る。または、一旦平坦に透明
導電膜を形成した後に、エツチング処理を施すことによ
り、透明導電Ｗ！、７の表面に深さが０．０１〜１．
Ｑ ｐｍ 、粒径０．１〜１．５ ｎの凹凸を生じさせ
ることも出来る。この透明導電膜７の上部にｋｌ、Ａｇ
等の金属電極４を蒸着またはスパッタリング等によって
形成する。この構成によれば、第１図においては裏面で
の散乱が非晶質半導体Ｎ３と金属裏面電極４の間で起き
たのに対して、この実施例においては透明導電膜７と金
属電極４の間において散乱が起きる点が異なっており、
散乱度は第１図の実施例と同様に凹凸の形状の関数であ
る。
第４図は、本発明のさらに別の実施例を示すもので、ガ
ラス基板ｌ上にＩＴＯまたはＳｎｕｇなどを主成分とす
る透明導電膜２を形成する際、この透明導電膜の結晶粒
の成長を促進することにより、透明導電膜２の表面に深
さ０．旧〜０．１８ｎ、粒径が０、１〜１．５ ｔｒｙ
ｓの凹凸を生じせしめ、その上部にＰＩＮまたはＮＩＰ
接合を有する■族元素に水素またはふっ素などを添加し
た非晶質半導体層３を０．２〜２．０μの厚さで積層す
る。この非晶質半導体層を積層する過程において横方向
の膜厚差緩和が生ずるために、積層された非晶質半導体
層３の表面は透明導電膜２の表面の凹凸を十分に反映せ
ず、十分な散乱面にはならない、そこで非晶質半導体Ｎ
３の表面をプラズマエツチング処理することにより、そ
の表面に深さが０．０１〜１．Ｏｎ、粒径が０．１〜１
．５ ｎの凹凸を生じせしめることが出来る。さらに、
その上に金属電極４を蒸着またはスパッタリングなどに
よって形成する。この構成によれば、ガラス基板１より
入射した光６は、透明導電膜２と非晶質半導体層３の界
面（第一散乱面）において第一次の散乱を受ける。さら
に入射光は、非晶質半導体層３と裏面電極４の界面（第
二散乱面）において第二次の散乱を受ける。散乱度は、
第６図に示すように凹凸の深さと粒径により大きく変化
するが、この実施例においては、第−散乱面と第二散乱
面の凹凸の形状を任意かつ独立に調整することが可能な
ために、太陽光線のように広いスペクトル域を持つ光に
対しては、該第−散乱面と該第二散乱面の凹凸形状を変
化させることによって全波にわたって散乱度を上げ、全
体としての光の光路長を伸ばすことにより非晶質半導体
層内部での光の吸収量を増加させ、光電変換素子の短絡
電流を大きく向上させることが可能となる。第７図に、
非晶質半導体層としてアモルファス・シリコンを用い、
第一散乱面の凹凸を深さ０．１８７１１１１粒径０．３
−１第二散乱面の凹凸を深さ０．２ ＃＠ １粒径０．
５−とした場合およびいずれの散乱面も持たない場合の
光電変換素子の出力特性を、それぞれ曲線７１および７
２で示す、裏面電極の金属にはＡｇを用いている。散乱
面を持つ場合は、短絡充電流密度として２０ｍＡ／ｃｄ
が得られている。
第５図は、本発明のさらに異なる実施例を示すもので、
第二散乱面を第３図の実施例と同様に透明導電膜７によ
り形成する点が第４図の実施例と異なっている。Embodiments of the present invention will be described below with reference to the drawings. Common parts in each figure including FIG. 2 are given the same reference numerals. In FIG. 1, Snu
The transparent conductive film 2 whose main component is g or ITO is 18
A P film is formed on the transparent conductive film to a thickness of 31.0 to 2000. ■Membrane 32. An amorphous semiconductor 1153, which has a PIN junction (or NIP junction) consisting of an N film 33, and is made by adding hydrogen or fluorine to a group III element is 0.5~
2. The surface of the N film 33 formed at the end of the amorphous semiconductor layer is etched to create unevenness, and then a back electrode made of a highly reflective metal such as An or Ag is formed. 4 and a terminal electrode 41 are formed by vapor deposition, sputtering, or the like. The shape of the unevenness can be formed using NaOH, Roll, hydrazine, etc., but the depth may be 0.01 to 1 depending on the etching conditions.
．． It is possible to control the diameter of 0#1#* within a range of about 0.1 to 1.5μ. The degree of scattering (scattering degree) when the light 6 incident from the substrate 1 is reflected at the interface with the back electrode 4 is determined by changing the diameter of the asperities at a depth of 0.3 − of the asperities on the surface of the N film 33 A diagram expressed as a function of wavelength λ is shown in FIG. 6. According to this configuration, the amorphous semiconductor layer 3
By changing the roughness of the surface irregularities according to the wavelength of the light to be scattered, the light 6 incident on the glass substrate 1 is scattered at the interface between the amorphous semiconductor layer 3 and the metal Ti electrode 4, so that the light 6 can be scattered vertically. The amount of light that returns to the incident direction decreases, and most of the scattered light that has a large incident angle is reflected at the interfaces between the amorphous semiconductor WJ3 and the transparent conductive film 2 and between the transparent conductive film 2 and the glass substrate 1. As a result, the distance traveled by the light incident on the inside of the amorphous semiconductor layer 3 increases significantly until it exits the amorphous semiconductor layer 3 again.
The amount of light absorbed inside increases, making it possible to increase the short-circuit current of the photoelectric conversion element. When trr -5i:H is used as an amorphous semiconductor, the short circuit current density is 14 m^/cgi under a solar emulator AMI of 100 IIW/- without any unevenness on the back surface; When , a short circuit current of 16.5 mA/- could be obtained. FIG. 3 shows another embodiment of the present invention, which differs from the one in FIG. 1 in that an amorphous semiconductor N3 having a PIN (or NIP) junction is laminated and then etched. SnO** or IT
A transparent conductive film 7 containing O or the like as a main component is formed. At this time, by promoting the growth of crystal grains of this transparent conductive film, it is possible to produce irregularities with a depth of 0.01 to 0.7 μm and a diameter of 0.1 to 1.3 μm. Alternatively, by forming a flat transparent conductive film and then performing an etching process, transparent conductive W! , 7 with a depth of 0.01 to 1.
It is also possible to produce unevenness with Q pm and a particle size of 0.1 to 1.5 n. On the top of this transparent conductive film 7, kl, Ag
The metal electrode 4 is formed by vapor deposition, sputtering, or the like. According to this configuration, scattering on the back surface occurred between the amorphous semiconductor N3 and the metal back electrode 4 in FIG. The difference is that scattering occurs between
The degree of scattering is a function of the shape of the asperities as in the embodiment of FIG. FIG. 4 shows still another embodiment of the present invention, in which when a transparent conductive film 2 mainly composed of ITO or Snug is formed on a glass substrate l, crystal grains of the transparent conductive film grow. By promoting this process, a depth of 0.0 mm is formed on the surface of the transparent conductive film 2. Old ~ 0.18n, particle size 0, 1~1.5 try
s unevenness and PIN or NIP on the top.
An amorphous semiconductor layer 3 in which hydrogen, fluorine, or the like is added to a group (1) element having a junction is laminated to a thickness of 0.2 to 2.0 μm. In the process of laminating this amorphous semiconductor layer, the difference in thickness in the lateral direction is relaxed, so the surface of the laminated amorphous semiconductor layer 3 does not sufficiently reflect the unevenness of the surface of the transparent conductive film 2. It does not become a sufficient scattering surface, so the amorphous semiconductor N
By plasma etching the surface of No. 3, the surface has a depth of 0.01 to 1. On, particle size is 0.1-1
．． 5n of unevenness can be produced. moreover,
A metal electrode 4 is formed thereon by vapor deposition or sputtering. According to this configuration, light 6 incident from the glass substrate 1 undergoes first-order scattering at the interface (first scattering surface) between the transparent conductive film 2 and the amorphous semiconductor layer 3. Further, the incident light undergoes second-order scattering at the interface (second scattering surface) between the amorphous semiconductor layer 3 and the back electrode 4. The degree of scattering is
As shown in FIG. 6, it varies greatly depending on the depth and particle size of the unevenness, but in this example, the shape of the unevenness on the first scattering surface and the second scattering surface can be adjusted arbitrarily and independently. In addition, for light with a wide spectral range such as sunlight, by changing the uneven shape of the first scattering surface and the second scattering surface, the degree of scattering is increased over the entire wave, and the overall light intensity is increased. By increasing the optical path length, it is possible to increase the amount of light absorbed inside the amorphous semiconductor layer and to greatly improve the short circuit current of the photoelectric conversion element. In Figure 7,
Using amorphous silicon as the amorphous semiconductor layer,
The depth of the irregularities on the first scattering surface is 0.1871111 and the particle size is 0.3.
-1 Depth of unevenness on the second scattering surface is 0.2 #@1 Particle size 0.
The output characteristics of the photoelectric conversion element when 5- and when there is no scattering surface are shown by curves 71 and 7, respectively.
Ag is used as the metal of the back electrode shown by 2. If it has a scattering surface, the short circuit charging current density is 20mA/cd.
is obtained. FIG. 5 shows yet another embodiment of the present invention,
This embodiment differs from the embodiment shown in FIG. 4 in that the second scattering surface is formed of a transparent conductive film 7, similar to the embodiment shown in FIG.
本発明によれば、非晶質半導体層への光閉じ込めのため
に形成される裏面電極下面の光反射面の凹凸を、透明絶
縁性基板上の透明電極を形成する透明導電膜面の凹凸に
依存せず、金属層直下の層の面に形成された凹凸によっ
て設け、基板上の透明導電膜面よりも大きい凹凸を持た
せることにより、反射光の散乱度を高くして非晶質半導
体層内の光路長を伸ばし、層内における光の吸収量を増
加させて光電変換素子の短絡光電流を向上させることが
可能になった。そして、基板上の透明導電膜の結晶粒の
成長を過度にする必要がないので、非晶質半導体層に障
害が生せず、製造歩留りの低下を阻止して高い良品率を
得ることができる。According to the present invention, the unevenness on the light reflecting surface on the lower surface of the back electrode formed for light confinement in the amorphous semiconductor layer is replaced by the unevenness on the surface of the transparent conductive film forming the transparent electrode on the transparent insulating substrate. By providing unevenness that is larger than the surface of the transparent conductive film on the substrate, the degree of scattering of reflected light is increased and the amorphous semiconductor layer By increasing the optical path length within the layer and increasing the amount of light absorbed within the layer, it has become possible to improve the short-circuit photocurrent of the photoelectric conversion element. In addition, since there is no need to excessively grow the crystal grains of the transparent conductive film on the substrate, the amorphous semiconductor layer will not be damaged, and a decline in manufacturing yield can be prevented and a high quality product rate can be obtained. .
第１図は本発明の一実施例の断面図、第２図は従来例の
断面図、第３図、第４図、第５図はそれぞれ本発明の異
なる実施例の断面図、第６図は反射面の凹凸径をパラメ
ータとした光の散乱度と波長の関係線図、第７図は第４
図に示した実施例と従来例との出力特性線図である。
１ニガラス基板、２．７：透明導電膜、３：非晶質半導
体層、４：金属裏面電橋。
第１図
ム
第２図
第３図
第４図
第５図FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a sectional view of a conventional example, FIGS. 3, 4, and 5 are sectional views of different embodiments of the present invention, and FIG. Figure 7 is a diagram of the relationship between the degree of scattering of light and the wavelength using the diameter of the unevenness of the reflecting surface as a parameter.
FIG. 4 is an output characteristic diagram of the embodiment shown in the figure and the conventional example. 1 glass substrate, 2.7: transparent conductive film, 3: amorphous semiconductor layer, 4: metal backside electrical bridge. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
面電極を積層してなるものにおいて、裏面電極を形成す
る金属層の下層との界面が透明電極と非晶質半導体層と
の界面より深い凹凸を有することを特徴とする光電変換
素子。 ２）特許請求の範囲第１項記載の素子において、裏面電
極を形成する金属層が非晶質半導体層に直接接すること
を特徴とする光電変換素子。 ３）特許請求の範囲第１項記載の素子において、裏面電
極が金属層とその下に接する透明導電膜よりなることを
特徴とする光電変換素子。[Claims] 1) In a structure in which a transparent electrode, an amorphous semiconductor layer, and a back electrode are laminated on a transparent insulating substrate, the interface between the lower layer of the metal layer forming the back electrode is between the transparent electrode and the non-crystalline electrode. A photoelectric conversion element characterized by having unevenness deeper than an interface with a crystalline semiconductor layer. 2) A photoelectric conversion element according to claim 1, wherein the metal layer forming the back electrode is in direct contact with the amorphous semiconductor layer. 3) A photoelectric conversion element according to claim 1, wherein the back electrode comprises a metal layer and a transparent conductive film in contact with the metal layer below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053020A JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053020A JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62209872A true JPS62209872A (en) | 1987-09-16 |
| JPH0793447B2 JPH0793447B2 (en) | 1995-10-09 |
Family
ID=12931215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61053020A Expired - Fee Related JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793447B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045908A (en) * | 1990-09-25 | 1991-09-03 | Motorola, Inc. | Vertically and laterally illuminated p-i-n photodiode |
| JPH0423149U (en) * | 1990-06-13 | 1992-02-26 | ||
| WO1999063600A1 (en) * | 1998-06-01 | 1999-12-09 | Kaneka Corporation | Silicon-base thin-film photoelectric device |
| JP2008506249A (en) * | 2004-07-07 | 2008-02-28 | サン−ゴバン グラス フランス | Solar cell and solar module |
| WO2009119174A1 (en) * | 2008-03-26 | 2009-10-01 | 日本合成化学工業株式会社 | Solar cell substrate and solar cell |
| WO2010004811A1 (en) * | 2008-07-07 | 2010-01-14 | 三菱電機株式会社 | Thin film solar cell and manufacturing method thereof |
| WO2010023867A1 (en) * | 2008-08-25 | 2010-03-04 | 株式会社エバテック | Thin-film solar cell and manufacturing method therefore and substrate for thin-film solar cell |
| WO2012169123A1 (en) * | 2011-06-10 | 2012-12-13 | Ｊｘ日鉱日石エネルギー株式会社 | Photoelectric conversion element |
| JP2013004805A (en) * | 2011-06-17 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| JP2013004535A (en) * | 2011-06-10 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| WO2017154384A1 (en) * | 2016-03-10 | 2017-09-14 | 株式会社カネカ | Solar cell module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8828780B2 (en) * | 2010-04-05 | 2014-09-09 | Mitsubishi Electric Corporation | Substrate for photoelectric conversion device and method of manufacturing the substrate, thin-film photoelectric conversion device and method of manufacturing the thin-film photoelectric conversion device, and solar cell module |
-
1986
- 1986-03-11 JP JP61053020A patent/JPH0793447B2/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423149U (en) * | 1990-06-13 | 1992-02-26 | ||
| US5045908A (en) * | 1990-09-25 | 1991-09-03 | Motorola, Inc. | Vertically and laterally illuminated p-i-n photodiode |
| WO1999063600A1 (en) * | 1998-06-01 | 1999-12-09 | Kaneka Corporation | Silicon-base thin-film photoelectric device |
| JP2008506249A (en) * | 2004-07-07 | 2008-02-28 | サン−ゴバン グラス フランス | Solar cell and solar module |
| WO2009119174A1 (en) * | 2008-03-26 | 2009-10-01 | 日本合成化学工業株式会社 | Solar cell substrate and solar cell |
| JP5127925B2 (en) * | 2008-07-07 | 2013-01-23 | 三菱電機株式会社 | Thin film solar cell and manufacturing method thereof |
| WO2010004811A1 (en) * | 2008-07-07 | 2010-01-14 | 三菱電機株式会社 | Thin film solar cell and manufacturing method thereof |
| WO2010023867A1 (en) * | 2008-08-25 | 2010-03-04 | 株式会社エバテック | Thin-film solar cell and manufacturing method therefore and substrate for thin-film solar cell |
| JP2013004535A (en) * | 2011-06-10 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| WO2012169123A1 (en) * | 2011-06-10 | 2012-12-13 | Ｊｘ日鉱日石エネルギー株式会社 | Photoelectric conversion element |
| JP2013004805A (en) * | 2011-06-17 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| WO2017154384A1 (en) * | 2016-03-10 | 2017-09-14 | 株式会社カネカ | Solar cell module |
| JPWO2017154384A1 (en) * | 2016-03-10 | 2019-01-10 | 株式会社カネカ | Solar cell module |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793447B2 (en) | 1995-10-09 |
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