JPS62203519U - - Google Patents

Info

Publication number
JPS62203519U
JPS62203519U JP9232886U JP9232886U JPS62203519U JP S62203519 U JPS62203519 U JP S62203519U JP 9232886 U JP9232886 U JP 9232886U JP 9232886 U JP9232886 U JP 9232886U JP S62203519 U JPS62203519 U JP S62203519U
Authority
JP
Japan
Prior art keywords
level
input signal
input
output level
time period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9232886U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9232886U priority Critical patent/JPS62203519U/ja
Publication of JPS62203519U publication Critical patent/JPS62203519U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図はその各部波形図。 3,8,15,19,18,21……トランジ
スタ、13,23……ダイオード。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure shows the waveform diagram of each part. 3, 8, 15, 19, 18, 21...transistor, 13,23...diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号を受け入れる第1及び第2の入力端子
を有し、入力信号の印加毎に出力レベルが第1の
レベルと第2のレベルとのいずれかに変化するフ
リツプフロツプ回路において、上記出力レベルが
第1のレベルに変化した直後から第1の所定時間
上記入力信号が上記第1の入力端子に加わるのを
阻止する手段と、上記出力レベルが第2のレベル
に変化した直後から第2の所定時間上記入力信号
が上記第2の入力端子に阻止する手段とを有する
フリツプフロツプ回路。
A flip-flop circuit has first and second input terminals for receiving an input signal, and the output level changes between a first level and a second level each time an input signal is applied. means for preventing the input signal from being applied to the first input terminal for a first predetermined time period immediately after the output level changes to a second level; and a second predetermined time period immediately after the output level changes to a second level. means for blocking said input signal to said second input terminal.
JP9232886U 1986-06-17 1986-06-17 Pending JPS62203519U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9232886U JPS62203519U (en) 1986-06-17 1986-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9232886U JPS62203519U (en) 1986-06-17 1986-06-17

Publications (1)

Publication Number Publication Date
JPS62203519U true JPS62203519U (en) 1987-12-25

Family

ID=30953936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9232886U Pending JPS62203519U (en) 1986-06-17 1986-06-17

Country Status (1)

Country Link
JP (1) JPS62203519U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01321488A (en) * 1988-06-22 1989-12-27 Yamaha Corp Electronic keyboard musical instrument

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01321488A (en) * 1988-06-22 1989-12-27 Yamaha Corp Electronic keyboard musical instrument

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