JPS6219745U - - Google Patents

Info

Publication number
JPS6219745U
JPS6219745U JP10983185U JP10983185U JPS6219745U JP S6219745 U JPS6219745 U JP S6219745U JP 10983185 U JP10983185 U JP 10983185U JP 10983185 U JP10983185 U JP 10983185U JP S6219745 U JPS6219745 U JP S6219745U
Authority
JP
Japan
Prior art keywords
substrate
resin layer
insulating resin
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10983185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10983185U priority Critical patent/JPS6219745U/ja
Publication of JPS6219745U publication Critical patent/JPS6219745U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す断面図、第2図
は他の実施例を示す断面図、第3図は従来例を示
す斜視図、第4図は従来例を示す断面図である。 1……基板、2……絶縁性樹脂層、3……回路
素子、4……周端部。
Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a sectional view showing another embodiment, Fig. 3 is a perspective view showing a conventional example, and Fig. 4 is a sectional view showing a conventional example. . DESCRIPTION OF SYMBOLS 1...Substrate, 2...Insulating resin layer, 3...Circuit element, 4...Peripheral edge part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板の一主面上に回路素子等を設け、前記基板
上にトランスフアー・モールドにより絶縁樹脂層
を形成する混成集積回路に於いて、前記基板の周
端を前記絶縁樹脂層の略中間より上側で折曲げ位
置したことを特徴とする混成集積回路。
In a hybrid integrated circuit in which circuit elements, etc. are provided on one principal surface of a substrate, and an insulating resin layer is formed on the substrate by transfer molding, the peripheral edge of the substrate is located above approximately the middle of the insulating resin layer. A hybrid integrated circuit characterized by being bent at a position.
JP10983185U 1985-07-18 1985-07-18 Pending JPS6219745U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10983185U JPS6219745U (en) 1985-07-18 1985-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10983185U JPS6219745U (en) 1985-07-18 1985-07-18

Publications (1)

Publication Number Publication Date
JPS6219745U true JPS6219745U (en) 1987-02-05

Family

ID=30988291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10983185U Pending JPS6219745U (en) 1985-07-18 1985-07-18

Country Status (1)

Country Link
JP (1) JPS6219745U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265134A (en) * 1987-01-21 1988-11-01 Naigai Glass Kogyo Kk Strength measuring apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265134A (en) * 1987-01-21 1988-11-01 Naigai Glass Kogyo Kk Strength measuring apparatus

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