JPS6219049B2 - - Google Patents
Info
- Publication number
- JPS6219049B2 JPS6219049B2 JP57004035A JP403582A JPS6219049B2 JP S6219049 B2 JPS6219049 B2 JP S6219049B2 JP 57004035 A JP57004035 A JP 57004035A JP 403582 A JP403582 A JP 403582A JP S6219049 B2 JPS6219049 B2 JP S6219049B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- width
- resist
- exposure
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 26
- 238000011161 development Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 22
- 239000007921 spray Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
発明の技術分野
この発明は、ICやLSI等の半導体素子の製造方
法に関し、さらに詳しくは微細加工を行うフオト
リソグラフイ（光蝕刻法）の工程に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing semiconductor elements such as ICs and LSIs, and more specifically to a photolithography process for microfabrication.
発明の技術的背景
最近のフオトリソグラフイは、素子の集積度向
上のためにパターンの微細化が進み、解像度や寸
法精度が重要視されるにつれて、使用されるフオ
トレジストはネガ型からポジ型に移行し、露光装
置はコンタクト方式や１：１プロジエクシヨン方
式に加えてステツプアンドリピート方式が注目さ
れるようになつた。Technical Background of the Invention In recent photolithography, patterns have become finer to improve the degree of integration of devices, and as resolution and dimensional accuracy have become more important, the photoresists used have changed from negative to positive. As a result, in addition to the contact method and 1:1 projection method, the step-and-repeat method has attracted attention as exposure equipment.
また現像装置は、デイツプ方式とスプレー方式
に大別されるが、デイツプ方式はウエハ面内及び
ウエハ間の現像むらやレジスト残り等の不良が発
生しやすく、また自動化し難いという欠点がある
ので、スプレー方式の自動化装置が使用される場
合が多いようである。 Furthermore, developing devices are broadly classified into dip type and spray type, but the dip type has the disadvantage that defects such as uneven development within the wafer surface and between wafers and resist residue are likely to occur, and it is difficult to automate. It appears that automated spray-type equipment is often used.
背景技術の問題点
しかしながら、スプレー方式の現像の場合に
は、ウエハの中央部と周縁部とでレジストパター
ンの幅寸法が異なるという問題がある。すなわ
ち、ポジ型レジストの場合周縁部に比べて中央部
のレジストパターンの幅寸法は、残しパターンの
幅寸法が小さくなり、穴あけパターンの幅寸法が
大きくなる。Problems with the Background Art However, in the case of spray-type development, there is a problem in that the width dimension of the resist pattern is different between the center portion and the peripheral portion of the wafer. That is, in the case of a positive resist, the width of the resist pattern at the center is smaller than that of the remaining pattern, and the width of the perforation pattern is larger than that at the periphery.
この問題は次の(i)(ii)の現像と密接な関係がある
と考えられている。 This problem is considered to be closely related to the following development (i) and (ii).
(i) スプレー方式では、一般にウエハを回転させ
ながら現像液を散布しているのでウエハ中央部
が周縁部に比べてより多くの現像液当り、中央
部の現像速度が速くなること。(i) In the spray method, the developer is generally sprayed while rotating the wafer, so the center of the wafer is exposed to more developer than the periphery, and the development speed in the center is faster.
(ii) 現像液温を一定に保つために室温より高くす
ることが多いが、この場合周縁部では中央部に
比べて温度が下がり易く、周縁部の現像速度が
遅くなること。(ii) In order to keep the developer temperature constant, it is often set higher than room temperature, but in this case, the temperature at the periphery tends to drop more easily than the center, and the development speed at the periphery becomes slower.
このように現像速度が異なつて幅寸法がばらつ
くということは、特に微細なパターンの場合、素
子の歩留り低下の大きな原因となる。なかんづ
く、ポバ型レジストはネガ型レジストより現像速
度が現像条件によつて影響を受けやすいので、ポ
ジ型レジストを使用した場合特に大きな問題とな
つている。 Such variations in width due to different development speeds are a major cause of reduced device yield, especially in the case of fine patterns. In particular, since the development speed of a POV resist is more easily affected by development conditions than a negative resist, this poses a particularly serious problem when a positive resist is used.
第１図は従来の製造方法（すなわちポジ型レジ
スト塗布後、ウエハ全面を同一露光時間で露光し
たものを、スプレー方式で現像する方法）によつ
て得られたパターン幅寸法（約２μｍ）の変動を
示す図である。同図において横軸はウエハ中心か
ら距離ｄ（mm）を、縦軸はレジストパターンの幅
寸法ｔ（μｍ）を表わす。この図から、従来の製
造方法によると、中央部は相対的に現像速度が速
く、一方周縁部は相対的に現像速度が遅く、レジ
ストパターンの幅寸法がばらつくことがわかる。 Figure 1 shows the variation in pattern width dimension (approximately 2 μm) obtained by the conventional manufacturing method (i.e., after applying a positive resist, the entire wafer is exposed for the same exposure time and then developed using a spray method). FIG. In the figure, the horizontal axis represents the distance d (mm) from the center of the wafer, and the vertical axis represents the width t (μm) of the resist pattern. From this figure, it can be seen that according to the conventional manufacturing method, the development speed is relatively fast in the center part, while the development speed is relatively slow in the peripheral part, and the width dimension of the resist pattern varies.
発明の目的
この発明の目的は、スプレー方式（シヤワー方
式を含む）の現像において形成されるレジストパ
ターンの幅寸法のばらつきを解消する新規な半導
体素子の製造方法を提供することにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a novel method for manufacturing a semiconductor device that eliminates variations in the width dimension of resist patterns formed in spray-type (including shower-type) development.
発明の概要
この発明の半導体素子の製造方法は、レジスト
パターンの幅寸法が露光時間増減によつて変化す
ることに着目してなされたものである。即ちレジ
スト塗布工程において被塗布面にほぼ均一に塗布
されたフオトレジスト膜がスプレー又はシヤワー
方式の現像工程によつてレジストパターンに形成
されるが、そのレジストパターンの幅寸法のばら
つきを、露光工程において被塗布面の周縁部から
中央部に向かつて徐々に露光時間を変えたステツ
プアンドリピート露光を行うことにより補償し
て、そのばらつきを解消しようとするものであ
る。SUMMARY OF THE INVENTION The method for manufacturing a semiconductor device of the present invention was developed by focusing on the fact that the width dimension of a resist pattern changes depending on an increase or decrease in exposure time. That is, in the resist coating process, a photoresist film that is almost uniformly applied to the surface to be coated is formed into a resist pattern by a spray or shower development process. This is an attempt to eliminate the variation by compensating by performing step-and-repeat exposure in which the exposure time is gradually changed from the periphery to the center of the surface to be coated.
レジストパターンの幅寸法と露光時間との関係
はレジストの種類材質によつて異なる。例えばポ
ジ型レジストの場合、第２図のグラフ〔横軸は露
光時間Ｔ（sec）、縦軸はレジストパターンの幅寸
法ｔ（μｍ）を表わす〕に示すように、露光時間
が長くなるにつれてレジストパターンの幅寸法は
減少するので、この事実を利用して現像によつて
レジストパターンの幅寸法が小となるウエハ中央
部については露光時間を少なくし、レジストパタ
ーンの幅寸法が大となるウエハ周縁部については
露光時間を多くするようにすれば、ウエハ全面に
わたつてレジストパターンの幅寸法を一定にする
ことができる。ネガ型レジストの場合にはこの逆
にすればよい。 The relationship between the width dimension of the resist pattern and the exposure time differs depending on the type and material of the resist. For example, in the case of a positive resist, as shown in the graph in Figure 2 [the horizontal axis represents the exposure time T (sec) and the vertical axis represents the width dimension t (μm) of the resist pattern], as the exposure time becomes longer, the resist pattern decreases. Since the width of the pattern decreases, this fact can be used to reduce the exposure time for the center of the wafer, where the width of the resist pattern becomes smaller during development, and for the periphery of the wafer, where the width of the resist pattern becomes larger. By increasing the exposure time, the width of the resist pattern can be made constant over the entire surface of the wafer. In the case of a negative resist, this process may be reversed.
ところで、ステツプアンドリピート方式の露光
は、被露光面を、縮少投影された露光面積で分割
し、繰返し露光の機構を持たせるものであるが、
従来は解像力を高め、欠陥数を減少させ、位置合
せや焦点補正をして精度を向上させるように使わ
れていただけであつて、この発明のようにステツ
プ毎に露光時間を変えてレジストパターンの幅寸
法のばらつきをなくすように使用されたことはな
かつた。 By the way, in the step-and-repeat method of exposure, the surface to be exposed is divided into reduced and projected exposure areas, and a mechanism for repeated exposure is provided.
Conventionally, resist patterns were only used to improve resolution, reduce the number of defects, and correct positioning and focus to improve precision. It has never been used to eliminate variations in width dimensions.
この発明においては、フオトレジストを被塗布
面にほぼ均一に塗布する。塗布膜厚の変動により
レジストパターンの幅寸法の変動が招来される
が、この原因によるレジストパターンの幅寸法の
ばらつきも通常ウエハを回転させて塗布するので
ウエハ周縁部から中央部に向かつて徐々に発生し
ているから、この発明によつて補償される。 In this invention, the photoresist is applied almost uniformly to the surface to be coated. Fluctuations in the width of the resist pattern occur due to variations in the coating film thickness, but variations in the width of the resist pattern due to this cause also occur gradually from the wafer's periphery toward the center because coating is normally performed by rotating the wafer. Since this has occurred, it is compensated by this invention.
この発明における現像工程は、スプレー又はシ
ヤワー方式による。これらの方式の特徴はスピン
ナーにより被現像体が回転することにあり、この
特徴をもつ方式がスピン方式と呼ぶ。通常スプレ
ー方式とは、N2ガスなどによつて現像液が霧吹
され、またシヤワー方式はN2ガスなどで加圧さ
れることによつて現像液がノズルから噴出し、被
現像体に吹き付けられる。 The developing step in this invention is carried out by a spray or shower method. The feature of these methods is that the object to be developed is rotated by a spinner, and methods having this feature are called spin methods. In the normal spray method, the developer is atomized using N2 gas, etc., and in the shower method, the developer is pressurized with N2 gas, etc., and the developer is spouted from a nozzle and sprayed onto the object to be developed. .
また、半導体素子製造におけるフオトリソグラ
フイとは、光蝕刻法が適用される工程を意味し、
半導体ウエハ上に適用される場合以外にも、マス
クブランク上に適用される場合などを含むものと
解されなければならない。 In addition, photolithography in semiconductor device manufacturing refers to a process in which a photoetching method is applied.
It should be understood that the present invention includes not only application on semiconductor wafers but also application on mask blanks.
次にこの発明の一実施例とその具体的な効果に
ついて説明する。 Next, an embodiment of the present invention and its specific effects will be described.
発明の実施例
厚さ4000Åの酸化膜を有する直径100mmのシリ
コンウエハに1.5μｍの厚さでポジ型フオトレジ
ストを塗布したのち、90℃・10分間のプリベーキ
ングを行つた。次に露光工程では10mm×10mmのス
テツプピツチでウエハ中央部のチツプに対しては
0.2秒の露光時間で、またウエハ周縁部のチツプ
に対しては0.4秒の露光時間となるようにウエハ
周縁部からウエハ中央部に向かうにつれて徐々に
露光時間を減少させつつ縮少投影型露光装置でス
テツプアンドリピート式に露光を行つた。そして
露光後のウエハをスプレー方式により現像をした
後、該レジストパターンの幅寸法の分布を測定し
たところ、ウエハ中心部と周縁部の幅寸法の差は
わずか0.06μｍ以下であつた。また、同一のテス
トを統計的に信頼性のある大きさの母集団につき
行つた幅寸法測定値を、従来方法（すなわち全面
同一露光時間のステツプアンドリピート方式）に
よる幅寸法測定値と比較したところ、標準偏差が
従来法の場合0.10μｍであるのに対して、この発
明の方法の場合0.03μｍであり、レジストパター
ンの幅寸法のばらつきは大幅に減少していた。EXAMPLE OF THE INVENTION A silicon wafer having a diameter of 100 mm and having an oxide film having a thickness of 4000 Å was coated with a positive photoresist to a thickness of 1.5 μm, and then prebaked at 90° C. for 10 minutes. Next, in the exposure process, the chips in the center of the wafer are exposed using a step pitch of 10 mm x 10 mm.
The exposure time is 0.2 seconds, and the exposure time is gradually reduced from the wafer edge to the center of the wafer so that chips at the wafer edge are exposed to 0.4 seconds. Exposure was performed in a step-and-repeat manner. After the exposed wafer was developed by a spray method, the width distribution of the resist pattern was measured, and it was found that the difference in width between the center and peripheral portion of the wafer was only 0.06 μm or less. In addition, the width measurement values obtained by performing the same test on a population of statistically reliable size were compared with the width measurement values obtained using the conventional method (i.e., step-and-repeat method with the same exposure time on the entire surface). The standard deviation was 0.10 μm in the conventional method, whereas it was 0.03 μm in the method of the present invention, and the variation in the width dimension of the resist pattern was significantly reduced.
発明の効果
以上のように、この発明によれば、ウエハ全面
にわたつて均一なパターン寸法が得られ、その結
果チツプ歩留りを改善させることができる新規な
半導体素子の製造方法が提供される。またこの発
明によれば、現像装置やレジスト塗膜装置などの
根本的改良を必要としないうえ、現に使用されて
いる縮少型投影露光装置を使用できるので、改善
効果の大きな割りには改善投資額が不要であり、
従つて大きな費用対比効果が得られる。Effects of the Invention As described above, according to the present invention, a novel semiconductor device manufacturing method is provided which can obtain uniform pattern dimensions over the entire surface of a wafer and, as a result, can improve chip yield. Furthermore, according to this invention, it is not necessary to fundamentally improve the developing device or the resist coating device, etc., and the currently used reduced-size projection exposure device can be used. No amount is required,
Therefore, a large cost-effectiveness can be obtained.
第１図は従来の製造方法によつて得られるウエ
ハ上のレジストパターン幅寸法の分布を示す図、
第２図はこの発明の基礎となる事実を示した図で
ある。
FIG. 1 is a diagram showing the distribution of resist pattern width dimensions on a wafer obtained by a conventional manufacturing method;
FIG. 2 is a diagram showing the basic facts of this invention.
Claims (1)
にあたり、レジスト塗布工程においてはフオトレ
ジストを被塗布面に塗布し、露光現像工程におい
ては被塗布面の周縁部から中央部に向かうステツ
プ毎に増加もしくは減少の一方向に露光時間を変
化させてステツプアンドリピート露光を行つた
後、スピン方式の現像を行うことを特徴とする半
導体素子の製造方法。1 In photolithography in the manufacture of semiconductor devices, in the resist coating process, photoresist is applied to the surface to be coated, and in the exposure and development process, the photoresist increases or decreases in one direction at each step from the periphery to the center of the surface to be coated. 1. A method for manufacturing a semiconductor device, comprising performing step-and-repeat exposure by varying exposure time, and then performing spin development.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57004035A JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57004035A JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58122726A JPS58122726A (en) | 1983-07-21 |
| JPS6219049B2 true JPS6219049B2 (en) | 1987-04-25 |
Family
ID=11573701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57004035A Granted JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58122726A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01159559U (en) * | 1988-04-23 | 1989-11-06 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5943550A (en) * | 1996-03-29 | 1999-08-24 | Advanced Micro Devices, Inc. | Method of processing a semiconductor wafer for controlling drive current |
-
1982
- 1982-01-16 JP JP57004035A patent/JPS58122726A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01159559U (en) * | 1988-04-23 | 1989-11-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58122726A (en) | 1983-07-21 |
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