JPS62188267A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62188267A JPS62188267A JP2957686A JP2957686A JPS62188267A JP S62188267 A JPS62188267 A JP S62188267A JP 2957686 A JP2957686 A JP 2957686A JP 2957686 A JP2957686 A JP 2957686A JP S62188267 A JPS62188267 A JP S62188267A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- groove
- conductive layer
- wiring
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 abstract description 35
- 239000000758 substrate Substances 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000708 deep reactive-ion etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置のコンタクトとその製造方法に関す
るもので、特に配線層とシリコン基板とのコンタクトに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a contact for a semiconductor device and a method for manufacturing the same, and particularly to a contact between a wiring layer and a silicon substrate.
本発明は、配線層を半導体基板の微細なコンタクト領域
に接続させる際に、
コンタクトされる側の導電層に傾斜部分を有する溝部を
設けることによって、
配線層間の接触面積を減少させたものである。The present invention reduces the contact area between wiring layers by providing a groove having an inclined portion in the conductive layer on the side to be contacted when connecting the wiring layer to a fine contact area of a semiconductor substrate. .
半導体装置の微細化に伴い、コンタクト径も徐々に小さ
くする必要性が生じている。ところがコンタクトを微細
化すると配線層間の接触面積は減少してしまうと言う問
題が生じる。With the miniaturization of semiconductor devices, there is a need to gradually reduce the contact diameter. However, when the contacts are miniaturized, a problem arises in that the contact area between wiring layers decreases.
よく知られている様にコンタク１−抵抗は接触面積に反
比例するため、このコンタクトのＵ＆ ｒｌｆＪ化によ
り、安定した抵抗の小さいコンタクトを得る事は増々困
難となって来ている。接触面積を増大させる試みは、今
までにいくつか発表されて来ている。〔■特開昭５９−
１８１６６４ ■特開昭５８−２０９１４４■特開昭
５８−２１６４４１）
いずれもコンタクト窓底部に凹凸を設ける方法であるが
、
■の方法は第２図に示されているように、Ｎ０型不純物
拡散領域１３に凹部を形成し、その凹部と酸化膜７の表
面に金属遮蔽膜１４を形成し、その上にＡＩ配線層９を
設けて接触面積を増大させる方法である。As is well known, the contact resistance is inversely proportional to the contact area, so with the U&rlfJ type of contact, it is becoming more and more difficult to obtain a stable contact with low resistance. Several attempts to increase the contact area have been announced so far. [■ Japanese Patent Application Publication No. 1983-
181664 (Japanese Patent Application Laid-open No. 58-209144 (Japanese Patent Application Laid-open No. 58-216441)) All of these methods involve providing unevenness at the bottom of the contact window, but method (2), as shown in FIG. In this method, a recess is formed in the oxide film 13, a metal shielding film 14 is formed on the recess and the surface of the oxide film 7, and an AI wiring layer 9 is provided thereon to increase the contact area.
■の方法は第３図に示されるように、上層配線４と上層
配線９に凹凸を形成するものである。Method (2), as shown in FIG. 3, forms irregularities on the upper layer wiring 4 and the upper layer wiring 9.
■の方法は第４図に示されるように、コンタクト窓下Ａ
ｔの配線層９を途中までエツチングして第４図Ｃのよう
なスルーホール部１２を形成して接触面積を増大させる
方法である。As shown in Fig. 4, the method (①) is to
This is a method in which the contact area is increased by etching the wiring layer 9 partway through to form a through hole portion 12 as shown in FIG. 4C.
〔発明が解決しようとする問題点〕
■の方法については、Ｎ°型不純物拡散領域１３に凹部
を精度良く形成するのが困難であると言う欠点がある。[Problems to be Solved by the Invention] The method (2) has a drawback in that it is difficult to form recesses in the N° type impurity diffusion region 13 with high precision.
また酸化膜７と基板凹部による直立段差が大きくなるた
め、この上に形成される配線層のカバレッジが悪くなる
と言う問題点もある。Further, since the vertical step between the oxide film 7 and the substrate recess becomes large, there is also the problem that the coverage of the wiring layer formed thereon becomes poor.
■の方法に於ては、下層配線層４に凹部１７を形成する
事が非常に困難であると言う問題点がある。The method (2) has a problem in that it is very difficult to form the recess 17 in the lower wiring layer 4.
■の方法に於ては、エツチングレベルを途中で止めなけ
ればならないと言う問題点がある。この点は量産レベル
に於ては特に困難な問題となる。Method (2) has the problem that the etching level must be stopped midway. This point becomes a particularly difficult problem at the mass production level.
また■の場合と同様、直立段差が大きくなって上層配線
のカバレッジが悪くなると言う問題点もある。Also, as in the case (2), there is also the problem that the vertical step becomes large and the coverage of the upper layer wiring deteriorates.
本発明に於ては、下層の導電層と上層の導電層を絶縁層
に設けた開口を介してコンタクトをとる半導体装置にお
いて、上記開口部に隣接する上記下層の導電層に傾斜部
分を有する溝部を設け、該溝部において、上記上層の導
電層を、上記下層の導電層とコンタクトさせて上記問題
点を解決した。In the present invention, in a semiconductor device in which a lower conductive layer and an upper conductive layer are brought into contact through an opening provided in an insulating layer, a groove portion having an inclined portion in the lower conductive layer adjacent to the opening is provided. The above problem was solved by providing a groove and bringing the upper conductive layer into contact with the lower conductive layer.
本発明に於ては、コンタクトされる側の半導体基板にＶ
字型溝部を設けて配線層とのコンタクトをとっているの
で、コンタクト径が微細にもかかわらず接触面積を大き
くとることができる。また本発明は結晶面の異方性エツ
チングを利用しているので、開口部の径に対応して自動
的にＶ字型溝部が形成される。In the present invention, V is applied to the semiconductor substrate on the side to be contacted.
Since the contact with the wiring layer is made by providing the shape groove, a large contact area can be obtained even though the contact diameter is small. Furthermore, since the present invention utilizes anisotropic etching of crystal planes, a V-shaped groove is automatically formed corresponding to the diameter of the opening.
本発明の半導体装置を第１図Ａ−Ｇの製造方法の工程に
基づいて説明する。The semiconductor device of the present invention will be explained based on the steps of the manufacturing method shown in FIGS. 1A to 1G.
Ａ （１００）のＰ型Ｓｉ半導体基板工にチャンネル
ストッパ２とフィールド酸化膜３を形成する。A channel stopper 2 and field oxide film 3 are formed on a P-type Si semiconductor substrate (100).
Ｂ デー１−酸化膜を成長させた後、多結晶Ｓｉ４によ
りゲート配線層を形成して、セルファラインによりソー
ス領域５とドレイン領域６を形成する。B Day 1 - After growing the oxide film, a gate wiring layer is formed using polycrystalline Si4, and a source region 5 and a drain region 6 are formed using self-alignment lines.
Ｃ層間絶縁膜としてＰＳＧ膜７を表面に形成する。A PSG film 7 is formed on the surface as a C interlayer insulating film.
Ｄ ＲＩＥ法により酸化膜にコンタクトホールを開け
る。A contact hole is made in the oxide film by the DRIE method.
Ｅ 上部配線と基板の接触面積を増やすために■エッチ
溝８を形成する。E. Form an etch groove 8 to increase the contact area between the upper wiring and the substrate.
■エッチ溝８の形成にはアルカリエッチなどのウェット
エッチを利用する。（１１１）面でエツチングが止ま
るので制御性が良い。但し■エッチ溝８の深さを一定に
保つため、コンタクトの開口部の大きさは一定にしてお
いたく。■Wet etching such as alkali etching is used to form the etch grooves 8. Since etching stops at the (111) plane, controllability is good. However, ■ In order to keep the depth of the etch groove 8 constant, the size of the contact opening should be kept constant.
Ｆ 通常拡散層は浅いのでエッチ溝８が拡散層５．６を
つきぬける事になるので、必要に応じて、Ｐ＋又はＢ”
４オンをＶ字溝８のみにイオン注入して拡散層５．６を
補償しておく。F Since the diffusion layer is usually shallow, the etch groove 8 will pass through the diffusion layer 5.6, so if necessary, P+ or B"
The diffusion layer 5.6 is compensated for by implanting 4-on ions only into the V-shaped groove 8.
なお、Ｖ字溝８のみでなく基板表面全体にイオン注入を
行って工程Ｃに変えて、ここの工程でＰＳＧ膜、ＢＳＧ
膜も同時に形成することも可能である。Note that ion implantation is performed not only on the V-shaped groove 8 but also on the entire substrate surface, and the process is changed to step C.
It is also possible to form a film at the same time.
Ｇ リフロー後ＡＩ配線層９を形成する。G: Form AI wiring layer 9 after reflow.
本発明のコンタクト方法によれば、コンタクトにさける
面積が微細であっても、配線層と基板の間に確実なコン
タクトをとることができる。そして直立段差が小さくな
るため上層の配線のカバレンジも従来のコンタクト方法
に比較して格段に向上する。また本発明のコンタクト形
成方法は従来のような複雑な方法を必要としないばかり
でなく、エツチングの制御性が良いため生産歩留りの向
上に寄与する。According to the contact method of the present invention, reliable contact can be made between the wiring layer and the substrate even if the area to be avoided for contact is minute. Furthermore, since the vertical height difference is reduced, the coverage of the upper layer wiring is also significantly improved compared to the conventional contact method. Furthermore, the contact forming method of the present invention not only does not require complicated methods as in the prior art, but also has good etching controllability, contributing to an improvement in production yield.
第１図Ａ−Ｇは本発明の半導体装置の製造方法を示す。
第２図は従来の微細コンタクトの構造を示す。
第３図は従来の微細コンタクトの構造を示す。
第４図Ａ−Ｃは従来の微細コンタクトの構造を示す。
１・・・Ｍ４７ｉ ２・・・チャンネル
ストッパ３・・・フィールド酸化膜
４・・・多結晶Ｓｉ ５・・・ソース領域６・
・・ドレイン領域 ７・・・ＰＳＧ膜８・・・■エッ
チ溝 ９・・・＾ｌ配線層１０・・・ＳｉＯ□ｖ１
．１１・・・フォトレジスト１２・・・スルーホール部1A to 1G show a method of manufacturing a semiconductor device according to the present invention. FIG. 2 shows the structure of a conventional fine contact. FIG. 3 shows the structure of a conventional fine contact. FIGS. 4A-4C show the structure of a conventional microcontact. 1...M47i 2...Channel stopper 3...Field oxide film 4...Polycrystalline Si 5...Source region 6.
...Drain region 7...PSG film 8...■ Etch groove 9...^l wiring layer 10...SiO□v1
．． 11... Photoresist 12... Through hole part
Claims (1)
を介してコンタクトをとる半導体装置において、 上記開口部に隣接する上記下層の導電層に傾斜部分を有
する溝部を設け、該溝部において、上記上層の導電層が
、上記下層の導電層とコンタクトしていることを特徴と
する半導体装置。 ２）下層の導電層と上層の導電層を絶縁層に設けた開口
を介してコンタクトをとる半導体装置の製造方法におい
て、 上記開口部に隣接する上記下層の導電層に傾斜部分を有
する溝部を設け、 上記導電層を下記導電層にコンタクトさせることを特徴
とする半導体装置の製造方法。[Claims] 1) A semiconductor device in which a lower conductive layer and an upper conductive layer are brought into contact through an opening provided in an insulating layer, wherein the lower conductive layer adjacent to the opening has a sloped portion. A semiconductor device characterized in that a groove is provided, and the upper conductive layer is in contact with the lower conductive layer in the groove. 2) In a method for manufacturing a semiconductor device in which a lower conductive layer and an upper conductive layer are brought into contact through an opening provided in an insulating layer, a groove portion having an inclined portion is provided in the lower conductive layer adjacent to the opening. , A method for manufacturing a semiconductor device, characterized in that the conductive layer is brought into contact with the conductive layer described below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2957686A JPS62188267A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2957686A JPS62188267A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188267A true JPS62188267A (en) | 1987-08-17 |
Family
ID=12279930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2957686A Pending JPS62188267A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188267A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146353A (en) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | Semiconductor memory device |
| KR20030002519A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Forming method for transistor of semiconductor device |
-
1986
- 1986-02-13 JP JP2957686A patent/JPS62188267A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146353A (en) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | Semiconductor memory device |
| KR20030002519A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Forming method for transistor of semiconductor device |
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